JPH0856024A - Manufacture of integrated circuit - Google Patents
Manufacture of integrated circuitInfo
- Publication number
- JPH0856024A JPH0856024A JP6206132A JP20613294A JPH0856024A JP H0856024 A JPH0856024 A JP H0856024A JP 6206132 A JP6206132 A JP 6206132A JP 20613294 A JP20613294 A JP 20613294A JP H0856024 A JPH0856024 A JP H0856024A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- integrated circuit
- lower electrode
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路の製造方法に
関し、特に、微細なトンネル型ジョセフソン接合の製造
に適した集積回路の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a method of manufacturing an integrated circuit suitable for manufacturing a fine tunnel type Josephson junction.
【０００２】[0002]
【従来の技術】バイアススパッタ法による平坦化法を用
いた素子の製造方法の従来例は、例えば、特開平４−９
４１７７号公報などに述べられている。典型的な従来例
を図３（ａ）〜（ｃ）を用いて説明する。図３（ａ）に
示すように、基板３１上に、幅Ｗ、厚さｔの電極３２を
形成する。次に、この基板上にバイアススパッタ法で絶
縁膜３３を成膜する。図３（ｂ）は、この成膜過程の途
中を抜き出して示したものである。このバイアススパッ
タによる絶縁膜３３の成膜を、J. Vac. Sci. Technol.
誌、第１５巻、第３号、１１０５〜１１１２頁でC. Y.
Tingらが述べているような平坦化条件で行うとすると、
平坦化に必要な絶縁膜の厚さｄは下記の式（１）で表さ
れる。2. Description of the Related Art A conventional example of a method for manufacturing an element using a flattening method by a bias sputtering method is disclosed in, for example, Japanese Patent Laid-Open No. 4-9.
4177, etc. A typical conventional example will be described with reference to FIGS. As shown in FIG. 3A, an electrode 32 having a width W and a thickness t is formed on the substrate 31. Next, the insulating film 33 is formed on this substrate by the bias sputtering method. FIG. 3 (b) shows an extracted part of this film formation process. The formation of the insulating film 33 by this bias sputtering is described in J. Vac. Sci. Technol.
CY, Vol. 15, No. 3, pp. 1105-1112
If it is performed under the flattening condition described by Ting et al.,
The thickness d of the insulating film required for planarization is represented by the following formula (1).
【０００３】[0003]
【数１】ｄ＝（Ｗ／２）ｔａｎα＋ｔ … （１）## EQU1 ## d = (W / 2) tan α + t (1)
【０００４】ここで、αはバイアススパッタ時に段差部
に形成される傾斜面の角度である。この（１）式で表さ
れるｄの厚さの絶縁膜３３を成膜すると、図３（ｃ）で
示したように電極の平坦化が完了する。バイアススパッ
タによる平坦化法では、（１）式に示されているよう
に、平坦化に必要な絶縁膜３３の厚さは、平坦化すべき
電極幅に依存する。Here, α is the angle of the inclined surface formed in the step portion during bias sputtering. When the insulating film 33 having a thickness of d expressed by the equation (1) is formed, the planarization of the electrodes is completed as shown in FIG. In the flattening method by bias sputtering, the thickness of the insulating film 33 required for flattening depends on the electrode width to be flattened, as shown in the equation (1).
【０００５】[0005]
【発明が解決しようとする課題】従来例による絶縁膜厚
さｄを見積もってみると、通常層間絶縁膜として多用さ
れるＳｉＯ2のバイアススパッタでは、傾斜角αは約４
０度である。例えば、幅２μｍ、高さ３００ｎｍの電極
の平坦化には、（１）式から１１３９ｎｍ厚の絶縁膜が
必要であることがわかる。また、幅１０μｍ、高さ３０
０ｎｍの電極の平坦化には４４９５ｎｍ厚の絶縁膜の成
膜が必要であり、電極幅が大きくなるほど非常に厚い層
間絶縁膜の成膜が必要となり、非現実的である。When the insulating film thickness d according to the conventional example is estimated, in the bias sputtering of SiO 2 which is often used as an interlayer insulating film, the inclination angle α is about 4.
0 degrees. For example, in order to flatten an electrode having a width of 2 μm and a height of 300 nm, it is understood from the equation (1) that an insulating film having a thickness of 1139 nm is necessary. Also, width 10 μm, height 30
It is impractical to flatten the 0 nm electrode because it is necessary to form an insulating film having a thickness of 4495 nm, and as the electrode width increases, it is necessary to form an extremely thick interlayer insulating film.
【０００６】本発明は、バイアススパッタ平坦化法にお
ける下地段差幅依存性の影響を低減し、特にジョセフソ
ン接合の下部電極に代表されるような幅広の電極などの
段差に対して平坦な絶縁層を容易に形成し、信頼性の高
い集積回路を製造する方法を提供することを目的とす
る。The present invention reduces the influence of the step difference width dependence of the underlying layer in the bias sputtering flattening method, and in particular, an insulating layer which is flat with respect to the step difference of a wide electrode typified by the lower electrode of the Josephson junction. It is an object of the present invention to provide a method for easily forming a semiconductor device and manufacturing a highly reliable integrated circuit.
【０００７】[0007]
【課題を解決するための手段】本発明は、基板上に電極
および配線を形成する工程と、前記電極および配線によ
り生じる段差と少なくとも同じ厚みの絶縁膜を成膜する
工程と、前記電極および配線よりもひとまわり小さい開
口部を持つフォトレジストパターンを形成し、前記絶縁
膜を前記電極の厚みと同じ厚みだけエッチングする工程
と、前記絶縁膜をエッチングした後の表面段差をバイア
ススパッタ法により平坦化する工程とを含むことを特徴
とする集積回路の製造方法である。本発明においては、
電極および配線が超伝導材料で形成されていることを好
適とし、集積回路は、上部電極、下部電極およびその間
のトンネル障壁層からなるジョセフソン接合であること
を好適とする。According to the present invention, there are provided a step of forming electrodes and wirings on a substrate, a step of forming an insulating film having at least the same thickness as a step formed by the electrodes and wirings, and the electrodes and wirings. Forming a photoresist pattern having an opening smaller than the above size, etching the insulating film by the same thickness as the electrode, and flattening the surface step after etching the insulating film by a bias sputtering method. The method for manufacturing an integrated circuit is characterized by including the step of: In the present invention,
The electrodes and wirings are preferably formed of a superconducting material, and the integrated circuit is preferably a Josephson junction including an upper electrode, a lower electrode and a tunnel barrier layer between them.
【０００８】[0008]
【作用】本発明によれば、電極を層間絶縁膜に埋め込
み、電極により生じた段差の平坦化が従来よりも薄い層
間絶縁膜厚で可能である。したがって、上部に設ける配
線の段切れを防止することが可能であり、集積回路の信
頼性を向上させ、素子の多層配線化、高集積化が実現で
きる。また、本発明によれば、超伝導体からなる電極お
よび配線を層間絶縁膜に埋め込み、電極および配線によ
り生じた段差の平坦化が可能である。したがって、上部
に設ける配線の段切れを防止することが可能であり、超
伝導集積回路の信頼性を向上させ、素子の多層配線化、
高集積化が実現できる。さらに、層間絶縁膜を可能な限
り薄くできるので、超伝導素子で問題となる配線のイン
ダクタンスを低減させることができ、超伝導素子の高速
化を実現できる。According to the present invention, the electrodes can be embedded in the interlayer insulating film and the steps caused by the electrodes can be flattened with a thinner interlayer insulating film thickness than the conventional one. Therefore, it is possible to prevent disconnection of the wiring provided on the upper part, improve the reliability of the integrated circuit, and realize the multi-layer wiring and high integration of the element. Further, according to the present invention, it is possible to bury electrodes and wirings made of a superconductor in an interlayer insulating film and flatten the steps generated by the electrodes and wirings. Therefore, it is possible to prevent disconnection of the wiring provided on the upper portion, improve the reliability of the superconducting integrated circuit, and realize the multi-layer wiring of the element,
High integration can be realized. Furthermore, since the interlayer insulating film can be made as thin as possible, the inductance of the wiring, which is a problem in the superconducting element, can be reduced, and the speed of the superconducting element can be increased.
【０００９】本発明をトンネル型ジョセフソン接合に用
いた場合には、さらに効果的である。本発明では、ジョ
セフソン素子上に平坦な面を持つ層間絶縁膜を形成でき
るので、層間絶縁膜をエッチバックする、あるいは上部
電極より大きなコンタクトホールを形成するなどの工程
により、容易に接合上部電極と上部配線とのコンタクト
を得ることができる。したがって、従来のように高い位
置合わせ精度で上部電極より小さいコンタクトホールを
設ける必要がなく、素子の微細化に対する信頼性が非常
に高い。さらに、下地の段差が平坦化されているので、
上部に設ける配線の段切れを防止することが可能であ
り、集積回路の信頼性を向上させ、素子の多層配線化、
高集積化が実現できる。また、層間絶縁膜を可能な限り
薄くできるので、ジョセフソン素子の高速動作を妨げる
問題となる配線のインダクタンスを低減させることがで
き、素子の高速化を実現できる。It is even more effective when the present invention is applied to a tunnel type Josephson junction. According to the present invention, since the interlayer insulating film having a flat surface can be formed on the Josephson device, the junction upper electrode can be easily formed by a process such as etching back the interlayer insulating film or forming a contact hole larger than the upper electrode. And contact with the upper wiring can be obtained. Therefore, it is not necessary to provide a contact hole smaller than the upper electrode with high alignment accuracy as in the conventional case, and the reliability for miniaturization of the device is very high. Furthermore, since the steps of the base are flattened,
It is possible to prevent disconnection of the wiring provided in the upper part, improve the reliability of the integrated circuit, and realize multilayer wiring of the element,
High integration can be realized. Further, since the interlayer insulating film can be made as thin as possible, it is possible to reduce the inductance of the wiring, which becomes a problem that hinders the high speed operation of the Josephson device, and it is possible to realize high speed operation of the device.
【００１０】[0010]
【実施例】次に、本発明の実施例について、図面を参照
して詳細に説明する。 実施例１ 図２は本発明の第１の実施例を説明するための集積回路
の製造工程断面図である。図２（ａ）に示すように、基
板２１上に幅１０μｍ、高さ５００ｎｍの電極２２を形
成する。次に図２（ｂ）に示すように、電極２２の高さ
５００ｎｍ以上の絶縁膜２３を成膜する。この絶縁膜２
３の成膜には、気相成長（ＣＶＤ）法を用いてもよい
し、スパッタ法を用いてもよい。ここでは、例えばバイ
アススパッタ法を用いて、６００ｎｍのＳｉＯ2を堆積
させた。この時のバイアススパッタ条件は、基板バイア
スを印加しない通常のスパッタリングに対し、７〜８割
程度の成膜速度が得られるような基板バイアス、すなわ
ち図５のＶ１で示される基板バイアスを印加して成膜を
行った。このバイアススパッタ条件では、非常に段差被
覆性に優れた絶縁膜を成膜することができる。また、こ
のとき段差部分において形成される傾斜面の角度は約４
０度である。絶縁膜２３の成膜後、図２（ｃ）に示すよ
うに、前記の電極２２よりも両側で１μｍづつ小さい開
口部２５を持つフォトレジストパターン２４を形成す
る。続いて、図２（ｄ）のように、フォトレジストパタ
ーン２４をマスクとして、絶縁膜２３を電極２２の厚さ
と同じ５００ｎｍだけエッチングする。フォトレジスト
２４を除去した後に、バイアススパッタを行い、層間絶
縁膜２３をエッチングして生じた段差を平坦化する。こ
の工程でのバイアススパッタ条件は、平坦面での成膜速
度が０となるような基板バイアス、すなわち図５のＶ２
で示される基板バイアスを印加した。このバイアススパ
ッタ条件では、平坦面の高さは変化せず傾斜面が選択的
にエッチングされ、図６に示すように６０分間のバイア
ススパッタを行うことで幅４μｍ以下の突起部分を実用
的に平坦化できる。したがって、必要最小限の絶縁膜の
膜厚で図２（ｅ）のように平坦化された素子が得られ
る。Embodiments of the present invention will now be described in detail with reference to the drawings. Embodiment 1 FIG. 2 is a sectional view of a manufacturing process of an integrated circuit for explaining the first embodiment of the present invention. As shown in FIG. 2A, an electrode 22 having a width of 10 μm and a height of 500 nm is formed on the substrate 21. Next, as shown in FIG. 2B, an insulating film 23 having a height of the electrode 22 of 500 nm or more is formed. This insulating film 2
For the film formation of 3, the vapor phase growth (CVD) method or the sputtering method may be used. Here, for example, the bias sputtering method was used to deposit 600 nm of SiO 2 . The bias sputtering conditions at this time are such that a substrate bias that gives a film forming rate of about 70 to 80%, that is, a substrate bias shown by V1 in FIG. A film was formed. Under this bias sputtering condition, it is possible to form an insulating film having excellent step coverage. At this time, the angle of the inclined surface formed in the step portion is about 4
0 degrees. After forming the insulating film 23, as shown in FIG. 2C, a photoresist pattern 24 having an opening 25 smaller by 1 μm on both sides than the electrode 22 is formed. Subsequently, as shown in FIG. 2D, the insulating film 23 is etched by 500 nm, which is the same as the thickness of the electrode 22, using the photoresist pattern 24 as a mask. After removing the photoresist 24, bias sputtering is performed to flatten the step generated by etching the interlayer insulating film 23. The bias sputtering conditions in this step are the substrate bias such that the film formation rate on the flat surface becomes 0, that is, V2 in FIG.
The substrate bias shown by was applied. Under this bias sputtering condition, the height of the flat surface does not change and the inclined surface is selectively etched. As shown in FIG. 6, by performing bias sputtering for 60 minutes, the protrusions with a width of 4 μm or less are practically flattened. Can be converted. Therefore, a flattened element as shown in FIG. 2E can be obtained with the minimum necessary insulating film thickness.
【００１１】本実施例において、最後のバイアススパッ
タによる平坦化の工程では、図５のＶ２で示される基板
バイアスを印加した。絶縁膜の厚さが問題にならない場
合には、図５のＶ１で示される基板バイアスで平坦化を
行ってもかまわない。基板バイアスＶ１で平坦化する際
に必要な絶縁膜の厚さは（１）式で表され、本実施例で
は幅１μｍ、高さ５００ｎｍの段差を平坦化することに
なるため、さらに９２０ｎｍの絶縁膜を基板バイアスＶ
１でバイアススパッタ法で成膜し、素子の平坦化を行
う。In this embodiment, in the final step of flattening by bias sputtering, a substrate bias indicated by V2 in FIG. 5 was applied. If the thickness of the insulating film does not matter, planarization may be performed by the substrate bias indicated by V1 in FIG. The thickness of the insulating film required for flattening with the substrate bias V1 is expressed by equation (1). In this embodiment, a step having a width of 1 μm and a height of 500 nm is flattened. Substrate bias V
In 1, the film is formed by the bias sputtering method, and the element is flattened.
【００１２】フォトレジストパターン２４の開口部２５
の大きさは、使用する露光機の目合わせ精度で決定され
る。本実施例では、目合わせ精度０．５μｍと安全マー
ジン０．５μｍを想定して電極２２に対して片側で１μ
ｍづつ縮小した開口部２５を設けた。露光機の目合わせ
精度の許す限りフォトレジストパターン２４の開口部２
５の大きさを電極２２の大きさに近づけて、最終的にバ
イアススパッタで平坦化される段差幅を小さくすればす
るほど平坦化に有利であることは言うまでもない。Opening 25 of photoresist pattern 24
Is determined by the alignment accuracy of the exposure machine used. In the present embodiment, assuming that the alignment accuracy is 0.5 μm and the safety margin is 0.5 μm, it is 1 μ on one side with respect to the electrode 22.
The opening 25 reduced by m was provided. The opening 2 of the photoresist pattern 24 as far as the aligning accuracy of the exposure machine allows.
Needless to say, the closer the size of 5 to the size of the electrode 22 and the smaller the step width finally flattened by bias sputtering, the more advantageous the flattening is.
【００１３】さらに、図６から明らかなように、平坦化
されるべき電極２２の幅が２μｍ未満である場合には、
フォトレジストパターン２４に開口部２５を設ける必要
はない。電極２２の幅が２μｍ以上４μｍ未満である場
合にはフォトレジストパターン２４に開口部２５を設け
ずとも実用上充分な平坦化が行えるが、可能な限り開口
部２５を設けた方が、より平坦な層間絶縁膜が得られ
る。本発明は、幅が３μｍ以上の突起部分の平坦化に対
して非常に有効である。尚、この第１の実施例におい
て、電極２２を構成する物質として超伝導体材料を用い
る場合にも、上記と同様の工程で超伝導集積回路が製造
される。Further, as is apparent from FIG. 6, when the width of the electrode 22 to be flattened is less than 2 μm,
It is not necessary to provide the opening 25 in the photoresist pattern 24. When the width of the electrode 22 is 2 μm or more and less than 4 μm, the photoresist pattern 24 can be sufficiently flattened in practice without providing the opening 25, but the opening 25 is flatter as much as possible. A good interlayer insulating film can be obtained. The present invention is very effective for flattening a protrusion having a width of 3 μm or more. In the first embodiment, even when a superconductor material is used as the substance forming the electrode 22, the superconducting integrated circuit is manufactured by the same steps as above.
【００１４】実施例２ 図１は本発明の第２の実施例を説明するためのトンネル
型ジョセフソン接合の製造における集積回路の製造工程
断面図である。本発明は、トンネル型ジョセフソン接合
のように階段状に複数の段差が生じる集積回路の製造に
も適している。図１（ａ）に示すように、基板１１上に
ジョセフソン接合を形成する。この接合の下部電極１２
の幅は１０μｍ、高さは３００ｎｍ、障壁層１３の幅は
３μｍ、高さは９ｎｍ、上部電極１４の幅は２μｍ、高
さは２００ｎｍとする。次に図１（ｂ）に示すように、
下部電極１２、障壁層１３、上部電極１４を合わせたジ
ョセフソン接合の高さ５０９ｎｍ以上の厚みをもつ絶縁
膜１５を成膜する。この絶縁膜１５の成膜には、気相成
長（ＣＶＤ）法を用いてもよいし、スパッタ法を用いて
もよい。ここでは、例えばバイアススパッタ法を用い
て、６００ｎｍのＳｉＯ2を堆積させた。この時のバイ
アススパッタ条件は、基板バイアスを印加しない通常の
スパッタリングに対し７〜８割程度の成膜速度が得られ
るような基板バイアス、すなわち図５のＶ１で示される
基板バイアスを印加して成膜を行った。このバイアスス
パッタ条件では、非常に段差被覆性に優れた絶縁膜を成
膜することができる。また、このとき段差部において形
成される傾斜面の角度は約４０度である。絶縁膜１５の
成膜後、図１（ｃ）に示すような下部電極１２よりも両
側で１μｍづつ小さい開口部１７を持つフォトレジスト
パターン１６を形成する。続いて、図１（ｄ）のよう
に、フォトレジストパターン１６をマスクとして、絶縁
膜１５を下部電極１２の厚さと同じ３００ｎｍだけエッ
チングする。フォトレジスト１６を除去した後に、バイ
アススパッタを行い、層間絶縁膜１５をエッチングして
生じた段差および上部電極１４により生じた段差を平坦
化する。この工程でのバイアススパッタ条件は、平坦面
での成膜速度が０となるような基板バイアス、すなわち
図５のＶ２で示される基板バイアスを印加した。このバ
イアススパッタ条件では、平坦面の高さは変化せず傾斜
面が選択的にエッチングされ、図６に示すように、６０
分間のバイアススパッタを行うことで幅４μｍ以下の突
起部分を実用的に平坦化できる。したがって、絶縁膜１
５のエッチングにより下部電極１２の両端に形成された
段差および幅４μｍ以下の上部電極１４により生じた段
差は容易に平坦化される。その結果、必要最小限の膜厚
の絶縁膜で図１（ｅ）のように平坦化されたジョセフソ
ン接合が得られる。Embodiment 2 FIG. 1 is a cross-sectional view of manufacturing steps of an integrated circuit in manufacturing a tunnel type Josephson junction for explaining a second embodiment of the present invention. The present invention is also suitable for manufacturing an integrated circuit in which a plurality of steps are formed stepwise like a tunnel type Josephson junction. As shown in FIG. 1A, a Josephson junction is formed on the substrate 11. Lower electrode 12 of this junction
Has a width of 10 μm and a height of 300 nm, the barrier layer 13 has a width of 3 μm and a height of 9 nm, and the upper electrode 14 has a width of 2 μm and a height of 200 nm. Next, as shown in FIG.
An insulating film 15 having a Josephson junction height of 509 nm or more including the lower electrode 12, the barrier layer 13, and the upper electrode 14 is formed. The insulating film 15 may be formed by a vapor deposition (CVD) method or a sputtering method. Here, for example, the bias sputtering method was used to deposit 600 nm of SiO 2 . The bias sputtering conditions at this time are set by applying a substrate bias such that a film forming rate of about 70 to 80% can be obtained as compared with normal sputtering in which no substrate bias is applied, that is, a substrate bias shown by V1 in FIG. The membrane was made. Under this bias sputtering condition, it is possible to form an insulating film having excellent step coverage. Further, at this time, the angle of the inclined surface formed in the step portion is about 40 degrees. After forming the insulating film 15, a photoresist pattern 16 having openings 17 smaller than the lower electrode 12 by 1 μm on both sides as shown in FIG. 1C is formed. Subsequently, as shown in FIG. 1D, the insulating film 15 is etched by 300 nm, which is the same as the thickness of the lower electrode 12, using the photoresist pattern 16 as a mask. After removing the photoresist 16, bias sputtering is performed to flatten the step created by etching the interlayer insulating film 15 and the step created by the upper electrode 14. As the bias sputtering conditions in this step, a substrate bias such that the film formation rate on the flat surface was 0, that is, a substrate bias indicated by V2 in FIG. 5 was applied. Under this bias sputtering condition, the height of the flat surface does not change and the inclined surface is selectively etched. As shown in FIG.
By performing bias sputtering for a period of time, it is possible to practically flatten the protruding portion having a width of 4 μm or less. Therefore, the insulating film 1
The step formed on both ends of the lower electrode 12 and the step formed by the upper electrode 14 having a width of 4 μm or less by the etching of 5 are easily flattened. As a result, a flattened Josephson junction as shown in FIG. 1E can be obtained with the insulating film having the minimum necessary thickness.
【００１５】本実施例において、最後のバイアススパッ
タによる平坦化の工程では、図５のＶ２で示される基板
バイアスを印加した。絶縁膜の厚さが問題にならない場
合には、図５のＶ１で示される基板バイアスで平坦化を
行ってもかまわない。In this embodiment, in the final planarization step by bias sputtering, a substrate bias indicated by V2 in FIG. 5 was applied. If the thickness of the insulating film does not matter, planarization may be performed by the substrate bias indicated by V1 in FIG.
【００１６】フォトレジストパターン１６の開口部１７
の大きさは、使用する露光機の目合わせ精度で決定され
る。本実施例では、目合わせ精度０．５μｍと安全マー
ジン０．５μｍを想定して下部電極１２に対して片側で
１μｍづつ縮小した開口部１７を設けた。露光機の目合
わせ精度の許す限りフォトレジストパターン１６の開口
部１７の大きさを下部電極１２の大きさに近づけて、最
終的にバイアススパッタで平坦化される段差幅を小さく
すればするほど平坦化に有利であることは言うまでもな
い。Opening 17 of photoresist pattern 16
Is determined by the alignment accuracy of the exposure machine used. In this embodiment, the opening 17 is provided which is reduced by 1 μm on each side with respect to the lower electrode 12 in consideration of the alignment accuracy of 0.5 μm and the safety margin of 0.5 μm. As far as the alignment accuracy of the exposure machine allows, the size of the opening 17 of the photoresist pattern 16 is made closer to the size of the lower electrode 12, and the step width finally flattened by bias sputtering is made smaller. Needless to say, it is advantageous for the realization.
【００１７】ジョセフソン接合を用いた集積回路では、
上部電極１４の幅は通常４μｍ以下である。したがっ
て、図６から明らかなように、上部電極１４は容易に平
坦化される。幅４μｍ以上の上部電極が必要である場合
には、図１（ｃ）で示した工程の後に、図４で示したよ
うに、上部電極１４に対してもひとまわり小さい開口部
１９を持つフォトレジストパターン１８を形成し、層間
絶縁膜１５を上部電極１４と障壁層１３を合わせた高さ
と同じ膜厚をエッチングした後に、バイアススパッタ平
坦化を行うことで対応できる。In an integrated circuit using Josephson junction,
The width of the upper electrode 14 is usually 4 μm or less. Therefore, as is apparent from FIG. 6, the upper electrode 14 is easily flattened. When an upper electrode having a width of 4 μm or more is required, as shown in FIG. 4, after the step shown in FIG. 1C, a photo having an opening 19 which is slightly smaller than the upper electrode 14 is formed. This can be dealt with by forming the resist pattern 18 and etching the interlayer insulating film 15 to the same film thickness as the combined height of the upper electrode 14 and the barrier layer 13, and then performing bias sputtering flattening.
【００１８】さらに、図６から明らかなように、平坦化
されるべき下部電極１２の幅が２μｍ未満である場合に
は、フォトレジストパターン１６に開口部１７を設ける
必要はない。下部電極１２の幅が２μｍ以上４μｍ未満
である場合にはフォトレジストパターン１６に開口部１
７を設けずとも実用上充分な平坦化が行えるが、可能な
限り開口部１７を設けた方が、より平坦な層間絶縁膜が
得られる。本発明は、幅が３μｍ以上の突起部分の平坦
化に対して非常に有効である。Further, as apparent from FIG. 6, when the width of the lower electrode 12 to be flattened is less than 2 μm, it is not necessary to provide the opening 17 in the photoresist pattern 16. When the width of the lower electrode 12 is 2 μm or more and less than 4 μm, the opening 1 is formed in the photoresist pattern 16.
Although it is possible to achieve sufficient planarization practically without providing 7, it is possible to obtain a flatter interlayer insulating film by providing the opening 17 as much as possible. The present invention is very effective for flattening a protrusion having a width of 3 μm or more.
【００１９】[0019]
【発明の効果】以上説明したように、本発明の集積回路
の製造方法によれば、非常に幅の広い電極に対してもバ
イアススパッタ法で平坦化を行うことが可能である。こ
の時必要とされる層間絶縁膜の厚さは、電気絶縁上必要
最小限の膜厚であり、通常のバイアススパッタ平坦化に
見られるような著しい段差幅依存性は生じない。したが
って、上部に設ける配線の段切れを防止することが可能
であり、集積回路の信頼性を向上させ、素子の多層配線
化、高集積化が実現できる。さらに、本発明の集積回路
の製造方法によれば、非常に幅の広い超伝導電極に対し
てもバイアススパッタ法で平坦化を行うことが可能であ
る。したがって、上部に設ける配線の段切れを防止する
ことが可能であり、集積回路の信頼性を向上させ、超伝
導素子の多層配線化、高集積化が実現できる。また、層
間絶縁膜を可能な限り薄くできるので、超伝導素子で問
題となる配線のインダクタンスを低減させることがで
き、素子の高速化を実現できる。また、本発明の製造方
法によれば、非常に幅の広い下部電極をもち、階段状の
段差を有するトンネル型ジョセフソン素子に対しても、
バイアススパッタ法で平坦化を行うことが可能である。
この時必要とされる層間絶縁膜の厚さは、電気絶縁上必
要最小限の膜厚であり、通常のバイアススパッタ平坦化
に見られるような著しい下部電極幅依存性は生じない。
また、非常に幅の広い上部電極を有するトンネル型ジョ
セフソン素子に対しても、本発明の工程の一部分を追加
することで、バイアススパッタ法で平坦化を行うことが
可能であり、素子設計上の自由度の高い平坦化方法を提
供できた。その結果、ジョセフソン素子上に平坦な面を
持つ層間絶縁膜を形成できるので、層間絶縁膜をエッチ
バックする、あるいは上部電極より大きなコンタクトホ
ールを形成して、容易に接合上部電極と上部配線とのコ
ンタクトを得ることが可能である。したがって、従来の
ように高い位置合わせ精度で上部電極より小さいコンタ
クトホールを設ける必要がなく、素子の微細化に対する
信頼性が非常に高い。さらに、下地の段差が平坦化され
ているので、上部に設ける配線の段切れを防止すること
が可能であり、集積回路の信頼性を向上させ、素子の多
層配線化、高集積化が実現できる。また、層間絶縁膜を
可能な限り薄くできるので、ジョセフソン素子の高速動
作を妨げる問題となる配線のインダクタンスを低減させ
ることができ、素子の高速化を実現できる。As described above, according to the method of manufacturing an integrated circuit of the present invention, even a very wide electrode can be planarized by the bias sputtering method. The thickness of the interlayer insulating film required at this time is the minimum film thickness necessary for electrical insulation, and does not have the remarkable step width dependency as seen in normal bias sputtering flattening. Therefore, it is possible to prevent disconnection of the wiring provided on the upper part, improve the reliability of the integrated circuit, and realize the multi-layer wiring and high integration of the element. Furthermore, according to the integrated circuit manufacturing method of the present invention, even a superconducting electrode having an extremely wide width can be planarized by the bias sputtering method. Therefore, it is possible to prevent disconnection of the wiring provided on the upper portion, improve the reliability of the integrated circuit, and realize multi-layer wiring and high integration of the superconducting element. Moreover, since the interlayer insulating film can be made as thin as possible, the inductance of the wiring, which is a problem in the superconducting element, can be reduced, and the element can be speeded up. Further, according to the manufacturing method of the present invention, even for a tunnel type Josephson element having a step electrode having a very wide lower electrode,
It is possible to perform flattening by the bias sputtering method.
The thickness of the interlayer insulating film required at this time is the minimum film thickness necessary for electrical insulation, and does not cause a remarkable lower electrode width dependency as seen in normal bias sputtering flattening.
Further, even for a tunnel type Josephson element having an extremely wide upper electrode, it is possible to perform flattening by a bias sputtering method by adding a part of the process of the present invention. It was possible to provide a flattening method with a high degree of freedom. As a result, an interlayer insulating film having a flat surface can be formed on the Josephson element, so that the interlayer insulating film is etched back or a contact hole larger than the upper electrode is formed, so that the bonding upper electrode and the upper wiring can be easily formed. It is possible to get the contact of. Therefore, it is not necessary to provide a contact hole smaller than the upper electrode with high alignment accuracy as in the conventional case, and the reliability for miniaturization of the device is very high. Further, since the step of the base is flattened, it is possible to prevent disconnection of the wiring provided on the upper part, improve the reliability of the integrated circuit, and realize multi-layer wiring and high integration of the element. . Further, since the interlayer insulating film can be made as thin as possible, it is possible to reduce the inductance of the wiring, which becomes a problem that hinders the high speed operation of the Josephson device, and it is possible to realize high speed operation of the device.
【図１】本発明の第２の実施例の製造方法の工程断面図
である。FIG. 1 is a process sectional view of a manufacturing method according to a second embodiment of the present invention.
【図２】本発明の第１の実施例の製造方法の工程断面図
である。FIG. 2 is a process sectional view of the manufacturing method according to the first embodiment of the present invention.
【図３】従来例による製造方法の工程断面図であるFIG. 3 is a process sectional view of a manufacturing method according to a conventional example.
【図４】本発明の別の実施例を説明するための基板断面
図である。FIG. 4 is a sectional view of a substrate for explaining another embodiment of the present invention.
【図５】本発明の実施例におけるバイアススパッタ条件
を説明するための図である。FIG. 5 is a diagram for explaining bias sputtering conditions in an example of the present invention.
【図６】本発明の実施例におけるバイアススパッタ条件
での平坦化を説明する図である。FIG. 6 is a diagram illustrating flattening under bias sputtering conditions in an example of the present invention.
１１ 基板 １２ 下部電極 １３ 障壁層 １４ 上部電極 １５ 絶縁膜 １６ フォトレジストパターン １７ 開口部 １８ フォトレジストパターン １９ 開口部 ２１ 基板 ２２ 電極 ２３ 絶縁膜 ２４ フォトレジストパターン ２５ 開口部 ３１ 基板 ３２ 電極 ３３ 絶縁膜 11 Substrate 12 Lower Electrode 13 Barrier Layer 14 Upper Electrode 15 Insulating Film 16 Photoresist Pattern 17 Opening 18 Photoresist Pattern 19 Opening 21 Substrate 22 Electrode 23 Insulating Film 24 Photoresist Pattern 25 Opening 31 Substrate 32 Electrode 33 Insulating Film
Claims (3)
と、前記電極および配線により生じる段差と少なくとも
同じ厚みの絶縁膜を成膜する工程と、前記電極および配
線よりもひとまわり小さい開口部を持つフォトレジスト
パターンを形成し、前記絶縁膜を前記電極の厚みと同じ
厚みだけエッチングする工程と、前記絶縁膜をエッチン
グした後の表面段差をバイアススパッタ法により平坦化
する工程とを含むことを特徴とする集積回路の製造方
法。1. A step of forming an electrode and a wiring on a substrate, a step of forming an insulating film having at least the same thickness as a step formed by the electrode and the wiring, and an opening slightly smaller than the electrode and the wiring. A step of forming a photoresist pattern having the same and etching the insulating film by the same thickness as the thickness of the electrode; and a step of flattening a surface step after etching the insulating film by a bias sputtering method. Manufacturing method of integrated circuit.
ている請求項１記載の集積回路の製造方法。2. The method for manufacturing an integrated circuit according to claim 1, wherein the electrodes and the wirings are made of a superconducting material.
その間のトンネル障壁層からなるジョセフソン接合であ
る請求項２記載の集積回路の製造方法。3. The method for manufacturing an integrated circuit according to claim 2, wherein the integrated circuit is a Josephson junction composed of an upper electrode, a lower electrode and a tunnel barrier layer between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6206132A JPH0856024A (en) | 1994-08-09 | 1994-08-09 | Manufacture of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6206132A JPH0856024A (en) | 1994-08-09 | 1994-08-09 | Manufacture of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0856024A true JPH0856024A (en) | 1996-02-27 |
Family
ID=16518321
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6206132A Pending JPH0856024A (en) | 1994-08-09 | 1994-08-09 | Manufacture of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0856024A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005039244A (en) * | 2003-06-27 | 2005-02-10 | Hitachi Ltd | Electronic device and method of forming multilayer wiring |
| WO2014082357A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| WO2014082352A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854965A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200440A (en) * | 1983-04-28 | 1984-11-13 | Agency Of Ind Science & Technol | Manufacture of wiring structure |
| JPH0239551A (en) * | 1988-07-29 | 1990-02-08 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
-
1994
- 1994-08-09 JP JP6206132A patent/JPH0856024A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59200440A (en) * | 1983-04-28 | 1984-11-13 | Agency Of Ind Science & Technol | Manufacture of wiring structure |
| JPH0239551A (en) * | 1988-07-29 | 1990-02-08 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005039244A (en) * | 2003-06-27 | 2005-02-10 | Hitachi Ltd | Electronic device and method of forming multilayer wiring |
| WO2014082357A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| WO2014082352A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854966A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854965A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854967A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
| US9406549B2 (en) | 2012-11-30 | 2016-08-02 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
| US9633855B2 (en) | 2012-11-30 | 2017-04-25 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
| US10068803B2 (en) | 2012-11-30 | 2018-09-04 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
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