JPH04303920A - Insulating film/iii-v compound semiconductor stacked structure on group iv substrate - Google Patents
Insulating film/iii-v compound semiconductor stacked structure on group iv substrateInfo
- Publication number
- JPH04303920A JPH04303920A JP9334491A JP9334491A JPH04303920A JP H04303920 A JPH04303920 A JP H04303920A JP 9334491 A JP9334491 A JP 9334491A JP 9334491 A JP9334491 A JP 9334491A JP H04303920 A JPH04303920 A JP H04303920A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- group
- iii
- substrate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 150000001875 compounds Chemical class 0.000 title claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 43
- 239000010408 film Substances 0.000 claims description 63
- 239000010409 thin film Substances 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 56
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 53
- 229910052681 coesite Inorganic materials 0.000 abstract description 28
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 28
- 239000000377 silicon dioxide Substances 0.000 abstract description 28
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 28
- 229910052682 stishovite Inorganic materials 0.000 abstract description 28
- 229910052905 tridymite Inorganic materials 0.000 abstract description 28
- 238000000034 method Methods 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- KAXRWMOLNJZCEW-UHFFFAOYSA-N 2-amino-4-(2-aminophenyl)-4-oxobutanoic acid;sulfuric acid Chemical compound OS(O)(=O)=O.OC(=O)C(N)CC(=O)C1=CC=CC=C1N KAXRWMOLNJZCEW-UHFFFAOYSA-N 0.000 description 3
- FOJZPLNOZUNMJO-UHFFFAOYSA-M chloro(dimethyl)indigane Chemical compound [Cl-].C[In+]C FOJZPLNOZUNMJO-UHFFFAOYSA-M 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- OTRPZROOJRIMKW-UHFFFAOYSA-N triethylindigane Chemical compound CC[In](CC)CC OTRPZROOJRIMKW-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はＩＶ族半導体単結晶基板
上に形成された高品質かつ大面積なＩＩＩ −Ｖ族化合
物半導体単結晶表面を有する絶縁膜／ＩＩＩ −Ｖ族化
合物半導体積層構造に関する。[Field of Industrial Application] The present invention relates to an insulating film/III-V compound semiconductor stacked structure having a high-quality, large-area III-V compound semiconductor single-crystal surface formed on a group-IV semiconductor single-crystal substrate. .
【０００２】0002
【従来の技術】現在、Ｓｉに代表されるＩＶ族半導体単
結晶基板上にＧａＡｓに代表されるＩＩＩ−Ｖ族化合物
半導体単結晶薄膜を形成する試みが活発に行なわれてい
る。
これは、このような薄膜構造が形成できると、ＩＩＩ
−Ｖ族化合物半導体高機能素子を安価なＳｉ基板上に作
製でき、またＳｉの高い熱伝導率によって光素子等の性
能向上が期待できるためである。さらにＳｉ基板上に選
択的にＩＩＩ −Ｖ族化合物半導体単結晶薄膜を形成で
きれば、Ｓｉ超高集積回路とＩＩＩ −Ｖ族化合物半導
体超高速素子や光素子を同一基板上に形成できるため、
新しい高機能素子の開発が予測されるからである。2. Description of the Related Art At present, attempts are being made to form single crystal thin films of group III-V compound semiconductors such as GaAs on single crystal substrates of group IV semiconductors such as Si. This means that if such a thin film structure can be formed, III
This is because a high-performance -V group compound semiconductor device can be fabricated on an inexpensive Si substrate, and the high thermal conductivity of Si can be expected to improve the performance of optical devices and the like. Furthermore, if a III-V group compound semiconductor single crystal thin film can be selectively formed on a Si substrate, a Si ultra-high integrated circuit and a III-V group compound semiconductor ultra-high-speed device or optical device can be formed on the same substrate.
This is because the development of new high-performance devices is predicted.
【０００３】しかしながら、ＩＩＩ −Ｖ族化合物半導
体結晶はＩＩＩ 族とＶ族の２種類の元素から成る有極
性結晶であるのに対し、ＩＶ族半導体単結晶基板は単一
元素から成る無極性結晶である。従って、通常用いられ
る（１００） 面方位を有するＩＶ族半導体単結晶基板
上にＩＩＩ −Ｖ族化合物半導体単結晶薄膜をエピタキ
シャル成長させようとする場合、ＩＩＩ 族とＶ族の配
列の位相がずれ、極性が反転した領域、いわゆるアンチ
・フェイズ・ドメインができやすく、全基板面内でＩＩ
Ｉ 族とＶ族の配列の位相がそろったいわゆるシングル
・ドメイン単結晶薄膜を確実に得ることはごく最近まで
は困難であった。However, while III-V compound semiconductor crystals are polar crystals made of two types of elements, Group III and V, group IV semiconductor single crystal substrates are nonpolar crystals made of a single element. be. Therefore, when attempting to epitaxially grow a III-V group compound semiconductor single crystal thin film on a commonly used group IV semiconductor single crystal substrate having a (100) plane orientation, the phase of the group III and group V arrangements is shifted, resulting in polarity. A so-called anti-phase domain, which is a region where the
Until very recently, it has been difficult to reliably obtain so-called single domain single crystal thin films in which the I and V groups are aligned in phase.
【０００４】この問題を解決するために考えられたのが
雑誌「ジャパニーズ・ジャーナル・オブ・アプライド・
フィジクス（Ｊｐｎ．Ｊ．Ａｐｐｌ．Ｐｈｙｓ．）」第
２４巻第６号（１９８５年）第Ｌ３９１−３９３頁に説
明されている「二段階成長法」と呼ばれる方法である。
すなわちＳｉ単結晶基板の温度を４５０℃以下の低温と
してまず２０ｎｍ程度の微細な多結晶もしくは非晶質状
のＧａＡｓバッファ層を堆積した後、Ｓｉ単結晶基板の
温度を通常の成長温度、上記文献の場合は６００℃とし
てＧａＡｓ単結晶薄膜を成長させる方法である。この方
法によってシングル・ドメイン単結晶薄膜を確実に得る
ことができるようになった。微細な多結晶もしくは非晶
質状のＧａＡｓ薄膜は温度を６００℃に昇温する間にア
ニールされて単結晶化する。上記文献の結果はＭＯＣＶ
Ｄ法によるものであったが、以後ＭＢＥ法でも同様に二
段階成長法が有効であることが確認された。[0004] The magazine ``Japanese Journal of Applied Science'' was devised to solve this problem.
This is a method called the "two-step growth method" described in "Physics (Jpn. J. Appl. Phys.)", Vol. 24, No. 6 (1985), pp. L391-393. That is, after setting the temperature of the Si single crystal substrate to a low temperature of 450° C. or less and depositing a fine polycrystalline or amorphous GaAs buffer layer of about 20 nm, the temperature of the Si single crystal substrate was set to the normal growth temperature, and then the temperature of the Si single crystal substrate was set to a low temperature of 450° C. In this case, a GaAs single crystal thin film is grown at 600°C. This method has made it possible to reliably obtain single-domain single-crystal thin films. The fine polycrystalline or amorphous GaAs thin film is annealed and turned into a single crystal while the temperature is raised to 600°C. The results of the above literature are MOCV
Although this method was based on the D method, it has since been confirmed that the two-step growth method is similarly effective for the MBE method.
【０００５】ところで半導体薄膜の素子応用の観点から
はシングル・ドメイン化とともに結晶品質の向上が重要
である。しかし通常Ｓｉ基板上にＧａＡｓなどのＩＩＩ
−Ｖ族化合物半導体を成長すると、ＳｉとＧａＡｓの
界面には基板と成長層との格子不整合から予想されるよ
りはるかに多くの転位や積層欠陥が発生し、さらにその
一部は容易に上層まで伸びて貫通転位となる。二段階成
長法で成長したＧａＡｓ層の転位密度は数ｕｍ厚の成長
表面で約１０８ ｃｍ−２にも達する。その後、歪超格
子層の挿入や熱サイクルアニールの導入で約１０６ ｃ
ｍ−２まで転位密度は急速に改善された。しかしこの１
０６ ｃｍ−２を大きな壁としてその後は進展が見られ
ない状態にある。From the viewpoint of device applications of semiconductor thin films, it is important to improve crystal quality as well as to create a single domain. However, it is common to use III such as GaAs on a Si substrate.
- When a group V compound semiconductor is grown, far more dislocations and stacking faults occur at the interface between Si and GaAs than would be expected from the lattice mismatch between the substrate and the grown layer, and some of them are easily formed in the upper layer. It extends to a threading dislocation. The dislocation density of the GaAs layer grown by the two-step growth method reaches approximately 108 cm-2 on the growth surface of several um thick. After that, by inserting a strained superlattice layer and introducing thermal cycle annealing, the
The dislocation density improved rapidly up to m-2. But this one
06 cm-2 has become a major barrier and no progress has been seen since then.
【０００６】この貫通転位の問題を回避する１つの方法
として注目されるのがＧａＡｓ／絶縁膜／Ｓｉ基板構造
の採用である。この様な構造は基板の露出したシード部
分から絶縁膜マスク上へ横方向成長を行なうことで形成
することができる。たとえば雑誌「ジャパニーズ・ジャ
ーナル・オブ・アプライド・フィジクス（Ｊｐｎ．Ｊ．
Ａｐｐｌ．Ｐｈｙｓ．）」第２８巻第３号（１９８９年
）の第Ｌ３３７−３３９頁に説明されているように、液
相成長法（ＬＰＥ法）でマスク上へ横方向成長して形成
したＧａＡｓ／絶縁膜／Ｓｉ構造部分のＧａＡｓ膜はほ
ぼ無転位となることが報告されている。ＧａＡｓ／Ｓｉ
界面で発生した転位は主にシード部分の上方のみに伸び
、横方向には伸びないためである。One method to avoid this problem of threading dislocations is to employ a GaAs/insulating film/Si substrate structure. Such a structure can be formed by lateral growth from an exposed seed portion of the substrate onto an insulating film mask. For example, the magazine ``Japanese Journal of Applied Physics (Jpn.J.
Appl. Phys. ), Vol. 28, No. 3 (1989), pages L337-339, GaAs/insulating film/ It has been reported that the GaAs film in the Si structure portion has almost no dislocations. GaAs/Si
This is because dislocations generated at the interface mainly extend only above the seed portion and do not extend laterally.
【０００７】[0007]
【発明が解決しようとする課題】Ｓｉ基板上に良質のＩ
ＩＩ −Ｖ族化合物半導体薄膜を得るために採用された
上記従来構造の問題点を考えてみる。[Problem to be solved by the invention] Good quality I on a Si substrate
Let us consider the problems of the above-mentioned conventional structure adopted to obtain a II-V compound semiconductor thin film.
【０００８】ＧａＡｓ／絶縁膜／Ｓｉ構造を形成するた
めには基板に対して垂直方向の成長が十分に抑えられた
横方向成長が必要であり、そのため熱平衡に極めて近い
条件で成長を行なうＬＰＥ法が使われた。しかしＬＰＥ
法では成長温度が約７５０℃と高い。そのため基板およ
び絶縁膜と成長膜との熱膨脹係数差のために成長膜にク
ラックが入ったり歪が残ってしまい問題となる。またＬ
ＰＥ法では扱うことができる基板の大きさと枚数に制限
がある。その点、横方向成長にハロゲン輸送法や有機金
属気相成長法（ＭＯＣＶＤ法）など気相成長法（ＶＰＥ
法）を用いることができるならば、より低い温度で成長
でき、量産性に優れており、またデバイス性能の向上に
必要な薄膜構造の成長も可能であるため有利である。し
かしＶＰＥ法では基板面方位が特に（１１１） 面であ
る場合を除くと、デバイス作製に重要な（１００）面な
どでの十分な横方向成長は得られない。In order to form a GaAs/insulating film/Si structure, lateral growth with sufficient suppression of growth perpendicular to the substrate is required, and therefore the LPE method, which performs growth under conditions extremely close to thermal equilibrium, is required. was used. However, L.P.E.
In this method, the growth temperature is as high as about 750°C. Therefore, due to the difference in coefficient of thermal expansion between the substrate and the insulating film and the grown film, cracks or distortions remain in the grown film, causing problems. Also L
In the PE method, there are limits to the size and number of substrates that can be handled. In this respect, vapor phase epitaxy (VPE) methods such as halogen transport method and metal organic chemical vapor deposition method (MOCVD method) are used for lateral growth.
If the method can be used, it is advantageous because it can be grown at a lower temperature, has excellent mass productivity, and also allows the growth of thin film structures necessary for improving device performance. However, in the VPE method, sufficient lateral growth cannot be obtained in the (100) plane, which is important for device fabrication, unless the substrate plane orientation is particularly the (111) plane.
【０００９】またマスク上への横方向成長速度には限界
があるので、大きな面積を得るにはたとえばシード部分
を近接して多数配置し横方向成長する必要がある。それ
ぞれのシードからの成長部分はいずれ合体するので一応
大面積化できる。しかしこの構造では転位密度の高いシ
ード領域が表面に周期的に残ってしまう。Furthermore, since there is a limit to the rate of lateral growth on the mask, in order to obtain a large area, it is necessary, for example, to arrange a large number of seed portions close to each other for lateral growth. The growing parts from each seed will eventually coalesce, so it can be made into a large area. However, in this structure, seed regions with high dislocation density remain periodically on the surface.
【００１０】本発明の目的はこのような従来技術の欠点
を克服し、ＩＶ族半導体単結晶基板上に高品質なＩＩＩ
−Ｖ族半導体単結晶表面を有する絶縁膜／ＩＩＩ −
Ｖ族化合物半導体積層構造を提供することにある。An object of the present invention is to overcome the drawbacks of the prior art and to produce high-quality III-III semiconductors on a single-crystal group-IV semiconductor substrate.
-Insulating film with group V semiconductor single crystal surface/III-
An object of the present invention is to provide a group V compound semiconductor stacked structure.
【００１１】[0011]
【課題を解決するための手段】本発明によれば、ＩＶ族
単結晶基板上に非晶質絶縁膜およびＩＩＩ −Ｖ族化合
物半導体単結晶薄膜が交互に積層され、表面はＩＩＩ
−Ｖ族化合物半導体単結晶であることを基本とする構造
において、前記積層体は少なくとも２層以上の非晶質絶
縁膜層を含み、それぞれの非晶質絶縁膜層はその占有面
内の一部に上下に貫通する穴を有し、この穴を通して上
下のＩＩＩ −Ｖ族化合物半導体単結晶層またはＩＶ族
単結晶基板が互に接続されており、さらに１つの非晶質
絶縁膜層に開けられた前記穴の面内方向の位置はその１
つ上方または下方の非晶質絶縁膜層の穴の位置と重なら
ないことを特徴とするＩＶ族基板上の絶縁膜／ＩＩＩ
−Ｖ族化合物半導体積層構造が得られる。[Means for Solving the Problems] According to the present invention, an amorphous insulating film and a III-V group compound semiconductor single crystal thin film are alternately laminated on a group IV single crystal substrate, and the surface is
- In a structure based on a group V compound semiconductor single crystal, the laminate includes at least two or more amorphous insulating film layers, and each amorphous insulating film layer covers one part of its occupied surface. The upper and lower III-V group compound semiconductor single crystal layers or IV group single crystal substrates are connected to each other through this hole, and a hole is formed in one amorphous insulating film layer. The position of the hole in the in-plane direction is 1
An insulating film on a group IV substrate characterized in that it does not overlap with the position of a hole in an upper or lower amorphous insulating film layer/III
- A group V compound semiconductor stacked structure is obtained.
【００１２】0012
【作用】従来のＧａＡｓ／絶縁膜／Ｓｉ構造の利点はＧ
ａＡｓ／Ｓｉ界面で発生した転位が主にシード部分の上
方のみに伸び、横方向には伸びないことである。そこで
転位のこの様な性質に加え、さらに非晶質、即ち原子配
列に周期性のない絶縁膜中へは転位の貫通が起こらない
という性質も考慮することで本発明の積層構造が得られ
た。すなわち図１に示すようにＳｉ基板１の上に設けら
れた第一のＳｉＯ２ 膜２にはシードとなるＳｉ基板１
の露出した開口部があり、この開口部の上方、ＧａＡｓ
成長層４中に開口部より面積の大きい第二のＳｉＯ２
膜３が開口部を覆う形で埋め込まれている。この様な構
造では、シード部分のＧａＡｓ／Ｓｉ界面で発生した転
位の上昇が第二のＳｉＯ２ 膜３によって阻止されるた
め、ＧａＡｓ成長層４の表面まで転位が貫通することが
ない。[Operation] The advantage of the conventional GaAs/insulating film/Si structure is that
The dislocations generated at the aAs/Si interface mainly extend only above the seed portion and do not extend laterally. Therefore, in addition to these properties of dislocations, the stacked structure of the present invention was obtained by taking into consideration the property that dislocations do not penetrate into an amorphous insulating film, that is, an insulating film with no periodicity in atomic arrangement. . That is, as shown in FIG.
There is an exposed opening, and above this opening, the GaAs
A second SiO2 layer having a larger area than the opening in the growth layer 4
A membrane 3 is embedded to cover the opening. In such a structure, the rise of dislocations generated at the GaAs/Si interface in the seed portion is prevented by the second SiO2 film 3, so that dislocations do not penetrate to the surface of the GaAs growth layer 4.
【００１３】またこの様な構造を形成するには図１から
ＧａＡｓ成長層４を除いたような構造、即ち第一のＳｉ
Ｏ２ 膜２と第二のＳｉＯ２ 膜３の２つのＳｉＯ２
膜で挟まれた空洞を有する構造を先に形成しておき、次
に２つのＳｉＯ２ 膜をガイドとしてＧａＡｓをＳｉＯ
２膜２の開口部から横方向成長すればよい。その結果、
ＧａＡｓ層の成長方法としてＬＰＥ法に限定する必要が
無くなり、選択成長が可能でさえあれば熱歪が少なく量
産性にも優れた気相成長法を適用することが可能となる
。Furthermore, in order to form such a structure, a structure similar to that shown in FIG. 1 with the GaAs growth layer 4 removed, that is, the first Si
Two SiO2: O2 film 2 and second SiO2 film 3
A structure having a cavity sandwiched between films is first formed, and then GaAs is deposited on SiO2 using the two SiO2 films as a guide.
2 may be grown laterally from the opening of the film 2. the result,
It is no longer necessary to limit the growth method of the GaAs layer to the LPE method, and as long as selective growth is possible, it becomes possible to apply the vapor phase growth method, which has less thermal strain and is excellent in mass productivity.
【００１４】以上の原理によってＩＶ族半導体単結晶基
板上に高品質かつ大面積なＩＩＩ −Ｖ族化合物半導体
単結晶表面を有する絶縁膜／ＩＩＩ −Ｖ族化合物半導
体積層構造が実現できる。According to the above principle, an insulating film/III-V compound semiconductor laminated structure having a high-quality, large-area III-V compound semiconductor single-crystal surface can be realized on a group-IV semiconductor single-crystal substrate.
【００１５】[0015]
【実施例】以下、本発明の実施例について図面を参照し
て詳細に説明する。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
【００１６】（実施例１）図２（ａ）〜（ｈ）には本発
明の構造を得るための一例としての製造工程を各段階に
おける断面図で示した。図２（ａ）に示すようにまずＳ
ｉ基板１の表面全面に第一のＳｉＯ２ 膜２および非晶
質ＡＩＮ膜２１を形成後、Ｓｉ基板１まで貫通する開口
部を等間隔で複数設ける。次に、図２（ｂ）に示すよう
にＳｉ基板１に貫通する開口部に第一のＧａＡｓ選択成
長層２２を形成する。ＧａＡｓの選択成長には、例えば
ＩＩＩ 族有機金属原料としてジエチルガリウムクロラ
イド（ＤＥＧａＣｌ）、Ｖ族原料としてはアルシン（Ａ
ｓＨ３ ）を用いたＭＯＣＶＤ法を用いることができ、
この方法は以下でＧａＡｓ横方向成長する場合にも適用
することができる。次に図２（ｃ）に示すように、表面
全面に第二のＳｉＯ２ 膜３および非晶質Ｓｉ膜２３を
形成後、非晶質ＡｌＮ膜２１まで貫通する開口部を設け
る。この開口部の面内の位置は第一のＧａＡｓ選択成長
層２２と重ならず、かつ周囲にある第一のＧａＡｓ選択
成長層２２から面内方向で等距離になる位置とする。次
に図２（ｄ）に示すように、開口部を通して非晶質Ａｌ
Ｎ膜２１を選択的に除去し、さらに図２（ｅ）に示すよ
うに、開口部を通して第一のＧａＡｓ横方向成長層２４
および第二のＧａＡｓ選択成長層２５を形成する。次に
図２（ｆ）に示すように、表面全面に第三のＳｉＯ２
膜２６を形成後、面内の位置が第二のＧａＡｓ選択成長
層２５と重ならないように非晶質Ｓｉ膜２３まで貫通す
る開口部を設け、さらにこの開口部を通して非晶質Ｓｉ
膜２３を選択的に除去する。この時の開口部の位置も図
２（ｃ）と同様に第二のＧａＡｓ選択成長層２５から面
内方向で等距離になる様にする。次に図２（ｇ）に示す
ように、開口部を通して第二のＧａＡｓ横方向成長層２
７を形成し、最後に図２（ｈ）に示すように、第三のＳ
ｉＯ２ 膜２６を除去し第二のＧａＡｓ選択成長層２５
および第二のＧａＡｓ横方向成長層２７の表面を露出さ
せる。(Example 1) FIGS. 2(a) to 2(h) show cross-sectional views at each stage of the manufacturing process as an example for obtaining the structure of the present invention. As shown in Figure 2(a), first S
After forming the first SiO2 film 2 and the amorphous AIN film 21 on the entire surface of the i-substrate 1, a plurality of openings penetrating to the Si substrate 1 are provided at equal intervals. Next, as shown in FIG. 2(b), a first GaAs selective growth layer 22 is formed in the opening penetrating the Si substrate 1. For selective growth of GaAs, for example, diethyl gallium chloride (DEGaCl) is used as a group III organic metal raw material, and arsine (A
MOCVD method using sH3) can be used,
This method can also be applied to the case of laterally growing GaAs. Next, as shown in FIG. 2C, after forming the second SiO2 film 3 and the amorphous Si film 23 on the entire surface, an opening penetrating to the amorphous AlN film 21 is provided. The in-plane position of this opening is such that it does not overlap with the first GaAs selectively grown layer 22 and is equidistant from the surrounding first GaAs selectively grown layer 22 in the in-plane direction. Next, as shown in Figure 2(d), the amorphous Al
The N film 21 is selectively removed, and the first GaAs lateral growth layer 24 is then removed through the opening, as shown in FIG.
Then, a second GaAs selective growth layer 25 is formed. Next, as shown in FIG. 2(f), a third layer of SiO2 is applied to the entire surface.
After forming the film 26, an opening penetrating to the amorphous Si film 23 is provided so that the in-plane position does not overlap with the second GaAs selectively grown layer 25, and the amorphous Si film 26 is formed through this opening.
Film 23 is selectively removed. The positions of the openings at this time are also set to be equidistant from the second GaAs selectively grown layer 25 in the in-plane direction, as in FIG. 2(c). Next, as shown in FIG. 2(g), the second GaAs lateral growth layer 2 is inserted through the opening.
7, and finally the third S, as shown in Figure 2(h).
The iO2 film 26 is removed and a second GaAs selectively grown layer 25 is formed.
Then, the surface of the second GaAs lateral growth layer 27 is exposed.
【００１７】このような製造工程では、第一のＧａＡｓ
選択成長層２２および第二のＧａＡｓ選択成長層２５が
それぞれ第二のＳｉＯ２ 膜３および第三のＳｉＯ２
膜２６に接してこれらを支えているため、原理的に幾ら
でも大面積化が可能である。[0017] In such a manufacturing process, the first GaAs
The selective growth layer 22 and the second GaAs selective growth layer 25 are the second SiO2 film 3 and the third SiO2 film, respectively.
Since these are supported in contact with the membrane 26, it is possible in principle to increase the area to any extent.
【００１８】得られたＧａＡｓ層の結晶品質を調べるた
め、図２の工程終了後さらにＧａＡｓ層を全面に約３ｕ
ｍ成長した。成長表面でのエッチピットはほとんど観測
されず、また平面ＴＥＭ観察の結果からも転位密度は多
くても１０３ 〜１０４ ｃｍ−２と極めて良好な結晶
品質が得られた。In order to examine the crystal quality of the obtained GaAs layer, after the process shown in FIG.
m has grown. Almost no etch pits were observed on the growth surface, and the results of planar TEM observation showed that the dislocation density was at most 103 to 104 cm-2, indicating extremely good crystal quality.
【００１９】[0019]
【実施例２】図３（ａ）〜（ｈ）には本発明の構造を得
るための別の例としての製造工程を各段階における断面
図で示した。図３（ａ）に示すように、まずＳｉ基板１
の表面全面に第一のＧａＡｓ成長層３１を形成する。次
に全面に第一のＳｉＯ２ 膜２を形成後、第一のＧａＡ
ｓ成長層３１まで貫通する開口部を一部の領域に等間隔
で複数設ける。次に図３（ｂ）に示すように、まず第一
のＧａＡｓ成長層３１に貫通する開口部に第一のＩｎＰ
選択成長層３２を形成する。次に表面全面にＩｎＰ層を
形成後、第一のＩｎＰ選択成長層３２の設けられた領域
上以外は除去して第一のＩｎＰ成長層３３を形成する。
この第一のＩｎＰ成長層３３は第一のＩｎＰ選択成長層
３２上では単結晶、また第一のＳｉＯ２膜２上では非晶
質また多結晶となっている。ＩｎＰの選択成長には例え
ばジメチルインジウムクロライド（ＤＭＩｎＣｌ）とホ
スフィン（ＰＨ３ ）を用いたＭＯＣＶＤ法を用いるこ
とができる。またＤＭＩｎＣｌではなく例えばトリエチ
ルインジウム（ＴＥＩ）を用いて比較的低温で成長すれ
ば、鏡面性良く全面に成長する事ができる。この時Ｓｉ
Ｏ２ 膜上では非晶質または多結晶となる。次に図３（
ｃ）に示すように表面全面に第二のＳｉＯ２ 膜３を形
成後、第一のＩｎＰ成長層３３まで貫通する開口部を設
ける。この開口部の面内の位置は第一のＩｎＰ選択成長
層３２と重ならないように、かつ周囲にある第一のＩｎ
Ｐ選択成長層３２から面内方向で等距離になる位置とす
る。次に図３（ｄ）に示すように開口部を通して第二の
ＩｎＰ選択成長層３４および第二のＩｎＰ成長層３５を
形成する。第二のＩｎＰ成長層３５は第一のＩｎＰ成長
層３３と同様に、まず表面全面にＩｎＰ層を形成し、続
いて第二のＩｎＰ選択成長層３４の設けられた領域上以
外は除去することで形成する。次に図３（ｅ）に示すよ
うに、表面全面に第三のＳｉＯ２ 膜２６を形成後、第
二のＩｎＰ成長層３５まで貫通する開口部を設ける。こ
の開口部も周囲にある第二のＩｎＰ選択成長層３４から
面内方向で等距離の重ならない位置とする。次に図３（
ｆ）に示すようにこの開口部を通してＩｎＰ層３２、３
３、３４、３５をすべて選択的に除去する。次に図３（
ｇ）に示すように、開口部を通して第三のＳｉＯ２ 膜
２６より下方の空洞内を第二のＧａＡｓ成長層３６で埋
める。最後に図３（ｈ）に示すように、第三のＳｉＯ２
膜２６のうち第二のＧａＡｓ成長層３６に接する部分
のみを除去して第二のＧａＡｓ成長層３６の表面を露出
させる。[Embodiment 2] FIGS. 3(a) to 3(h) show cross-sectional views at each stage of another example of the manufacturing process for obtaining the structure of the present invention. As shown in FIG. 3(a), first, the Si substrate 1
A first GaAs growth layer 31 is formed over the entire surface. Next, after forming a first SiO2 film 2 on the entire surface, a first GaA film 2 is formed on the entire surface.
A plurality of openings penetrating to the s growth layer 31 are provided in some regions at equal intervals. Next, as shown in FIG. 3(b), first InP is placed in the opening penetrating the first GaAs growth layer 31.
A selective growth layer 32 is formed. Next, after forming an InP layer on the entire surface, the first InP growth layer 33 is formed by removing the region other than the region where the first InP selective growth layer 32 is provided. This first InP growth layer 33 is monocrystalline on the first InP selective growth layer 32, and amorphous or polycrystalline on the first SiO2 film 2. For selective growth of InP, for example, MOCVD using dimethylindium chloride (DMInCl) and phosphine (PH3) can be used. Further, if growth is performed at a relatively low temperature using, for example, triethyl indium (TEI) instead of DMInCl, it is possible to grow the entire surface with good specularity. At this time Si
It becomes amorphous or polycrystalline on the O2 film. Next, Figure 3 (
As shown in c), after forming the second SiO2 film 3 on the entire surface, an opening is provided that penetrates to the first InP growth layer 33. The in-plane position of this opening is such that it does not overlap with the first InP selective growth layer 32 and that it does not overlap with the first InP selective growth layer 32.
The positions are equidistant from the P selective growth layer 32 in the in-plane direction. Next, as shown in FIG. 3(d), a second InP selective growth layer 34 and a second InP growth layer 35 are formed through the opening. As with the first InP growth layer 33, the second InP growth layer 35 is formed by first forming an InP layer on the entire surface, and then removing the area other than the area where the second InP selective growth layer 34 is provided. to form. Next, as shown in FIG. 3(e), after forming a third SiO2 film 26 on the entire surface, an opening penetrating to the second InP growth layer 35 is provided. This opening is also located at a non-overlapping position equidistant from the surrounding second InP selective growth layer 34 in the in-plane direction. Next, Figure 3 (
InP layers 32, 3 are inserted through this opening as shown in f).
3, 34, and 35 are all selectively removed. Next, Figure 3 (
As shown in g), the cavity below the third SiO2 film 26 is filled with the second GaAs growth layer 36 through the opening. Finally, as shown in Figure 3(h), the third SiO2
Only the portion of the film 26 that is in contact with the second GaAs growth layer 36 is removed to expose the surface of the second GaAs growth layer 36.
【００２０】この様にして得られたＧａＡｓ層の結晶品
質も実施例１と同様に高品質であり、転位密度の極めて
少ない結果が得られた。The crystal quality of the GaAs layer obtained in this way was also high as in Example 1, and the result was that the dislocation density was extremely low.
【００２１】なおこの方法は実施例１とは異なりあまり
大面積化は期待できない。しかし絶縁膜として必要なの
は１種類のみで工程はより単純であり、またＳｉＯ２
膜以外の例えばＡｌＮやＳｉ３ Ｎ４ などの非晶質膜
を用いても良い。実施例１でも互に選択除去さえできれ
ば他の絶縁膜の組合わせを用いても良い。Note that this method is different from the first embodiment and cannot be expected to increase the area very much. However, only one type of insulating film is required, the process is simpler, and SiO2
For example, an amorphous film such as AlN or Si3 N4 may be used instead of the film. In the first embodiment, other combinations of insulating films may be used as long as they can be selectively removed from each other.
【００２２】２つの実施例ではＧａＡｓおよびＩｎＰの
選択成長方法としてＤＥＧａＣｌなどの塩素系原料を用
いたＭＯＣＶＤを用いた。これは塩素系原料の方が通常
のトリメチルガリウム（ＴＭＧ）やトリメチルインジウ
ム（ＴＭＩ）を用いた場合より選択性が良いためである
。同様の理由から選択成長にはハロゲン輸送法を用いる
ことができる。ただしこの系ではＩｎＰの全面成長はで
きず、原料を変えるだけで選択成長と全面成長とを連続
的に行なうことができる点、ＭＯＣＶＤが有利である。
なお全面成長に限れば、より低温で鏡面性良く成長でき
る分子線エピタキシー（ＭＢＥ）が最も適している。In the two examples, MOCVD using a chlorine-based raw material such as DEGaCl was used as a selective growth method for GaAs and InP. This is because the chlorine-based raw material has better selectivity than when using normal trimethyl gallium (TMG) or trimethyl indium (TMI). For the same reason, the halogen transport method can be used for selective growth. However, in this system, InP cannot be grown over the entire surface, and MOCVD is advantageous in that selective growth and overall growth can be performed continuously by simply changing the raw material. As far as full-surface growth is concerned, molecular beam epitaxy (MBE) is most suitable because it can grow at a lower temperature and with good specularity.
【００２３】また２つの実施例ともにＳｉ基板上の絶縁
膜／ＧａＡｓ積層構造を例に説明したが、ＩＶ族単結晶
基板がＧｅの場合、またＩＩＩ −Ｖ族化合物半導体が
他のＧａＰやＩｎＰ、ＩｎＧａＡｓなどの混晶の場合、
さらに積層構造中に複数種類のＩＩＩ−Ｖ族化合物半導
体層が混在する場合にも広く本発明を適用することがで
きる。[0023]Also, in both embodiments, the insulating film/GaAs laminated structure on a Si substrate was explained as an example, but when the group IV single crystal substrate is Ge, or when the III-V group compound semiconductor is other than GaP, InP, In the case of mixed crystals such as InGaAs,
Furthermore, the present invention can be broadly applied to cases where a plurality of types of III-V compound semiconductor layers coexist in a stacked structure.
【００２４】[0024]
【発明の効果】以上のように本発明によればＩＶ族単結
晶基板とＩＩＩ −Ｖ族エピタキシャル界面で発生した
転位が成長表面まで上昇してこないので、ＩＶ族半導体
単結晶基板上に高品質かつ大面積なＩＩＩ −Ｖ族化合
物半導体単結晶表面を有する絶縁膜／ＩＩＩ −Ｖ族化
合物半導体積層構造が実現でき、発明の効果が示された
。As described above, according to the present invention, dislocations generated at the interface between a group IV single crystal substrate and a group III-V epitaxial substrate do not rise to the growth surface, so that a high quality product can be obtained on a group IV semiconductor single crystal substrate. Moreover, an insulating film/III-V group compound semiconductor laminated structure having a large-area III-V group compound semiconductor single crystal surface was realized, and the effects of the invention were demonstrated.
【図１】本発明の原理的な構造を示す模式図。FIG. 1 is a schematic diagram showing the basic structure of the present invention.
【図２】本発明の一実施例の製造工程を示す断面図。FIG. 2 is a sectional view showing the manufacturing process of an embodiment of the present invention.
【図３】本発明の別の実施例の製造工程を示す断面図。FIG. 3 is a sectional view showing the manufacturing process of another embodiment of the present invention.
１ Ｓｉ基板
２ 第一のＳｉＯ２ 膜
３ 第二のＳｉＯ２ 膜
４ ＧａＡｓ成長層
５ 転位
２１ 非晶質ＡｌＮ膜
２２ 第一のＧａＡｓ選択成長層２３ 非
晶質Ｓｉ膜
２４ 第一のＧａＡｓ横方向成長層２５
第二のＧａＡｓ選択成長層２６ 第三のＳｉＯ２
膜
２７ 第二のＧａＡｓ横方向成長層３１
第一のＧａＡｓ成長層
３２ 第一のＩｎＰ選択成長層
３３ 第一のＩｎＰ成長層
３４ 第二のＩｎＰ選択成長層
３５ 第二のＩｎＰ成長層
３６ 第二のＧａＡｓ成長層1 Si substrate 2 First SiO2 film 3 Second SiO2 film 4 GaAs growth layer 5 Dislocation 21 Amorphous AlN film 22 First GaAs selective growth layer 23 Amorphous Si film 24 First GaAs lateral growth layer 25
Second GaAs selective growth layer 26 Third SiO2
Membrane 27 Second GaAs lateral growth layer 31
First GaAs growth layer 32 First InP selective growth layer 33 First InP growth layer 34 Second InP selective growth layer 35 Second InP growth layer 36 Second GaAs growth layer
Claims (1)
よびＩＩＩ −Ｖ族化合物半導体単結晶薄膜が交互に積
層され、表面はＩＩＩ −Ｖ族化合物半導体単結晶であ
ることを基本とする構造において、前記積層体は少なく
とも２層以上の非晶質絶縁膜層を含み、それぞれの非晶
質絶縁膜層はその占有面内の一部に上下に貫通する穴を
有し、この穴を通して上下のＩＩＩ −Ｖ族化合物半導
体単結晶層またはＩＶ族単結晶基板が互に接続されてお
り、さらに１つの非晶質絶縁膜層に開けられた前記穴の
面内方向の位置はその１つ上方または下方の非晶質絶縁
膜層の穴の位置と重ならないことを特徴とするＩＶ族基
板上の絶縁膜／ＩＩＩ −Ｖ族化合物半導体積層構造。[Claim 1] Basically, an amorphous insulating film and a group III-V compound semiconductor single crystal thin film are alternately laminated on a group IV single crystal substrate, and the surface is a group III-V compound semiconductor single crystal. In the structure, the laminate includes at least two or more amorphous insulating film layers, and each amorphous insulating film layer has a hole penetrating vertically in a part of its occupied surface, and through this hole, The upper and lower III-V group compound semiconductor single crystal layers or IV group single crystal substrates are connected to each other, and the in-plane position of the hole made in one amorphous insulating film layer is one of them. An insulating film/III-V compound semiconductor laminated structure on a group IV substrate, characterized in that the hole position does not overlap with the position of the hole in the upper or lower amorphous insulating film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9334491A JPH04303920A (en) | 1991-03-29 | 1991-03-29 | Insulating film/iii-v compound semiconductor stacked structure on group iv substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9334491A JPH04303920A (en) | 1991-03-29 | 1991-03-29 | Insulating film/iii-v compound semiconductor stacked structure on group iv substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04303920A true JPH04303920A (en) | 1992-10-27 |
Family
ID=14079656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9334491A Withdrawn JPH04303920A (en) | 1991-03-29 | 1991-03-29 | Insulating film/iii-v compound semiconductor stacked structure on group iv substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04303920A (en) |
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| JP2002505519A (en) * | 1998-02-27 | 2002-02-19 | ノース・キャロライナ・ステイト・ユニヴァーシティ | Method for producing gallium nitride semiconductor layer by lateral overgrowth through mask and gallium nitride semiconductor structure produced thereby |
| JP2004247753A (en) * | 2004-04-15 | 2004-09-02 | Toyoda Gosei Co Ltd | GaN SYSTEM SEMICONDUCTOR |
| US6818926B2 (en) | 1999-07-27 | 2004-11-16 | Toyoda Gosei Co., Ltd. | Method for manufacturing gallium nitride compound semiconductor |
| US6830948B2 (en) | 1999-12-24 | 2004-12-14 | Toyoda Gosei Co., Ltd. | Method for producing group III nitride compound semiconductor and group III nitride compound semiconductor device |
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1991
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