JPH0484418A - Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates - Google Patents
Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substratesInfo
- Publication number
- JPH0484418A JPH0484418A JP19964290A JP19964290A JPH0484418A JP H0484418 A JPH0484418 A JP H0484418A JP 19964290 A JP19964290 A JP 19964290A JP 19964290 A JP19964290 A JP 19964290A JP H0484418 A JPH0484418 A JP H0484418A
- Authority
- JP
- Japan
- Prior art keywords
- development
- growth
- substrate
- gaas
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 26
- 150000001875 compounds Chemical class 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000203 mixture Substances 0.000 claims description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 claims description 3
- 150000004820 halides Chemical class 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012159 carrier gas Substances 0.000 abstract description 2
- 239000001257 hydrogen Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000004140 cleaning Methods 0.000 abstract 2
- 239000007792 gaseous phase Substances 0.000 abstract 2
- 150000004678 hydrides Chemical class 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021617 Indium monochloride Inorganic materials 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- APHGZSBLRQFRCA-UHFFFAOYSA-M indium(1+);chloride Chemical compound [In]Cl APHGZSBLRQFRCA-UHFFFAOYSA-M 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はへテロエピタキシャル成長法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to heteroepitaxial growth methods.
異種基板上への■−ｖ族化合物半導体の成長は、太陽電
池、光電子累積素子等の応用をめざして広く研究されて
いる。そのうち、基板としてもっとも広く用いられてい
るＳｉ基板と■−Ｖ族化合物半導体との間には、例えば
ＧａＡｓにおいては４％、ＩｎＰにおいては８％の格子
不整合が存在する為に直接これらをＳｉ基板上にエピタ
キシャル成長させることは出来ない。また、熱膨張係数
の差により反りやクラックが入るという問題もある。こ
れらの問題点を解決するために一般に種々のバッファ層
を導入することが行われている。The growth of ■-V group compound semiconductors on heterogeneous substrates has been widely studied with the aim of applying them to solar cells, photoelectron accumulation devices, and the like. Among these, there is a lattice mismatch of 4% in GaAs and 8% in InP between the Si substrate, which is the most widely used substrate, and ■-V group compound semiconductors. It cannot be epitaxially grown on a substrate. There is also the problem that warpage and cracks occur due to differences in thermal expansion coefficients. In order to solve these problems, various buffer layers are generally introduced.
例えば、Ｇ ａ Ａ ｓ ／ Ｓ ｉにおいては、４０
０℃程度の低温で成長させたＧａＡｓ （ジャパニーズ
ジャーナル オブ アプライド フィジックス２４巻
８４３ページ、１９８４年）、歪超格子（アプライド
フィジックス レター ４８巻１２２３ページ １９８
６年）等がバッファ層として用いられている。また、熱
サイクルアニール（アプライド フィジックス レター
５０巻３１ページ １９８７年）による転位低減効果
も報告されている。一方、Ｓｉ上のＧａＡｓ成長に於て
分子線エピタキシャル成長法（ＭＢＥ）によりＧａＡｓ
層を形成した後、ＳｉＯ２をマスクとしてライン状の窓
をあけ液相エピタキシャル成長法（ＬＰＥ）によりＧａ
Ａｓの横方向成長を用いて非常に低転位のＧａＡｓを得
たという報告がある（第４９回秋季応用物理学会予稿集
ＮＯ３１２９６ページ １９８８年）。これはＳ ｉ
Ｏ２が転位遮断層として働いている為である。For example, in Ga As / Si, 40
GaAs grown at a low temperature of around 0°C (Japanese Journal of Applied Physics Vol. 24)
843 pages, 1984), strained superlattices (Applied
Physics Letters Volume 48, Page 1223, 198
6 years) etc. are used as a buffer layer. Furthermore, the effect of reducing dislocations by thermal cycle annealing (Applied Physics Letters, Vol. 50, p. 31, 1987) has been reported. On the other hand, when growing GaAs on Si, molecular beam epitaxial growth (MBE) is used to grow GaAs on Si.
After forming the layer, a line-shaped window is opened using SiO2 as a mask, and Ga is grown by liquid phase epitaxial growth (LPE).
There is a report that GaAs with extremely low dislocations was obtained using lateral growth of As (Proceedings of the 49th Autumn Annual Meeting of Japan Society of Applied Physics, No. 31296, 1988). This is Si
This is because O2 acts as a dislocation blocking layer.
しかしながら、ＭＢＥ／ＬＰＥ成長による横方向成長以
外は依然として■−Ｖ族化合物半導体成長層中には１０
６ｃｍ−３を越える高密度の残留貫通転位が存在する。However, except for lateral growth by MBE/LPE growth, there are still 10
There is a high density of residual threading dislocations exceeding 6 cm-3.
またＭＢＥ／ＬＰＥ成長ではＳｉ基板の侵食の問題や三
日成長となり製造工程が複雑である等の問題がある。Furthermore, MBE/LPE growth has problems such as erosion of the Si substrate and three-day growth, which complicates the manufacturing process.
本発明の目的は異種基板上に転位の少ないＩ［ｒ−Ｖ族
化合物半導体を一回成長でヘテロエピタキシャル成長さ
せる方法を提供することを目的とする。An object of the present invention is to provide a method for heteroepitaxially growing an I[r-V group compound semiconductor with few dislocations on a heterogeneous substrate in one-time growth.
本発明のへテロエピタキシャル成長法は、■−Ｖ族化合
物半導体成長層を当該成長層とは異なる組成の基板上に
ヘテロエピタキシャル成長させる方法であって、（１１
１）面或は（１１１）面近傍よりなる基板を用い、誘電
体膜を形成した後［１１２］方向或は［１１２］方向近
傍へストライブ状に上記誘電体膜を除去する第一の工程
、ハライド系気相成長法により少なくとも１層のバッフ
ァ層を形成した後に■−Ｖ族化合物半導体成長層を（１
１１｝Ｂ面の成長速度が（１１０）面の成長速度に比べ
て充分大きな条件で成長する第二の工程、上記成長法で
＋１１１面の成長速度がｆｌ１４｝Ｂ面の成長速度に比
べて充分大きな条件でラテラル成長を平坦化するまで行
う第三の工程、■−ｖ族化合物半導体成長層を上記成長
法で？１１１１Ｂ面の成長速度が充分に大きい条件で全
面に成長する第四の工程を含むことを特徴とする成長方
法である。The heteroepitaxial growth method of the present invention is a method for heteroepitaxially growing a -V group compound semiconductor growth layer on a substrate having a composition different from that of the growth layer, the method comprising:
1) A first step of forming a dielectric film using a substrate consisting of a plane or near the (111) plane and then removing the dielectric film in a stripe shape in the [112] direction or near the [112] direction. After forming at least one buffer layer by halide vapor phase epitaxy, a ■-V group compound semiconductor growth layer (1
11}The second step in which the growth rate of the B-plane is sufficiently higher than that of the (110) plane, and in the above growth method, the growth rate of the +111 plane is sufficient compared to the growth rate of the fl14}B-plane. The third step is to perform lateral growth under large conditions until it is flattened.■-Grow a group V compound semiconductor layer using the above growth method? This growth method is characterized by including a fourth step of growing the entire surface under conditions where the growth rate of the 1111B plane is sufficiently high.
本発明によるヘテロエピタキシャル成長法では基板と成
長層の間に誘電体膜、例えばＳ ｉ ０２が挟まれてお
り、これが転位遮断層として働くことが転位低減に重要
な役割を果たす、即ち、種結晶としてＳｉ基板表面が出
ている部分の上のＧａＡｓ成長層は数多くの転位を含ん
でいるが、全面積の大部分を占めるＳ ｉ ０２上のＧ
ａＡｓ層上には殆ど転位が出来ないため全体として非常
に低転位のＧａＡｓ成長層が得られる。また、これまで
はＬＰＥ法で横方向成長を行っていたためＳｉ基板のＧ
ａ融液による侵食等の問題があったが本発明では全気相
成長法で成長を行なうためＬＰＥで見られるような問題
がなく、また製造工程が一回成長になり簡略化される。In the heteroepitaxial growth method according to the present invention, a dielectric film, for example SiO2, is sandwiched between the substrate and the growth layer, and this acts as a dislocation blocking layer, which plays an important role in reducing dislocations. The GaAs growth layer on the exposed part of the Si substrate surface contains many dislocations, but the G on the SiO2, which occupies most of the total area,
Since almost no dislocations are formed on the aAs layer, a GaAs grown layer with very low dislocations as a whole can be obtained. In addition, since lateral growth was previously performed using the LPE method, the G
Although there have been problems such as erosion by the melt, in the present invention, the growth is performed by an all-vapor phase growth method, so there is no problem like that seen in LPE, and the manufacturing process is simplified because the growth is performed once.
以下、図面を用いて本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail using the drawings.
第一図は本発明の一実施例を説明する工程説明図である
。本実施例では基板１０としてＳｉ （１１１）面を用
いる。この基板上にまず第一工程として熱酸化法により
５ｉＯｚｌｌを２００ｎｍ形成し、次にホトリソグラフ
ィーにより＜１１２＞方向にストライブ状に５ｉ０２膜
１１を除去し幅３μｍのストライブ窓を形成してＳｉ表
面を露出させた（第一図（ａ））。FIG. 1 is a process explanatory diagram illustrating an embodiment of the present invention. In this embodiment, a Si (111) plane is used as the substrate 10. As a first step, 5iOzll is formed on this substrate to a thickness of 200 nm by thermal oxidation, and then the 5i02 film 11 is removed in stripes in the <112> direction by photolithography to form a stripe window with a width of 3 μm. The surface was exposed (Figure 1 (a)).
第二工程としてこの基板を水素キャリアガスを用いてア
ルシン（ＡｓＨ３）雰囲気中９００″Ｃで５分間熱クリ
ーニングを行った後降温し、ハイドライド気相成長法（
ＶＰＥ）によりアンドープＧａＡｓバッファ層１２を４
００°Ｃで１１００ｎ成長した。その後ＧａＡｓ １３
を＜１１１＞ Ｂ方向の成長速度が＜１１０＞方向の成
長速度に比べて十分大きい条件（基板温度６９０℃、Ｈ
２流量：３５１ｍ ＩｎＣｌ流量：６ｓｅｃｍ Ｐ
Ｈ８流量：６ｓｅｃｍ）で成長し、矩形にＧａＡｓ １
３を２μｍ成長した（第一図（ｂ））。第三工程として
＜１１０＞方向の成長速度が＜１１１＞ Ｂ方向の成長
速度に比べて十分大きい条件（基板温度６９０℃、Ｈ２
流量：３５１ｍ ＩｎＣｌ流量： １１ ｓｃｃｍ
ＰＨ３流量：１１ｓｃｃｍ）で＜１１０＞方向へのＧ
ａＡｓ１４のラテラル成長を行った（第一図（Ｃ））。As a second step, this substrate was thermally cleaned at 900''C for 5 minutes in an arsine (AsH3) atmosphere using a hydrogen carrier gas, and then the temperature was lowered and the substrate was heated using a hydride vapor phase epitaxy method.
The undoped GaAs buffer layer 12 is
1100n was grown at 00°C. Then GaAs 13
The growth rate in the <111> B direction is sufficiently large compared to the growth rate in the <110> direction (substrate temperature 690°C, H
2 flow rate: 351m InCl flow rate: 6secm P
H8 flow rate: 6 sec) to form a rectangular GaAs 1
3 was grown to a thickness of 2 μm (Fig. 1 (b)). As the third step, the growth rate in the <110> direction is sufficiently higher than the growth rate in the <111>B direction (substrate temperature 690°C, H2
Flow rate: 351 m InCl flow rate: 11 sccm
G in <110> direction at PH3 flow rate: 11 sccm)
Lateral growth of aAs14 was performed (Figure 1 (C)).
第四工程として（１１１）８面上の成長速度が十分大き
い条件でＧａＡｓ１５を５μｍ成長した（第一図（ｄ）
）。As the fourth step, GaAs15 was grown to a thickness of 5 μm under conditions where the growth rate on the (111)8 plane was sufficiently high (Fig. 1 (d)).
).
このような手法を用いることによりエッチピット密度３
Ｘ１０’ｃｍ−’程度の低転位のＧａＡｓ層が一回成長
で得られる。By using such a method, the etch pit density can be reduced to 3.
A GaAs layer with low dislocations of about 10'cm-' can be obtained by one-time growth.
本実施例においてはＳｉ上のＧａＡｓについて説明した
が、ＩｎＰでもよく、またＩ ｎＧａＡｓ、ＩｎＧａＡ
ｓＰ等三元、四元系材料でもよい また、基板もＳｉ以
外、例えばＧｅでもよい。さらに、基板に形成する誘電
体膜も５ｉ０２に限らず窒化膜等、他の組成のものでも
よい。In this example, GaAs on Si was explained, but InP may also be used, and InGaAs, InGaA
A ternary or quaternary material such as sP may be used. The substrate may also be made of a material other than Si, for example, Ge. Furthermore, the dielectric film formed on the substrate is not limited to 5i02, but may be of other compositions, such as a nitride film.
本実施例においては熱サイクルアニールやボストアニー
ルは行っていないが、これらを行っても勿論よい。Although thermal cycle annealing and boss annealing were not performed in this example, these may of course be performed.
本実施例においてはハイドライド気相成長法を用いたが
、クロライド気相成長法を用いても勿論実現できる。Although hydride vapor phase epitaxy was used in this embodiment, it can of course be realized using chloride vapor phase epitaxy.
本発明によるヘテロエピタキシャル成長法は誘電体膜が
転位遮断層として働くため■−ｖ族化合物半導体成長層
において非常に低転位のものが一回の気相成長法で得ら
れる。In the heteroepitaxial growth method according to the present invention, since the dielectric film acts as a dislocation blocking layer, a very low dislocation layer can be obtained in the (1)-V group compound semiconductor growth layer by a single vapor phase growth method.
第一図は本発明の一実施例であるＳｉ基板上へのＧａＡ
ｓの成長方法を示す工程説明図である。
図に於て、
１０・・・５ｉ（１１１）基板、１１・・・５ｉ０２膜
、１２・・・ＧａＡｓバッファ層、１３・・・矩形Ｇａ
Ａｓ成長層、１４・・・ＧａＡｓラテラル成長層、１５
・・・ＧａＡｓ全面成長層。Figure 1 shows an embodiment of the present invention in which GaA is deposited on a Si substrate.
FIG. 2 is a process explanatory diagram showing a method for growing s. In the figure, 10...5i (111) substrate, 11...5i02 film, 12... GaAs buffer layer, 13... rectangular Ga
As growth layer, 14...GaAs lateral growth layer, 15
...GaAs full-grown layer.
Claims (1)
る組成の基板上にヘテロエピタキシャル成長させる方法
であつて、｛１１１｝面或は｛１１１｝面近傍よりなる
基板を用い、誘電体膜を形成した後［１１２］方向或は
［１１２］方向近傍へストライプ状に上記誘電体膜を除
去する第一の工程、ハライド系気相成長法により少なく
とも１層のバッファ層を形成した後にIII−Ｖ族化合物
半導体成長層を｛１１１｝Ｂ面の成長速度が｛１１０｝
面の成長速度に比べて充分大きな条件で成長する第二の
工程、上記成長法で｛１１０｝面の成長速度が｛１１１
｝Ｂ面の成長速度に比べて充分大きな条件でラテラル成
長を平坦化するまで行う第三の工程、III−Ｖ族化合物
半導体成長層を上記成長法で｛１１１｝Ｂ面の成長速度
が充分に大きい条件で全面に成長する第四の工程を含む
ことを特徴とする異種基板上へのIII−Ｖ族化合物半導
体のヘテロエピタキシャル成長法。A method of heteroepitaxially growing a III-V compound semiconductor growth layer on a substrate having a composition different from that of the growth layer, in which a dielectric film is formed using a substrate made of {111} plane or near {111} plane. After that, the first step is to remove the dielectric film in stripes in the [112] direction or near the [112] direction, and after forming at least one buffer layer by halide vapor phase epitaxy, III-V group The growth rate of the compound semiconductor growth layer is {111} and the B-plane is {110}.
In the second step, the growth rate of the {110} plane is grown under sufficiently high conditions compared to the growth rate of the {110} plane in the above growth method.
}The third step is to perform lateral growth under conditions that are sufficiently high compared to the growth rate of the B-plane until the lateral growth is flattened. 1. A method for heteroepitaxial growth of a III-V compound semiconductor on a heterogeneous substrate, the method comprising a fourth step of growing the entire surface under high conditions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19964290A JPH0484418A (en) | 1990-07-27 | 1990-07-27 | Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19964290A JPH0484418A (en) | 1990-07-27 | 1990-07-27 | Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0484418A true JPH0484418A (en) | 1992-03-17 |
Family
ID=16411247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19964290A Pending JPH0484418A (en) | 1990-07-27 | 1990-07-27 | Method of heteroepitaxial development of iii-v group compound semiconductor for different types of substrates |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0484418A (en) |
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| US7052979B2 (en) | 2001-02-14 | 2006-05-30 | Toyoda Gosei Co., Ltd. | Production method for semiconductor crystal and semiconductor luminous element |
| US7141444B2 (en) | 2000-03-14 | 2006-11-28 | Toyoda Gosei Co., Ltd. | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
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