JPH04297044A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04297044A
JPH04297044A JP6218291A JP6218291A JPH04297044A JP H04297044 A JPH04297044 A JP H04297044A JP 6218291 A JP6218291 A JP 6218291A JP 6218291 A JP6218291 A JP 6218291A JP H04297044 A JPH04297044 A JP H04297044A
Authority
JP
Japan
Prior art keywords
anisotropic conductive
adhesive layer
liquid crystal
conductive film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6218291A
Other languages
Japanese (ja)
Inventor
Osamu Osada
長田　治
Hirotaka Nakano
博隆 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6218291A priority Critical patent/JPH04297044A/en
Publication of JPH04297044A publication Critical patent/JPH04297044A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device in which a substrate and a semiconductor element can be connected together with high reliability and yield. CONSTITUTION:Laid on the surface of a glass substrate 11 of an LCD are wire electrodes 12 and position identification marks 13. Superimposed on the bottom surface of an LCD driving IC 16 are, from the surface, aluminum electrodes 17 and a passivating film 18. Disposed under the bottom surface of each aluminum electrode 17 is a metal bump electrode 19. An anisotropic conductive adhesive layer 21 is made up of an adhesive 22 which contains dispersed conductive particles 23. This anisotropic conductive adhesive layer 21 is provided with a conductive film absence cavity 24 which is somewhat larger than the position identification marks 13. The adhesive layer 21 is positioned so that the absent portion 24 is situated above the position identification marks 13, whereupon the adhesive layer 21 is attached to the glass substrate 11 in such a manner that the absent portion 24 is out of contact with the marks 13.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】〔発明の目的〕[Object of the invention]

【０００２】0002

【産業上の利用分野】本発明は、半導体素子の電極と基
板上の電極とが、たとえばフェイスダウンボンディング
法により電気的に接続された半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an electrode of a semiconductor element and an electrode on a substrate are electrically connected by, for example, a face-down bonding method.

【０００３】0003

【従来の技術】一般に、半導体素子を基板に実装した電
子装置で、半導体素子を実装する方法として、半導体素
子上の金属バンプ電極と基板上の取りだし電極とを直接
接続するフェイスダウンボンディング法が知られている
。[Prior Art] Generally, in electronic devices in which a semiconductor element is mounted on a substrate, a face-down bonding method is known as a method for mounting the semiconductor element, in which a metal bump electrode on the semiconductor element is directly connected to a lead-out electrode on the substrate. It is being

【０００４】そして、接続材料として導電性微片が含ま
れた異方性導電膜を用いて電気的に接続することにより
、低コストで高密度実装を実現する方法が、たとえば特
公昭６２−６６５２号公報に記載されている。[0004] A method of realizing high-density packaging at low cost by electrically connecting using an anisotropic conductive film containing conductive particles as a connection material was proposed, for example, in Japanese Patent Publication No. 62-6652. It is stated in the No.

【０００５】この特公昭６２−６６５２号公報に記載さ
れている構成は、たとえば図７に示すように、上面に取
りだし電極としての導電リード層１および位置決め部２
が形成された基板３と、この基板３の導電リード層１上
に配置され、絶縁性を有する接着剤４中に導電性微片と
しての導電粒子５が混入分散され、厚み方向に導電性を
有し面方向に絶縁性を有する異方性導電接着剤層６と、
この異方性導電接着剤層６上に配置固定され、下面に形
成された金属バンプ電極としてのパッド７が形成された
半導体素子８とを備えている。そして、基板３と半導体
素子８との間に、異方性導電接着剤層６を介挿させ、基
板３と半導体素子８とを接着するとともに導電リード層
１とパッド７とを導電粒子５により電気的に接続する。The structure described in Japanese Patent Publication No. 62-6652 has a conductive lead layer 1 as a lead-out electrode and a positioning part 2 on the upper surface, as shown in FIG. 7, for example.
is disposed on the substrate 3 on which is formed and the conductive lead layer 1 of the substrate 3, and conductive particles 5 as conductive particles are mixed and dispersed in the adhesive 4 having insulating properties to provide conductivity in the thickness direction. an anisotropic conductive adhesive layer 6 having insulation properties in the surface direction;
A semiconductor element 8 is arranged and fixed on the anisotropic conductive adhesive layer 6 and has a pad 7 formed on its lower surface as a metal bump electrode. Then, an anisotropic conductive adhesive layer 6 is interposed between the substrate 3 and the semiconductor element 8, and the substrate 3 and the semiconductor element 8 are bonded together, and the conductive lead layer 1 and the pad 7 are bonded together by the conductive particles 5. Connect electrically.

【０００６】また、基板３に半導体素子８を接続するに
際しては、図８に示すように、基板３と半導体素子８と
の間に異方性導電接着剤層６を介挿し、位置決め部２に
より基板３に対する半導体素子８の位置を設定する。そ
して、半導体素子８を基板３方向に押圧し、図７に示す
ように異方性導電接着剤層６の接着剤４により基板３に
半導体素子８を接着するとともに、導電リード層１とパ
ッド７とを導電粒子５により電気的に接続する。Furthermore, when connecting the semiconductor element 8 to the substrate 3, as shown in FIG. 8, an anisotropic conductive adhesive layer 6 is inserted between the substrate 3 and the semiconductor element 8, and The position of the semiconductor element 8 with respect to the substrate 3 is set. Then, the semiconductor element 8 is pressed in the direction of the substrate 3, and as shown in FIG. are electrically connected by conductive particles 5.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、基板３
と上記半導体素子８との間の全域にわたって異方性導電
接着剤層６が介挿されているので、半導体素子８を基板
３に接続する際、機械が認識するときに導電粒子５を接
着剤４中に分散された異方性導電接着剤層６の上から基
板３の位置決め部２を見ることになり、位置決め部２が
ぼやけ、認識ミスが発生し、精度の高い接続ができない
。また、半導体素子８が大きくなると、たとえばシート
状の異方性導電接着剤層６を用いて半導体素子８を接続
する場合、圧着加重が低いと半導体素子８下面の導電リ
ード層１間の異方性導電接着剤層６が外周部に向かって
流れ出すことができず、むりやり押し出すためより大き
な加重が必要となる。このため、接続時に半導体素子８
に損傷を与え、接続の歩留まりを低下させる問題を有し
ている。[Problem to be solved by the invention] However, the substrate 3
Since the anisotropic conductive adhesive layer 6 is interposed over the entire area between the semiconductor element 8 and the semiconductor element 8, when the semiconductor element 8 is connected to the substrate 3, the conductive particles 5 are bonded to the adhesive when recognized by a machine. Since the positioning portion 2 of the substrate 3 is viewed from above the anisotropic conductive adhesive layer 6 dispersed in the substrate 4, the positioning portion 2 becomes blurred, a recognition error occurs, and highly accurate connection cannot be performed. In addition, when the semiconductor element 8 becomes large, for example, when connecting the semiconductor element 8 using a sheet-like anisotropic conductive adhesive layer 6, if the pressure bonding force is low, the anisotropy between the conductive lead layer 1 on the lower surface of the semiconductor element 8 will increase. The conductive adhesive layer 6 cannot flow out toward the outer periphery, and a larger load is required to force it out. Therefore, when connecting the semiconductor element 8
This has the problem of causing damage to the wires and lowering the yield of connections.

【０００８】本発明は、上記問題点に鑑みなされたもの
で、高信頼性および高歩留まりで基板と半導体素子とを
接続した半導体装置を提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device in which a substrate and a semiconductor element are connected with high reliability and high yield.

【０００９】〔発明の構成〕[Configuration of the invention]

【００１０】0010

【課題を解決するための手段】本発明は、半導体素子に
形成されたバンプ電極と、基板上に形成された電極とを
、導電性微片を含む異方性導電膜を介し電気的に接続し
た半導体装置において、前記異方性導電膜は、少なくと
も一部に異方性導電膜が存在していない異方性導電膜不
存在部を形成したものである。[Means for Solving the Problems] The present invention electrically connects bump electrodes formed on a semiconductor element and electrodes formed on a substrate via an anisotropic conductive film containing conductive particles. In the semiconductor device, the anisotropic conductive film has an anisotropic conductive film-free portion formed in at least a portion thereof where no anisotropic conductive film exists.

【００１１】[0011]

【作用】本発明は、半導体素子を異方性導電膜を介して
基板に接続する場合、異方性導電膜の少なくとも一部に
異方性導電膜が存在していない異方性導電膜不存在部が
形成されているため、基板上の位置決め部に介在しない
ように異方性導電膜が配置されれば、位置決め部をたと
えばカメラで直接見ることも可能であり、確実に認識さ
れ、認識ミスの発生がおこりずらくなるため精度の高い
接続ができる。また、圧着加重が低くても異方性導電膜
不存在部に異方性導電膜が容易に流れ出すことができ、
半導体素子に損傷を与えることなく低加重で接続できる
ため、高信頼性、高歩留りとなる。[Operation] When a semiconductor element is connected to a substrate via an anisotropic conductive film, the present invention provides an anisotropic conductive film in which no anisotropic conductive film exists in at least a part of the anisotropic conductive film. Since the presence part is formed, if the anisotropic conductive film is arranged so as not to be interposed in the positioning part on the substrate, it is possible to directly view the positioning part with a camera, for example, and it will be reliably recognized and recognized. Since mistakes are less likely to occur, highly accurate connections can be made. In addition, even if the compression load is low, the anisotropic conductive film can easily flow out into the area where the anisotropic conductive film does not exist.
Since connections can be made with low load without damaging semiconductor elements, high reliability and high yields are achieved.

【００１２】0012

【実施例】以下、本発明の半導体装置の一実施例を図面
を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.

【００１３】図１に示すように、半導体装置としての液
晶表示装置のガラス基板１１上には、所定位置に配線電
極１２および位置決め部としての位置認識マーク１３が
形成されている。この配線電極１２は、表面層がアルミ
ニウム（Ａｌ）またはアルミニウムを主体とする金属ま
たは金属多層膜からなり、本実施例では、クロム（Ｃｒ
）およびアルミニウムからなり、これらクロムおよびア
ルミニウムの膜厚は、それぞれ７０ｎｍ、４００ｎｍに
設定されている。As shown in FIG. 1, wiring electrodes 12 and position recognition marks 13 as positioning portions are formed at predetermined positions on a glass substrate 11 of a liquid crystal display device as a semiconductor device. The wiring electrode 12 has a surface layer made of aluminum (Al) or a metal or metal multilayer film mainly composed of aluminum.
) and aluminum, and the film thicknesses of chromium and aluminum are set to 70 nm and 400 nm, respectively.

【００１４】また、位置認識マーク１３も同じ材質で形
成されている。Furthermore, the position recognition mark 13 is also made of the same material.

【００１５】一方、半導体素子である出力数１２０の液
晶駆動用ＩＣ１６は、およそ５ｍｍ×９ｍｍの大きさで
ある。 そして、液晶駆動用ＩＣ１６の表面にはアルミニウム電
極１７とこのアルミニウム電極１７の下面の一部をも被
覆する窒化シリコン（ＳｉＮ）　などからなる保護用の
パッシベーション膜１８とが形成され、アルミニウム電
極１７の上面には、たとえばチタン（Ｔｉ）、ニッケル
（Ｎｉ）、金（Ａｕ）の順序で構成された図示しないバ
リアメタル層が形成されている。このバリアメタル層の
上には、たとえば金（Ａｕ）　よりなる金属バンプ電極
１９がメッキ法などによって形成されている。On the other hand, the liquid crystal driving IC 16, which is a semiconductor element and has 120 outputs, has a size of approximately 5 mm x 9 mm. Then, on the surface of the liquid crystal driving IC 16, an aluminum electrode 17 and a protective passivation film 18 made of silicon nitride (SiN), which also covers a part of the lower surface of the aluminum electrode 17, are formed. A barrier metal layer (not shown) made of, for example, titanium (Ti), nickel (Ni), and gold (Au) in this order is formed on the upper surface. On this barrier metal layer, a metal bump electrode 19 made of, for example, gold (Au) is formed by plating or the like.

【００１６】この場合、金属バンプ電極１９の高さは約
２３μｍ、大きさは約１００μｍ角のものが用いられ、
接続ピッチは約１４０μｍである。In this case, the height of the metal bump electrode 19 is about 23 μm, and the size is about 100 μm square.
The connection pitch is approximately 140 μm.

【００１７】また、２１は異方性導電膜としての異方性
導電接着剤層で、この異方性導電接着剤層２１は、たと
えばエポキシ系の絶縁性を有する熱硬化性樹脂の接着剤
２２に、たとえばニッケル製の導電性微片としての導電
粒子２３が分散されて包含されている。そして、この異
方性導電接着剤層２１は、厚み方向に導電性を有し、面
方向に絶縁性を有している。Further, reference numeral 21 denotes an anisotropic conductive adhesive layer as an anisotropic conductive film, and this anisotropic conductive adhesive layer 21 is made of an adhesive 22 made of, for example, an epoxy-based thermosetting resin having insulating properties. Conductive particles 23 as conductive particles made of, for example, nickel are dispersed and included in the conductive particles. The anisotropic conductive adhesive layer 21 has conductivity in the thickness direction and insulation in the surface direction.

【００１８】なお、異方性導電接着剤層２１の膜厚は約
３０μｍである。また、導電粒子２３は完全に球形でな
くてもよく、たとえば毬栗状であっても良く、直径は、
約２μｍから６μｍに設定されている。さらに、異方性
導電接着剤層２１には、位置認識マーク１３よりやや大
きめの孔状の導電膜不存在部２４が形成されている。The thickness of the anisotropic conductive adhesive layer 21 is approximately 30 μm. Further, the conductive particles 23 do not have to be completely spherical, and may be chestnut-shaped, for example, and have a diameter of
The thickness is set to approximately 2 μm to 6 μm. Further, the anisotropic conductive adhesive layer 21 has a hole-shaped conductive film absent portion 24 that is slightly larger than the position recognition mark 13 .

【００１９】次に、ガラス基板１１上の配線電極１２へ
、液晶駆動用ＩＣ１６の金属バンプ電極１９をフェイス
ダウンボンディング法により電気的に接続する方法につ
いて図２ないし図４を用いて説明する。Next, a method for electrically connecting the metal bump electrodes 19 of the liquid crystal driving IC 16 to the wiring electrodes 12 on the glass substrate 11 by face-down bonding will be described with reference to FIGS. 2 to 4.

【００２０】まず、異方性導電接着剤層２１の外形を液
晶駆動用ＩＣ１６よりやや大きく、その中心部に３ｍｍ
×７ｍｍの大きさの導電膜不存在部２４を金型で打ち抜
く。First, the outer shape of the anisotropic conductive adhesive layer 21 is slightly larger than that of the liquid crystal driving IC 16, and a 3 mm thick layer is formed in the center of the anisotropic conductive adhesive layer 21.
A conductive film-free portion 24 having a size of 7 mm is punched out using a die.

【００２１】そして、図２に示すように、たとえばカメ
ラ等で位置認識マーク１３を確認し、位置認識マーク１
３上に、異方性導電膜不存在部２４が位置するように異
方性導電接着剤層２１を位置させ、図３に示すように異
方性導電接着剤層２１の異方性導電膜不存在部２４がガ
ラス基板１１上の位置認識マーク１３に接触しないよう
に貼付する。Then, as shown in FIG. 2, the position recognition mark 13 is confirmed using a camera or the like, and the position recognition mark 1 is
The anisotropic conductive adhesive layer 21 is positioned on the anisotropic conductive adhesive layer 21 so that the anisotropic conductive film absent portion 24 is located on the anisotropic conductive adhesive layer 21 as shown in FIG. It is attached so that the absent portion 24 does not come into contact with the position recognition mark 13 on the glass substrate 11.

【００２２】次に、図４に示す自動ボンディング・ツー
ル３１で、液晶駆動用ＩＣ１６の裏面側より約８ｋｇで
加圧（約５０ｇ／パッド）・加熱（ツール温度１９０℃
）しながら約３０秒保持する。Next, using the automatic bonding tool 31 shown in FIG. 4, pressurize (approximately 50 g/pad) and heat (tool temperature 190° C.) with approximately 8 kg from the back side of the LCD driving IC 16.
) and hold for about 30 seconds.

【００２３】この時、ガラス基板１１は、約６０℃に加
熱した図示しないステージ上に載せてあり、ガラス基板
１１の裏面側より加熱されている。At this time, the glass substrate 11 is placed on a stage (not shown) heated to about 60° C., and is heated from the back side of the glass substrate 11.

【００２４】そうして、ボンディング・ツール３１を液
晶駆動用ＩＣ１６から離せば、図１に示すように、異方
性導電接着剤層２１の接着剤２２により、ガラス基板１
１に液晶駆動用ＩＣ１６が接着されるとともに、異方性
導電接着剤層２１中の導電粒子２３によりガラス基板１
１の配線電極１２に液晶駆動用ＩＣ１６の金属バンプ電
極１９が電気的に接続される。Then, when the bonding tool 31 is separated from the liquid crystal driving IC 16, as shown in FIG.
The liquid crystal driving IC 16 is bonded to the glass substrate 1 , and the conductive particles 23 in the anisotropic conductive adhesive layer 21 are bonded to the glass substrate 1 .
A metal bump electrode 19 of a liquid crystal driving IC 16 is electrically connected to one wiring electrode 12 .

【００２５】以上の工程は、すべて自動化されており、
液晶駆動用ＩＣ１６はガラス基板１１上に実装される。 液晶駆動用ＩＣ１６下面中央部に３ｍｍ×７ｍｍの大き
さの異方性導電接着剤層２１が介在していない異方性導
電膜不存在部２４があるため、ガラス基板１１上の、異
方性導電膜不存在部２４の範囲内に形成されている位置
認識マーク１３をカメラ等で直接見ることができ、クリ
アに認識され、認識ミスの発生がおこりにくく、精度の
高い接続ができる。[0025] All of the above steps are automated.
The liquid crystal driving IC 16 is mounted on the glass substrate 11. Since there is an anisotropic conductive film absent area 24 with a size of 3 mm x 7 mm in which the anisotropic conductive adhesive layer 21 is not interposed at the center of the lower surface of the liquid crystal driving IC 16, the anisotropic conductive film on the glass substrate 11 is The position recognition mark 13 formed within the conductive film absent area 24 can be directly viewed with a camera or the like, and is clearly recognized, making it difficult for recognition errors to occur and allowing highly accurate connection.

【００２６】また、液晶駆動用ＩＣ１６とガラス基板１
１との間隙は異方性導電接着剤層２１の厚さより少なく
設定する。これにより、たとえばシート状の異方性導電
接着剤層２１を用いて接続の場合、液晶駆動用ＩＣ１６
下面の一部に３ｍｍ×７ｍｍの大きさの異方性導電接着
剤層２１が介在していない異方性導電膜不存在部２４が
あるため、低加重の接続で、液晶駆動用ＩＣ１６下面の
接着剤２２が容易に流れ出すことができ、高信頼性・高
歩留まりの液晶表示装置を提供することが可能である。[0026] Also, the liquid crystal driving IC 16 and the glass substrate 1
1 is set to be smaller than the thickness of the anisotropic conductive adhesive layer 21. As a result, when connecting using the sheet-like anisotropic conductive adhesive layer 21, for example, the liquid crystal driving IC 16
Since there is an anisotropic conductive film-free area 24 in a part of the lower surface where the anisotropic conductive adhesive layer 21 with a size of 3 mm x 7 mm is not interposed, the lower surface of the liquid crystal driving IC 16 can be connected with a low load. The adhesive 22 can flow out easily, making it possible to provide a liquid crystal display device with high reliability and high yield.

【００２７】なお、上記接着剤２２は、接続時に１９０
℃、約３０秒間保持することにより硬化が進み、液晶駆
動用ＩＣ１６の表面保護層であるパッシベーション膜１
８およびガラス基板１１に強固に密着する。それゆえ、
液晶駆動用ＩＣ１６全体が、ガラス基板１１上に強固に
装着され、その後のボンディングによる樹脂補強の工程
も不要となる。[0027] Note that the adhesive 22 has a 190%
℃ for about 30 seconds, the curing progresses and the passivation film 1, which is the surface protection layer of the liquid crystal driving IC 16, is cured.
8 and the glass substrate 11. therefore,
The entire liquid crystal driving IC 16 is firmly mounted on the glass substrate 11, and the subsequent process of reinforcing resin by bonding is also unnecessary.

【００２８】また、液晶駆動用ＩＣ１６の上の金属バン
プ電極１９の高さが揃っている場合には、図１に示すよ
うに、それぞれの金属バンプ電極１９が導電粒子２３を
介して配線電極１２に接続される。しかし、液晶駆動用
ＩＣ１６には、多くの金属バンプ電極１９が形成されて
おり、金属バンプ電極１９の高さは必ずしも一様ではな
い。Further, when the heights of the metal bump electrodes 19 on the liquid crystal driving IC 16 are the same, as shown in FIG. connected to. However, many metal bump electrodes 19 are formed on the liquid crystal driving IC 16, and the heights of the metal bump electrodes 19 are not necessarily uniform.

【００２９】すなわち、金属バンプ電極１９は通常はメ
ッキ法により形成されるが、その高さにはばらつきがあ
る。出力数１２０の液晶駆動用ＩＣ１６の場合には、金
属バンプ電極１９の数は、たとえば１８２であり、高さ
２３μｍの金属バンプ電極１９のばらつきは、通常±３
．５μｍ、すなわち、約７μｍの高低差がある。That is, the metal bump electrodes 19 are usually formed by a plating method, but their heights vary. In the case of a liquid crystal driving IC 16 with 120 outputs, the number of metal bump electrodes 19 is, for example, 182, and the variation in the metal bump electrodes 19 with a height of 23 μm is usually ±3.
．． There is a height difference of 5 μm, that is, about 7 μm.

【００３０】したがって、導電粒子２３の粒子径が約２
μｍから６μｍである異方性導電接着剤層２１を用いて
ボンディングを行なうと、図６に示すように、金属バン
プ電極１９の高い箇所においては良好な接続が成される
が、金属バンプ電極１９の低い箇所においては、導電粒
子２３が金属バンプ電極１９あるいは配線電極１２とは
接触せず、電気的にオープンが発生するということがし
ばしば起こった。Therefore, the particle diameter of the conductive particles 23 is approximately 2
When bonding is performed using the anisotropic conductive adhesive layer 21 having a thickness of 6 μm to 6 μm, as shown in FIG. At low points, the conductive particles 23 did not come into contact with the metal bump electrodes 19 or the wiring electrodes 12, and electrical open circuits often occurred.

【００３１】そこで、図５に示すように、大きい導電粒
子２３を用いると、高低差のある金属バンプ電極１９の
いずれに対しても、良好な接続が成される。Therefore, as shown in FIG. 5, if large conductive particles 23 are used, a good connection can be made to any of the metal bump electrodes 19 having different heights.

【００３２】そして、導電粒子２３として、粒子径が約
１０μｍ（±１．５　μｍ）の異方性導電接着剤層２１
を用い、接続実験を行なったところ、電気的にオープン
が発生することが無くなった。なお、導電粒子２３の粒
子径の範囲は、たとえば６μｍから２０μｍの範囲で効
果がある。 具体的には、液晶表示装置の接続部の接触抵抗を評価し
たところ、接続箇所１８２に対し、最低値で約０．１Ω
、最大値で１．０Ωであり、オープン発生は１箇所も無
く、また、ショートの発生も無かった。[0032] As the conductive particles 23, an anisotropic conductive adhesive layer 21 having a particle diameter of about 10 μm (±1.5 μm) is used.
When we conducted a connection experiment using this, we found that no electrical open circuits occurred. Note that a range of particle diameters of the conductive particles 23, for example, from 6 μm to 20 μm is effective. Specifically, when the contact resistance of the connection part of the liquid crystal display device was evaluated, the lowest value was about 0.1Ω for the connection point 182.
The maximum value was 1.0Ω, and there were no open circuits or short circuits.

【００３３】また、−３０℃（３０分間）／８５℃（３
０分間）の５００サイクルの熱衝撃試験、温度６５℃湿
度９５％の１０００時間の高温高湿保存試験、８５℃で
１０００時間の高温保存試験、湿度９５％で−１０℃か
ら６５℃の５サイクルの温湿度サイクル試験、動作試験
、振動試験や衝撃試験等の機械試験など、各種信頼性試
験により本発明による液晶表示装置を評価したところ、
接続箇所に起因するオープン、ショートの発生は、皆無
であった。[0033] Also, -30°C (30 minutes)/85°C (30 minutes)
500 cycles of thermal shock test (0 minutes), 1000 hours of high temperature and high humidity storage test at 65°C and 95% humidity, 1000 hours of high temperature storage test at 85°C, 5 cycles from -10°C to 65°C at 95% humidity The liquid crystal display device according to the present invention was evaluated through various reliability tests such as a temperature/humidity cycle test, an operation test, a mechanical test such as a vibration test, and an impact test.
There were no occurrences of opens or shorts caused by connection points.

【００３４】上記実施例として、液晶駆動用ＩＣ１６の
金属バンプ電極１９が金の場合を例にしたが、ニッケル
粒子より柔らかく、ニッケル粒子が良く食い込む金属バ
ンプ電極として、たとえば鉛−錫（ＰｂーＳｎ）系また
は鉛−インジウム（ＰｂーＩｎ）系などの半田バンプ電
極の場合にも適用できる。In the above embodiment, the metal bump electrode 19 of the liquid crystal driving IC 16 is made of gold. However, the metal bump electrode 19, which is softer than nickel particles and into which nickel particles can easily penetrate, may be made of, for example, lead-tin (Pb-Sn). ) type or lead-indium (Pb-In) type solder bump electrodes.

【００３５】また、アルミニウム電極１７上にバリアメ
タルを形成し、メッキ法で形成された金属バンプ電極付
きの半導体素子について説明したが、バリアメタルの構
成は、たとえばプラチナ／チタン（Ｐｔ／Ｔｉ）であっ
ても良く、また、無くても構わない。さらに、メッキ法
以外、たとえばディップ法、ボールボンディング法によ
りバンプ電極が形成された場合にも適用できる。Furthermore, although a semiconductor element with a metal bump electrode formed by a plating method in which a barrier metal is formed on the aluminum electrode 17 has been described, the structure of the barrier metal may be, for example, platinum/titanium (Pt/Ti). It's okay to have it, and it's okay to not have it. Furthermore, the present invention can also be applied to cases where bump electrodes are formed by methods other than plating methods, such as dipping methods and ball bonding methods.

【００３６】また、液晶駆動用ＩＣ１６の下面中央部に
、３ｍｍ×７ｍｍの大きさの異方性導電接着剤層２１が
介在していない導電膜不存在部２４が１箇所ある例につ
いてであるが、この大きさは、ＩＣのサイズ、基板上の
位置認識マーク１３の位置に基づき任意に設定できる。[0036] Also, regarding an example in which there is one conductive film-free area 24 with a size of 3 mm x 7 mm in which the anisotropic conductive adhesive layer 21 is not interposed, in the center of the lower surface of the liquid crystal driving IC 16. , this size can be arbitrarily set based on the size of the IC and the position of the position recognition mark 13 on the board.

【００３７】基板上の認識マークをカメラで認識しやす
いよう、マークの位置周辺に複数個の空間を設けても良
い。[0037] In order to make it easier to recognize the recognition mark on the board with a camera, a plurality of spaces may be provided around the position of the mark.

【００３８】また、ガラス基板１１上に形成された取り
出し電極の配線電極１２をクロム／アルミニウムとした
が、配線電極１２が金属または金属多層膜で、その表面
層に来る材料がアルミニウム、アルミニウム合金以外で
も、たとえばアルミニウム、アルミニウム合金の上に薄
い金属が形成されている場合などでも適用できる。この
様な例として、ガラス基板１１上にモリブデン（Ｍｏ）
アルミニウム（Ａｌ）モリブデン（Ｍｏ）が順次形成さ
れた配線電極１２がある。なお、それぞれの膜厚は、た
とえば、７０ｎｍ、４００ｎｍ、５０ｎｍである。Further, although the wiring electrode 12 of the extraction electrode formed on the glass substrate 11 is made of chromium/aluminum, the wiring electrode 12 is a metal or a metal multilayer film, and the material on the surface layer is other than aluminum or aluminum alloy. However, it can also be applied to cases where thin metal is formed on aluminum or aluminum alloys, for example. As an example of this, molybdenum (Mo) is placed on the glass substrate 11.
There is a wiring electrode 12 in which aluminum (Al) and molybdenum (Mo) are sequentially formed. Note that the respective film thicknesses are, for example, 70 nm, 400 nm, and 50 nm.

【００３９】また、上記装置は、高信頼性の接続部を有
するので、液晶駆動用ＩＣ１６の裏面側から封止樹脂で
覆うことは不要であるが、封止樹脂で覆っても良い。Furthermore, since the above device has a highly reliable connection portion, it is not necessary to cover the back side of the liquid crystal driving IC 16 with a sealing resin, but it may be covered with a sealing resin.

【００４０】さらに、駆動方式が単純マトリクス方式あ
るいはＴＦＴ（薄膜トランジスタ）方式などに限らず、
いずれの方式の液晶表示装置にも適用できる。Furthermore, the driving method is not limited to a simple matrix method or a TFT (thin film transistor) method.
It can be applied to any type of liquid crystal display device.

【００４１】なお、上記各実施例では、液晶表示装置を
例にとり説明したが、液晶表示装置に限定されること無
く、ＩＣなどの半導体装置を基板上に実装した電子装置
のすべてに適用可能である。[0041] In each of the above embodiments, the explanation was given using a liquid crystal display device as an example, but the invention is not limited to liquid crystal display devices and can be applied to all electronic devices in which a semiconductor device such as an IC is mounted on a substrate. be.

【００４２】また、導電膜不存在部を形成することによ
り、高価な異方性導電膜の節約にもなるため、低コスト
化にも有効である。[0042] Furthermore, by forming the conductive film-free portion, the expensive anisotropic conductive film can be saved, so that it is effective for cost reduction.

【００４３】[0043]

【発明の効果】本発明の半導体装置によれば、半導体素
子を異方性導電膜を介して基板に接続する場合、異方性
導電膜の少なくとも一部に異方性導電膜が存在していな
い異方性導電膜不存在部が形成されているため、基板上
の位置決め部に介在しないように異方性導電膜が配置さ
れれば、位置決め部をたとえばカメラで直接見ることも
可能であり、確実に認識され、認識ミスの発生がおこり
ずらくなるため精度の高い接続ができる。また、圧着加
重が低くても異方性導電膜不存在部に異方性導電膜が容
易に流れ出すことができ、半導体素子に損傷を与えるこ
となく低加重で接続できるため、高信頼性および高歩留
りを得ることができる。According to the semiconductor device of the present invention, when a semiconductor element is connected to a substrate via an anisotropic conductive film, the anisotropic conductive film is present in at least a part of the anisotropic conductive film. Therefore, if the anisotropic conductive film is arranged so that it does not interfere with the positioning part on the substrate, it is possible to directly view the positioning part with a camera, for example. , it is reliably recognized, and recognition errors are less likely to occur, allowing for highly accurate connections. In addition, even if the pressure is low, the anisotropic conductive film can easily flow out into the area where the anisotropic conductive film is not present, and the semiconductor element can be connected with a low load without damaging it, resulting in high reliability and high performance. Yield can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の半導体装置の一実施例に係る液晶表示
装置を示す断面図である。FIG. 1 is a sectional view showing a liquid crystal display device according to an embodiment of the semiconductor device of the present invention.

【図２】同上液晶表示装置を製造する工程を示す断面図
である。FIG. 2 is a cross-sectional view showing a process of manufacturing the liquid crystal display device.

【図３】同上液晶表示装置を製造する図２に示すつぎの
工程を示す断面図である。FIG. 3 is a sectional view showing the next step shown in FIG. 2 for manufacturing the liquid crystal display device.

【図４】同上液晶表示装置を製造する図３に示すつぎの
工程を示す断面図である。FIG. 4 is a sectional view showing the next step shown in FIG. 3 for manufacturing the liquid crystal display device.

【図５】同上大きな導電粒子を用いた場合の液晶表示装
置を示す断面図である。FIG. 5 is a cross-sectional view showing a liquid crystal display device using large conductive particles.

【図６】同上小さな導電粒子を用いた場合の液晶表示装
置を示す断面図である。FIG. 6 is a cross-sectional view showing a liquid crystal display device using small conductive particles.

【図７】従来例の液晶表示装置を示す断面図である。FIG. 7 is a sectional view showing a conventional liquid crystal display device.

【図８】同上液晶表示装置を製造する工程を示す断面図
である。FIG. 8 is a cross-sectional view showing a process of manufacturing the liquid crystal display device as described above.

【符号の説明】[Explanation of symbols]

１１　　　　ガラス基板 １２　　　　配線電極 １６　　　　半導体素子としての液晶駆動用ＩＣ２１　
　　　異方性導電膜としての異方性導電接着剤層２４　
　　　異方性導電膜不存在部11 Glass substrate 12 Wiring electrode 16 Liquid crystal driving IC 21 as a semiconductor element
Anisotropic conductive adhesive layer 24 as an anisotropic conductive film
Area without anisotropic conductive film

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　半導体素子に形成されたバンプ電極と
、基板上に形成された電極とを、導電性微片を含む異方
性導電膜を介し電気的に接続した半導体装置において、
前記異方性導電膜は、少なくとも一部に異方性導電膜が
存在していない異方性導電膜不存在部を形成したことを
特徴とする半導体装置。1. A semiconductor device in which a bump electrode formed on a semiconductor element and an electrode formed on a substrate are electrically connected via an anisotropic conductive film containing conductive particles, comprising:
A semiconductor device, wherein the anisotropic conductive film has an anisotropic conductive film-free portion formed in at least a portion thereof.
JP6218291A 1991-03-26 1991-03-26 Semiconductor device Pending JPH04297044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6218291A JPH04297044A (en) 1991-03-26 1991-03-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6218291A JPH04297044A (en) 1991-03-26 1991-03-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04297044A true JPH04297044A (en) 1992-10-21

Family

ID=13192738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6218291A Pending JPH04297044A (en) 1991-03-26 1991-03-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04297044A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330393A (en) * 1995-03-24 1996-12-13 Matsushita Electric Ind Co Ltd Method for bonding ic part to flat panel display
EP0928016A1 (en) * 1997-07-17 1999-07-07 Rohm Co., Ltd. Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card
JPH11243115A (en) * 1998-02-26 1999-09-07 Hitachi Chem Co Ltd Circuit board
JP2004038203A (en) * 1997-07-30 2004-02-05 Seiko Epson Corp Method for manufacturing circuit board unit and method for manufacturing liquid crystal device
JP2004079693A (en) * 2002-08-14 2004-03-11 Sony Corp Semiconductor device and its manufacturing method
JP2019024097A (en) * 2006-01-16 2019-02-14 日立化成株式会社 Conductive adhesive film and solar battery module
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330393A (en) * 1995-03-24 1996-12-13 Matsushita Electric Ind Co Ltd Method for bonding ic part to flat panel display
EP0928016A1 (en) * 1997-07-17 1999-07-07 Rohm Co., Ltd. Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card
EP0928016B1 (en) * 1997-07-17 2008-01-02 Rohm Co., Ltd. Process for manufacturing semiconductor wafer, semiconductor chip, and ic card
JP2004038203A (en) * 1997-07-30 2004-02-05 Seiko Epson Corp Method for manufacturing circuit board unit and method for manufacturing liquid crystal device
JPH11243115A (en) * 1998-02-26 1999-09-07 Hitachi Chem Co Ltd Circuit board
JP2004079693A (en) * 2002-08-14 2004-03-11 Sony Corp Semiconductor device and its manufacturing method
JP2019024097A (en) * 2006-01-16 2019-02-14 日立化成株式会社 Conductive adhesive film and solar battery module
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform

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