JPH0428260A - 半導体チップの実装方法 - Google Patents

半導体チップの実装方法

Info

Publication number
JPH0428260A
JPH0428260A JP2133391A JP13339190A JPH0428260A JP H0428260 A JPH0428260 A JP H0428260A JP 2133391 A JP2133391 A JP 2133391A JP 13339190 A JP13339190 A JP 13339190A JP H0428260 A JPH0428260 A JP H0428260A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
face
semiconductor
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2133391A
Other languages
English (en)
Inventor
Katsuhiro Nakano
中野　克宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2133391A priority Critical patent/JPH0428260A/ja
Publication of JPH0428260A publication Critical patent/JPH0428260A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、基板に複数の半導体チップを実装する場合に
用いる半導体チップの実装方法に関する。
従来の技術 ２ベー／ 従来、複数の半導体チップをフリップチップ方式で基板
に実装する場合、第２図に示すように、基板１上に半導
体チップ２および３が半導体チップ２および３の電極上
に形成されたバンプ４と導電性接着剤５を介して電気的
に接続され、つぎにその上部を絶縁性樹脂６等で被覆し
て実装しているＯ 発明が解決しようとする課題 しかしながら上記従来の構成では、搭載する半導体チッ
プ２および３の数に応じて基板の面積を大きくしていか
なければならないために、実装密度が向上せず、製品の
小型化を著しく阻害するという課題があった。
本発明は、上記従来の課題を解決するものであり、半導
体チップの実装密度を向上し、しだがって電子機器の小
型化に有効な半導体チップの実装方法を提供することを
目的とするものである。
課題を解決するための手段 本発明は上記目的を達成するために、電極部に導電性バ
ンプが形成され接続材料として導電性を３ベ−ノ 有する第一の熱可塑性樹脂を用いて基板上にフェースダ
ウンで実装された第一の半導体チップと、その第一の半
導体チップ上に塗布され絶縁性を有しかつ第一の熱可塑
性樹脂よシ低温度で熱処理可能な第二の熱可塑性樹脂で
第一の半導体チップ上にフェースアップで実装されかつ
基板とはワイヤボンディングによって電気的に接続され
た第二の半導体チップとを封止材料にて一括して封止す
るものである。
作用 したがって本発明によれば、搭載する半導体チップの数
に応じて基板の面積を大きくしていく必要がなく、実装
密度を向上でき、さらには電子機器等の製品の小型化に
も大きな効果を有するものである。
実施例 以下、本発明の一実施例を図面を参照して説明する。第
１図は本発明の一実施例によって実装された半導体チッ
プの断面図であり、図に示すように、第一の半導体チッ
プ７のアルミ電極部（図示せず）に導電性バンプ８が形
成され、接続材料として導電性を有する第一の熱可塑性
樹脂９を介して基板１ｏ上にフェースダウンにて実装さ
れる。
つぎにその第一の半導体チップ７の上に絶縁性を有しか
つ第一の熱可塑性樹脂９よシ低温度にて熱処理可能な第
二の熱可塑性樹脂１１を用いてフェースアップで第二の
半導体チップ１２を実装し、さらにワイヤ１３を用いて
第二の半導体チップ１２のアルミ電極部１４と基板１ｏ
の上面に設けられた配線電極１５とをワイヤボンディン
グによって接続し、その後絶縁性樹脂よりなる封止材料
１６で一括して封止する。
この実施例によれば、搭載する半導体チップの数に応じ
て基板面積を大きくする必要がなく、実装密度を向上す
ることができる。
なお、第二の半導体チップ１２の実装に用いている第二
の熱可塑性樹脂１１の熱処理温度を、第一の半導体チッ
プ７の実装に用いている第一の熱可塑性樹脂９の熱処理
温度よシも低くしているので、第二の半導体チップ１′
２が不良の場合、容易５ペ−ノ に交換することができ、すでに実装済みの第一の半導体
チップγの接続部の信頼性を損うことがない。捷た、絶
縁性樹脂よりなる封止材料１６によって一括して封止で
きるため、封止材料１６の節約に著しく有効である。
発明の効果 本発明は上記実施例よシ明らかなように、２個の半導体
チップをフェイスダウン実装とフェイヌアップ実装を併
用し、フリップチップ接続とワイヤボンディング接続に
よって実装しているため基板上に半導体チップを立体的
に配置することができ、基板の面積を有効に活用して実
・装密度を向上し、したがって電子機器等の製品の小型
化にも役立つものである。
【図面の簡単な説明】
第１図は本発明の一実施例における半導体チップの実装
方法によって形成された半導体チップ実装部の部分断面
図、第２図は従来の実装方法による半導体チップ実装部
の部分断面図である。 ７・・・・・第一の半導体チップ、８・・・・・・導電
性パン６ベーノ プ、９・・・・・・第」の熱可塑性樹脂、１０・・・・
・・基板、１１・・・・・・第二の熱可塑性樹脂、１２
・・・・・・第二の半導体チップ、１３・・・・・・ワ
イヤ、１４・・・・・・アルミ電極部（電極部）、１５
・・・・・・配線電極、１６・・・・・封止材料。

Claims (1)

    【特許請求の範囲】
  1. 　電極部に導電性バンプが形成され接続材料として導電
    性を有する第一の熱可塑性樹脂を用いて基板上にフェー
    スダウンで実装された第一の半導体チップと、その第一
    の半導体チップ上に塗布され絶縁性を有しかつ第一の熱
    可塑性樹脂より低温度で熱処理可能な第二の熱可塑性樹
    脂で前記第一の半導体チップ上にフェースアップで実装
    されかつ基板とはワイヤボンディングによって電気的に
    接続された第二の半導体チップとを封止材料にて一括し
    て封止することを特徴とする半導体チップの実装方法。
JP2133391A 1990-05-23 1990-05-23 半導体チップの実装方法 Pending JPH0428260A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2133391A JPH0428260A (ja) 1990-05-23 1990-05-23 半導体チップの実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2133391A JPH0428260A (ja) 1990-05-23 1990-05-23 半導体チップの実装方法

Publications (1)

Publication Number Publication Date
JPH0428260A true JPH0428260A (ja) 1992-01-30

Family

ID=15103650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2133391A Pending JPH0428260A (ja) 1990-05-23 1990-05-23 半導体チップの実装方法

Country Status (1)

Country Link
JP (1) JPH0428260A (ja)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5714803A (en) * 1995-07-28 1998-02-03 Sgs-Thomson Microelectronics, Inc. Low-profile removable ball-grid-array integrated circuit package
US5872397A (en) * 1996-06-24 1999-02-16 International Business Machines Corporation Semiconductor device package including a thick integrated circuit chip stack
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor
US5909055A (en) * 1996-08-27 1999-06-01 Nec Corporation Chip package device mountable on a mother board in whichever of facedown and wire bonding manners
US5950072A (en) * 1997-07-25 1999-09-07 Stmicroelectronics, Inc. Low-profile removable ball-grid-array integrated circuit package
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
KR20020016278A (ko) * 2000-08-25 2002-03-04 듀흐 마리 에스. 플립 칩 기술 공정에서 개량된 칩 실장 방법
FR2813708A1 (fr) * 2000-09-01 2002-03-08 Orient Semiconductor Elect Ltd Procede ameliore de montage de pastilles dans des processus de technologie a pastilles a protuberances
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6521478B2 (en) * 2001-03-20 2003-02-18 Computech International Ventures Limited Method for manufacturing a low-profile semiconductor device
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
WO2000048444A3 (de) * 1999-02-16 2003-05-22 Wichmann Workx Ag Information Häusung für ein halbleiterchip
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7071567B2 (en) 2002-10-15 2006-07-04 Seiko Epson Corporation Semiconductor device and method of fabrication thereof, optical module and method of fabrication thereof, circuit board, and electronic instrument
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5714803A (en) * 1995-07-28 1998-02-03 Sgs-Thomson Microelectronics, Inc. Low-profile removable ball-grid-array integrated circuit package
US5872397A (en) * 1996-06-24 1999-02-16 International Business Machines Corporation Semiconductor device package including a thick integrated circuit chip stack
US5909055A (en) * 1996-08-27 1999-06-01 Nec Corporation Chip package device mountable on a mother board in whichever of facedown and wire bonding manners
US5950072A (en) * 1997-07-25 1999-09-07 Stmicroelectronics, Inc. Low-profile removable ball-grid-array integrated circuit package
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor
US6157080A (en) * 1997-11-06 2000-12-05 Sharp Kabushiki Kaisha Semiconductor device using a chip scale package
WO2000048444A3 (de) * 1999-02-16 2003-05-22 Wichmann Workx Ag Information Häusung für ein halbleiterchip
US6395578B1 (en) 1999-05-20 2002-05-28 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6650019B2 (en) 2000-07-20 2003-11-18 Amkor Technology, Inc. Method of making a semiconductor package including stacked semiconductor dies
KR20020016278A (ko) * 2000-08-25 2002-03-04 듀흐 마리 에스. 플립 칩 기술 공정에서 개량된 칩 실장 방법
FR2813708A1 (fr) * 2000-09-01 2002-03-08 Orient Semiconductor Elect Ltd Procede ameliore de montage de pastilles dans des processus de technologie a pastilles a protuberances
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6340846B1 (en) 2000-12-06 2002-01-22 Amkor Technology, Inc. Making semiconductor packages with stacked dies and reinforced wire bonds
US7485490B2 (en) 2001-03-09 2009-02-03 Amkor Technology, Inc. Method of forming a stacked semiconductor package
US6521478B2 (en) * 2001-03-20 2003-02-18 Computech International Ventures Limited Method for manufacturing a low-profile semiconductor device
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US7071567B2 (en) 2002-10-15 2006-07-04 Seiko Epson Corporation Semiconductor device and method of fabrication thereof, optical module and method of fabrication thereof, circuit board, and electronic instrument
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US9768124B2 (en) 2007-02-21 2017-09-19 Amkor Technology, Inc. Semiconductor package in package

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