JPH04268098A - Jig for electroplating - Google Patents
Jig for electroplatingInfo
- Publication number
- JPH04268098A JPH04268098A JP2847591A JP2847591A JPH04268098A JP H04268098 A JPH04268098 A JP H04268098A JP 2847591 A JP2847591 A JP 2847591A JP 2847591 A JP2847591 A JP 2847591A JP H04268098 A JPH04268098 A JP H04268098A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- disk
- pins
- ammeters
- conditions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009713 electroplating Methods 0.000 title claims abstract description 18
- 239000012212 insulator Substances 0.000 claims abstract description 3
- 238000007747 plating Methods 0.000 abstract description 42
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 12
- 239000010935 stainless steel Substances 0.000 abstract description 5
- 229910001220 stainless steel Inorganic materials 0.000 abstract description 5
- 229920006362 Teflon® Polymers 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 239000004809 Teflon Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は電解めっき用治具に関し
、特に電解めっきに用いる条件測定用の治具に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jig for electrolytic plating, and more particularly to a jig for measuring conditions used in electrolytic plating.
【０００２】0002
【従来の技術】半導体基板上に電極や配線等を形成する
ために金や銅の電解めっき法が用いられる。この電解め
っきは、例えば図４に示すように、カップ５が設けられ
ためっき槽１０にめっき液８を満し、このめっき液８を
ヒータ１２により所定の温度にしたのちポンプ１４によ
りカップ５内に噴流させ、カップ５内のアノードメッシ
ュ６とカップ５の上方にセットした半導体基板１１との
間に電流を流すことにより行なわれていた。尚図４にお
いて１３はフィルターである。2. Description of the Related Art Electrolytic plating of gold or copper is used to form electrodes, wiring, etc. on a semiconductor substrate. In this electrolytic plating, for example, as shown in FIG. This was done by causing a current to flow between the anode mesh 6 in the cup 5 and the semiconductor substrate 11 set above the cup 5. Note that 13 in FIG. 4 is a filter.
【０００３】この従来の電解めっき法において、半導体
基板１１の被めっき面のめっき厚ばらつきを低減させる
ためには、めっき処理における各パラメーター、例えば
めっき液の流量，アノードメッシュ６の位置と大きさ及
びめっき電流値等を変化させ、各々の条件それぞれにつ
いて半導体基板１１にめっき処理を行ない、被めっき面
のめっき厚のばらつきを測定し、最適な条件を求めてい
た。In this conventional electrolytic plating method, in order to reduce variations in plating thickness on the surface of the semiconductor substrate 11 to be plated, various parameters in the plating process, such as the flow rate of the plating solution, the position and size of the anode mesh 6, and The plating process was performed on the semiconductor substrate 11 under each condition by changing the plating current value, etc., and the variations in the plating thickness on the surface to be plated were measured to find the optimum conditions.
【０００４】0004
【発明が解決しようとする課題】このような従来の電解
めっき法においては、実際に半導体基板にめっき処理を
行ない各々の条件出しする必要があるため、条件出し用
半導体基板の作成，各々の条件でのめっき処理，めっき
厚ばらつき測定等と、多くの工数が必要となる。又各々
の条件でのめっき処理中での状態が連続的に把握するこ
とができないため、条件の最適化が困難であり、精度の
より電解めっきを行うことができないという問題があっ
た。[Problems to be Solved by the Invention] In such conventional electrolytic plating methods, it is necessary to actually perform plating processing on the semiconductor substrate and set each condition. This requires a lot of man-hours, such as plating treatment and measuring variations in plating thickness. Furthermore, since the state during the plating process under each condition cannot be continuously grasped, it is difficult to optimize the conditions, and there is a problem that electrolytic plating cannot be performed due to accuracy.
【０００５】[0005]
【課題を解決するための手段】本発明の電解めっき用治
具は、伝導性の円板と、この円板に絶縁物を介し表面が
円板の表面と同一平面となるように埋め込まれた複数の
導電性のピンと、このピンの裏面に接続された電流計と
を含んで構成される。[Means for Solving the Problems] The electrolytic plating jig of the present invention includes a conductive disk and a conductive disk embedded in the disk through an insulator so that the surface thereof is flush with the surface of the disk. It is composed of a plurality of conductive pins and an ammeter connected to the back side of the pins.
【０００６】[0006]
【実施例】次に本発明の実施例について図面を参照して
説明する。図１（ａ），（ｂ）は本発明の一実施例の上
面図及びＡ−Ａ線断面図である。Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) and 1(b) are a top view and a sectional view taken along the line A-A of an embodiment of the present invention.
【０００７】図１（ａ），（ｂ）において電解めっき用
治具は、半導体基板と同程度の大きさのステンレス製の
円板１と、この円板１に絶縁用のテフロンリング２と共
に表面が円板１の表面と同一平面となるように埋め込ま
れた複数のステンレス製のピン３と、このピン３の裏面
に接続された電流計４とから主に構成される。In FIGS. 1(a) and 1(b), the electrolytic plating jig consists of a stainless steel disk 1 of about the same size as the semiconductor substrate, and a Teflon ring 2 for insulation on the surface of the disk 1. It mainly consists of a plurality of stainless steel pins 3 embedded so that they are flush with the surface of the disk 1, and an ammeter 4 connected to the back surface of the pins 3.
【０００８】図２は本実施例の使用方法を説明するため
のカップ近傍の斜視図である。電解めっきは図４で説明
したように、めっき槽１０内に設けたカップ５内にヒー
タ１２により温度調節されためっき液８を噴流させて、
カップ５の上方にセットされた半導体基板１１にめっき
を施すものであるが、めっき条件を測定する場合は、こ
の半導体基板１１の代りに円板１をセットする。FIG. 2 is a perspective view of the vicinity of the cup for explaining how to use this embodiment. As explained in FIG. 4, electrolytic plating is performed by jetting the plating solution 8 whose temperature is controlled by the heater 12 into the cup 5 provided in the plating tank 10.
The semiconductor substrate 11 set above the cup 5 is plated, but when measuring the plating conditions, the disk 1 is set in place of the semiconductor substrate 11.
【０００９】すなわち図２に示したように、それぞれの
ピン３を裏面より電流計４を介して円板１と共にめっき
電源７のマイナス側へ接続する。そしてカップ５内にあ
るアノードメッシュ６はプラス側へ接続する。ここで、
所定の温度に保もたれためっき液８をポンプ１４によっ
て噴流させることにより円板１およびピン３の表面にめ
っき処理がはじまる。それぞれのピン３につながれた電
流計４には、ピン３にめっきされた量と比例して電流が
流れるため、それぞれのピン３におけるめっき量のばら
つきが一見して読みとることができる。この状態におい
て各々の条件を変化させれば、連続的にめっき量のばら
つきを把握することができ、めっき条件の最適値を求め
ることができる。以下に本実施例の治具を用いて最適条
件を求めた例をあげる。That is, as shown in FIG. 2, each pin 3 is connected to the negative side of a plating power source 7 together with the disk 1 from the back side via an ammeter 4. Then, the anode mesh 6 inside the cup 5 is connected to the positive side. here,
The plating process is started on the surfaces of the disk 1 and the pins 3 by jetting the plating solution 8 maintained at a predetermined temperature using the pump 14. Since current flows through the ammeter 4 connected to each pin 3 in proportion to the amount of plating on each pin 3, variations in the amount of plating on each pin 3 can be read at a glance. By changing each condition in this state, it is possible to continuously grasp variations in the amount of plating, and to determine the optimum value of the plating conditions. An example of finding the optimum conditions using the jig of this example will be given below.
【００１０】図５は本治具を用いて噴流量とピン３部の
電流値ばらつきを求めた例であり、噴流量を増すことに
よって、ピン３部の電流値ばらつきが減少していること
がわかり、噴流量は多い方がよい（例えば１０ｌ／ｍｉ
ｎ程度）ことがわかる。図６は本治具を用いてめっき電
流とピン３部の電流値ばらつきを求めた例である。めっ
き電流を増すことによって、ピン３部の電流値ばらつき
が増加していることがわかり、めっき電流値は少ない方
がよい（例えば２０ｍＡ程度）ことがわかる。[0010] Figure 5 is an example of determining the jet flow rate and the current value dispersion of the three pin parts using this jig. I understand, the larger the jet flow rate, the better (for example, 10 l/mi
(about n). FIG. 6 is an example in which the plating current and the current value variation at the pin 3 portion were determined using this jig. It can be seen that by increasing the plating current, the variation in the current value at the pin 3 portion increases, and it can be seen that the plating current value should be smaller (for example, about 20 mA).
【００１１】このように図５及び図６より、高精度のめ
っき行なうためには、噴流量は多く、めっき電流値を小
さくした方がよいことが分る。このようにして他の条件
であるカップ形状、アノードメッシュ間距離等の最適条
件を求めていくことができる。As described above, it can be seen from FIGS. 5 and 6 that in order to perform highly accurate plating, it is better to have a large jet flow rate and a small plating current value. In this way, other optimum conditions such as cup shape and distance between anode meshes can be determined.
【００１２】図３は本実施例の他の適用例を説明するた
めのめっき槽の一部切り欠き斜視図である。図２の場合
と同様に円板１の表面のみをめっき液８に接するように
、円板１の裏面側を絶縁性の材質でシールすることによ
って、デップ式の電解めっき装置にも適用することが可
能である。FIG. 3 is a partially cutaway perspective view of a plating tank for explaining another example of application of this embodiment. As in the case of Fig. 2, by sealing the back side of the disk 1 with an insulating material so that only the surface of the disk 1 comes into contact with the plating solution 8, it can also be applied to a dip-type electrolytic plating device. is possible.
【００１３】上記実施例では、導電性の円板及びピンを
ステンレスで形成した場合について説明したが、めっき
液と反応しない、白金等他の金属や合金を用いることが
できる。またピンの数を増せばより精度の良い条件を求
めることができる。[0013] In the above embodiment, the conductive disk and pin are made of stainless steel, but other metals or alloys such as platinum that do not react with the plating solution may be used. Furthermore, by increasing the number of pins, more accurate conditions can be obtained.
【００１４】[0014]
【発明の効果】以上説明したように本発明の電解めっき
用治具を用いることにより、半導体基板に電解めっきを
行う場合の条件を連続的に把握することができるため、
めっき条件の最適化が容易になり、精度のよい電解めっ
きを行うことができるという効果を有する。[Effects of the Invention] As explained above, by using the electrolytic plating jig of the present invention, it is possible to continuously grasp the conditions when performing electrolytic plating on a semiconductor substrate.
This has the effect that plating conditions can be easily optimized and electrolytic plating can be performed with high precision.
【図１】本発明の一実施例の上面図及びＡ−Ａ線断面図
。FIG. 1 is a top view and a sectional view taken along line A-A of an embodiment of the present invention.
【図２】実施例を用いた場合のカップ近傍の斜視図。FIG. 2 is a perspective view of the vicinity of the cup when using the embodiment.
【図３】実施例の他の適用例を説明する場合のめっき槽
の斜視図。FIG. 3 is a perspective view of a plating tank for explaining another application example of the embodiment.
【図４】半導体基板のめっき方法を説明するためのめっ
き装置の構成図。FIG. 4 is a configuration diagram of a plating apparatus for explaining a method of plating a semiconductor substrate.
【図５】噴流量とピン部の電流値ばらつきとの関係を示
す図。FIG. 5 is a diagram showing the relationship between the jet amount and the current value variation in the pin portion.
【図６】めっき電流とピン部の電流値ばらつきとの関係
を示す図。FIG. 6 is a diagram showing the relationship between plating current and current value variation at the pin portion.
１ 円板 ２ テフロンリング ３ ピン ４ 電流計 ５ カップ ６ アノードメッシュ ７ めっき電源 ８ めっき液 １０，１０Ａ めっき槽 １１ 半導体基板 １２ ヒーター １３ フィルター １４ ポンプ 1 Disk 2 Teflon ring 3 Pin 4 Ammeter 5 Cups 6 Anode mesh 7 Plating power supply 8 Plating solution 10,10A plating tank 11 Semiconductor substrate 12 Heater 13 Filter 14 Pump
Claims (1)
介し表面が円板の表面と同一平面となるように埋め込ま
れた複数の導電性のピンと、このピンの裏面に接続され
た電流計とを含むことを特徴とする電解めっき用治具。Claim 1: A conductive disk, a plurality of conductive pins embedded in the disk through an insulator so that the surface thereof is flush with the surface of the disk, and a plurality of conductive pins connected to the back surface of the pins. An electrolytic plating jig, comprising: an ammeter;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3028475A JP2734785B2 (en) | 1991-02-22 | 1991-02-22 | Jig for electrolytic plating |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3028475A JP2734785B2 (en) | 1991-02-22 | 1991-02-22 | Jig for electrolytic plating |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04268098A true JPH04268098A (en) | 1992-09-24 |
| JP2734785B2 JP2734785B2 (en) | 1998-04-02 |
Family
ID=12249673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3028475A Expired - Fee Related JP2734785B2 (en) | 1991-02-22 | 1991-02-22 | Jig for electrolytic plating |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2734785B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011063888A (en) * | 1999-05-03 | 2011-03-31 | Freescale Semiconductor Inc | Method for forming copper layer on semiconductor wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5139534A (en) * | 1974-10-01 | 1976-04-02 | Uemura Kogyo Kk | Metsuki denkaikenmanadono denkaishori niokeru denryubunfusokuteihoho |
-
1991
- 1991-02-22 JP JP3028475A patent/JP2734785B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5139534A (en) * | 1974-10-01 | 1976-04-02 | Uemura Kogyo Kk | Metsuki denkaikenmanadono denkaishori niokeru denryubunfusokuteihoho |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011063888A (en) * | 1999-05-03 | 2011-03-31 | Freescale Semiconductor Inc | Method for forming copper layer on semiconductor wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2734785B2 (en) | 1998-04-02 |
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