JPH04243982A - Wiring substrate - Google Patents
Wiring substrateInfo
- Publication number
- JPH04243982A JPH04243982A JP3029481A JP2948191A JPH04243982A JP H04243982 A JPH04243982 A JP H04243982A JP 3029481 A JP3029481 A JP 3029481A JP 2948191 A JP2948191 A JP 2948191A JP H04243982 A JPH04243982 A JP H04243982A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- wiring
- wiring conductor
- sintered body
- mullite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 39
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052863 mullite Inorganic materials 0.000 claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000011800 void material Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 description 33
- 239000000843 powder Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000002994 raw material Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000002245 particle Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012777 electrically insulating material Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000000292 calcium oxide Substances 0.000 description 1
- 235000012255 calcium oxide Nutrition 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体素子収納用パッケ
ージや混成集積回路基板等に使用さる配線基板の改良に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in wiring boards used in semiconductor element storage packages, hybrid integrated circuit boards, and the like.
【０００２】0002
【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路基板等に使用される配線基板は通常、電気絶
縁性で化学的に安定な酸化アルミニウム質焼結体から成
る絶縁基体の表面に配線導体としてタングステンやモリ
ブデン、アルミニウム等の金属を厚膜形成技術、薄膜形
成技術により被着することによって形成されている。[Prior Art] Conventionally, wiring boards used for semiconductor element storage packages, hybrid integrated circuit boards, etc. usually have wiring on the surface of an insulating base made of an electrically insulating and chemically stable aluminum oxide sintered body. It is formed by depositing a metal such as tungsten, molybdenum, or aluminum as a conductor using thick film formation technology or thin film formation technology.
【０００３】しかしながら、近時、半導体素子の大型化
、電気信号の伝播速度の高速化が急激に進み、該半導体
素子を上記半導体素子収納用パッケージや混成集積回路
基板等に収容、搭載した場合、以下に述べる欠点を有し
たものとなる。However, in recent years, the size of semiconductor elements and the speed of propagation of electric signals have rapidly increased, and when the semiconductor elements are housed and mounted in the above-mentioned semiconductor element housing package or hybrid integrated circuit board, etc. It has the following drawbacks.
【０００４】即ち、■半導体素子を構成するシリコンの
熱膨張係数と半導体素子収納用パッケージや混成集積回
路基板等の絶縁基体に使用される酸化アルミニウム質焼
結体の熱膨張係数がそれぞれ３．０ 〜３．５ ×１０
−６／ ℃、６．０ 〜７．５ ×１０−６／ ℃であ
り、大きく相違することから両者に半導体素子を作動さ
せた際等に発生する熱が印加されると両者間に大きな熱
応力が発生し、該熱応力によって半導体素子が破損した
り、半導体素子が絶縁基体より剥離してしまう。That is, (1) the coefficient of thermal expansion of silicon constituting the semiconductor element and the coefficient of thermal expansion of the aluminum oxide sintered body used for the insulating substrate of semiconductor element housing packages, hybrid integrated circuit boards, etc. are each 3.0. ~3.5 ×10
-6/°C, 6.0 to 7.5 × 10-6/°C, and because of the large difference, when the heat generated when operating a semiconductor element is applied to both, a large amount of heat will be generated between the two. Stress is generated, and the semiconductor element may be damaged or peeled off from the insulating base due to the thermal stress.
【０００５】■半導体素子収納用パッケージや混成集積
回路基板等の絶縁基体に使用される酸化アルミニウム質
焼結体はその誘電率が９ 〜１０（ 室温１ＭＨｚ）
と高いため絶縁基体に設けた配線導体を伝わる電気信号
の伝播速度が遅く、そのため電気信号の高速伝播を要求
する半導体素子はその収容、搭載が不可となる。等の欠
点を有していた。[0005] The aluminum oxide sintered body used as an insulating substrate for semiconductor element storage packages and hybrid integrated circuit boards has a dielectric constant of 9 to 10 (at room temperature of 1 MHz).
Because of the high speed, the propagation speed of electrical signals transmitted through the wiring conductor provided on the insulating substrate is slow, making it impossible to accommodate or mount semiconductor devices that require high-speed propagation of electrical signals. It had the following drawbacks.
【０００６】そこで上記欠点を解消するために半導体素
子収納用パッケージや混成集積回路基板等の絶縁基体を
酸化アルミニウム質焼結体に代えて半導体素子を構成す
るシリコンの熱膨張係数（３．０〜３．５ ×１０−６
／ ℃） と近似した熱膨張係数４．０ 〜４．５ ×
１０−６／ ℃を有し、且つ誘電率が６．３ と低いム
ライト質焼結体を使用することが検討されている。Therefore, in order to eliminate the above-mentioned drawbacks, the insulating substrate of the semiconductor element housing package, hybrid integrated circuit board, etc. is replaced with an aluminum oxide sintered body, and the thermal expansion coefficient (3.0~ 3.5 ×10-6
/ °C) approximate thermal expansion coefficient 4.0 ~ 4.5 ×
The use of a mullite sintered body having a temperature of 10-6/°C and a dielectric constant as low as 6.3 is being considered.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このム
ライト質焼結体は一般に粒子径が０．１ 乃至１０．０
μｍ のムライト原料粉末にバインダー及び溶媒を添加
混合して成形するとともに該成形体を高温で焼成するこ
とによって製作されており、該ムライト原料粉末はその
粒子径が０．１ 乃至１０．０μｍ という大きな幅を
有しているためこのムライト原料粉末を焼成し、ムライ
ト質焼結体となす際、粒子径の大きなムライト原料粉末
が粒子径の小さなムライト原料粉末を吸収して異常粒成
長を起こし、その結果、得られるムライト質焼結体は内
表面に多量の気孔ができ、表面に最大径３０μｍ 程度
のボイド（ 穴） が絶縁基体の全表面積に対し６％程
度形成されたものとなっている。そのためこの従来のム
ライト質焼結体表面に薄膜形成技術で微細な配線導体や
抵抗素子を被着形成し、半導体素子収納用パッケージや
混成集積回路基板等を形成すると配線導体が前記絶縁基
体表面のボイドにより断線したり、抵抗素子の厚みに不
均一を生じ、電気抵抗値にバラツキが発生したりしてし
まうという欠点が誘発される。[Problems to be Solved by the Invention] However, this mullite sintered body generally has a particle size of 0.1 to 10.0.
It is manufactured by adding and mixing a binder and a solvent to mullite raw material powder of 1.0 μm, molding it, and firing the molded body at high temperature.The mullite raw material powder has a large particle size of 0.1 to 10.0 μm. When this mullite raw material powder is fired to form a mullite sintered body, the mullite raw material powder with a large particle size absorbs the mullite raw material powder with a small particle size, causing abnormal grain growth. As a result, the obtained mullite sintered body has a large number of pores on its inner surface, and voids (holes) with a maximum diameter of about 30 μm are formed on the surface by about 6% of the total surface area of the insulating substrate. Therefore, when fine wiring conductors and resistive elements are deposited on the surface of this conventional mullite sintered body using thin film formation technology to form packages for storing semiconductor elements, hybrid integrated circuit boards, etc., the wiring conductors are deposited on the surface of the insulating substrate. This leads to drawbacks such as wire breakage due to voids, non-uniformity in the thickness of the resistance element, and variations in electrical resistance values.
【０００８】[0008]
【課題を解決するための手段】本発明は絶縁基体表面に
薄膜形成技術によって配線導体を被着して成る配線基板
において、前記絶縁基体をムライト質焼結体で形成する
とともに絶縁基体表面に形成されるボイドの最大径を２
０．０μｍ以下、絶縁基体の全表面積に対するボイドの
面積を４．０ ％以下としたことを特徴とするものであ
る。[Means for Solving the Problems] The present invention provides a wiring board in which a wiring conductor is adhered to the surface of an insulating substrate by a thin film forming technique, in which the insulating substrate is formed of a mullite sintered body, and the wiring conductor is formed on the surface of the insulating substrate. The maximum diameter of the void to be
It is characterized by having a void area of 0.0 μm or less and a void area of 4.0% or less relative to the total surface area of the insulating substrate.
【０００９】[0009]
【実施例】次に本発明を添付図面に示す実施例に基づき
詳細に説明する。第１図は本発明の配線基板を半導体素
子収納用パッケージに適用した場合の断面図を示し、１
は電気絶縁材料から成る絶縁基体、２ は同じく電気
絶縁材料から成る蓋体である。この絶縁基体１ と蓋体
２ とで半導体素子４ を収容するための絶縁容器３
が構成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail based on embodiments shown in the accompanying drawings. FIG. 1 shows a cross-sectional view when the wiring board of the present invention is applied to a package for storing semiconductor elements.
2 is an insulating base made of an electrically insulating material, and 2 is a lid also made of an electrically insulating material. An insulating container 3 for accommodating a semiconductor element 4 with this insulating base 1 and lid 2
is configured.
【００１０】前記絶縁基体１ はその上面中央部に半導
体素子４ を収容するための凹部が設けてあり、該凹部
底面には半導体素子４ が接着材を介し取着される。The insulating substrate 1 has a recessed portion in the center of its upper surface for accommodating a semiconductor element 4, and the semiconductor element 4 is attached to the bottom surface of the recessed portion through an adhesive.
【００１１】前記絶縁基体１はムライト質焼結体から成
り、該ムライト質焼結体はその熱膨張係数が４．０ 〜
４．５ ×１０−６／ ℃と半導体素子４ を構成する
シリコンの熱膨張係数（３．０〜３．５ ×１０−６／
℃） に近似することから絶縁基体１ 上に半導体素
子４ を取着した後、両者に熱が印加されたとしても両
者間には熱膨張係数の相違に起因した熱応力が発生する
ことは殆どなく、半導体素子４を絶縁基体１ 上に極め
て強固に取着することができる。The insulating substrate 1 is made of a mullite sintered body, and the mullite sintered body has a thermal expansion coefficient of 4.0 to 4.0.
4.5 × 10-6/°C and the thermal expansion coefficient of silicon constituting semiconductor element 4 (3.0 to 3.5 × 10-6/
℃), so even if heat is applied to both after mounting the semiconductor element 4 on the insulating substrate 1, thermal stress due to the difference in thermal expansion coefficient will hardly occur between them. Therefore, the semiconductor element 4 can be attached extremely firmly onto the insulating substrate 1.
【００１２】尚、前記ムライト質焼結体から成る絶縁基
体１は、例えば中心粒径１．５ 〜２．０ μｍ の均
粒のムライト原料粉末に焼結助剤としてのシリカ粉末、
マグネシア粉末、カルシア粉末等と適当な有機溶剤、溶
媒とを添加混合して泥漿状となすとともにこれを従来周
知のドクターブレード法を採用することによってグリー
ンシート（ 生シート） を形成し、しかる後、前記グ
リーンシードに適当な打ち抜き加工を施すとともに高温
（ 約１６００℃） で焼成することによって製作され
る。The insulating substrate 1 made of the mullite sintered body is made of, for example, uniform mullite raw material powder with a center particle diameter of 1.5 to 2.0 μm, silica powder as a sintering aid,
Magnesia powder, calcia powder, etc. are added and mixed with a suitable organic solvent or solvent to form a slurry, and this is then formed into a green sheet by employing the conventionally well-known doctor blade method, and then, It is manufactured by subjecting the green seed to a suitable punching process and firing it at a high temperature (approximately 1600° C.).
【００１３】また前記絶縁基体１ にはタングステン、
モリブデン等の高融点金属粉末から成る多数のメタライ
ズ配線層５ が形成されており、該メタライズ配線層５
の一端には外部電気回路と接続される外部リード端子
６が銀ロウ等のロウ材を介し取着されている。[0013] The insulating base 1 also contains tungsten,
A large number of metallized wiring layers 5 made of high melting point metal powder such as molybdenum are formed.
An external lead terminal 6 to be connected to an external electric circuit is attached to one end of the terminal via a soldering material such as silver solder.
【００１４】前記外部リード端子６ はコバール金属（
Ｆｅ−Ｎｉ−Ｃｏ合金） や４２Ａｌｌｏｙ（Ｆｅ−Ｎ
ｉ 合金） 等の金属から成り、パッケージ内部に収容
する半導体素子４ の各電極を所定の外部電気回路に電
気的に接続する作用を為し、例えば鉄、ニッケル、コバ
ルト等の合金インゴット（ 塊） を従来周知の金属圧
延加工法、打ち抜き加工法を採用し、所定形状に加工す
ることによって得られる。The external lead terminal 6 is made of Kovar metal (
Fe-Ni-Co alloy) and 42Alloy (Fe-N
It serves to electrically connect each electrode of the semiconductor element 4 housed inside the package to a predetermined external electric circuit, and is made of an alloy ingot (lump) of iron, nickel, cobalt, etc. It can be obtained by processing into a predetermined shape using conventionally well-known metal rolling methods and punching methods.
【００１５】また前記絶縁基体１ にはその上面にポリ
イミド樹脂等の有機高分子材料より成る絶縁膜７ とア
ルミニウム（Ａｌ）、銅（Ｃｕ）、クロム（Ｃｒ）、ニ
ッケル（Ｎｉ）等の金属より成る配線導体８が薄膜形成
技術により多層に被着形成されており、該配線導体８
には半導体素子４ の電極がボンディグワイヤ９ を介
し電気的に接続され、また配線導体８ の他部は外部リ
ード端子６ がロウ付けされたメタライズ配線層５ の
一端に接続されている。尚、この場合、配線導体８ は
絶縁基体１ に形成したメタライズ配線層５ に電気的
に接続していることから配線導体８ に半導体素子４
の各電極をボンディングワイヤ９ を介し接続した後、
外部リード端子６ を外部電気回路に接続すれば内部に
収容される半導体素子４ はその各々の電極が配線導体
８ 、メタライズ配線層５ 及び外部リード端子６ を
介して外部電気回路に電気的に接続されることとなる。The insulating substrate 1 also has an insulating film 7 made of an organic polymer material such as polyimide resin on its upper surface and an insulating film 7 made of a metal such as aluminum (Al), copper (Cu), chromium (Cr), or nickel (Ni). A wiring conductor 8 consisting of
The electrode of the semiconductor element 4 is electrically connected to the bonding wire 9 through a bonding wire 9, and the other part of the wiring conductor 8 is connected to one end of the metallized wiring layer 5 to which an external lead terminal 6 is brazed. In this case, since the wiring conductor 8 is electrically connected to the metallized wiring layer 5 formed on the insulating substrate 1, the wiring conductor 8 is connected to the semiconductor element 4.
After connecting each electrode through bonding wire 9,
When the external lead terminal 6 is connected to the external electric circuit, each electrode of the semiconductor element 4 housed inside is electrically connected to the external electric circuit via the wiring conductor 8, the metallized wiring layer 5, and the external lead terminal 6. It will be done.
【００１６】尚、前記絶縁基体上面に被着される配線導
体８ は絶縁基体１がムライト質焼結体から成り、その
誘電率が６．３（室温１ＭＨｚ） と低いことから該配
線導体８ を伝わる電気信号の伝播速度を極めて速いも
のとなすことができ、その結果、半導体素子収納用パッ
ケージ内に電気信号の伝播速度が速い高速駆動の半導体
素子４ を収容することが可能となる。Note that the wiring conductor 8 to be adhered to the upper surface of the insulating substrate is made of a mullite sintered body and has a low dielectric constant of 6.3 (room temperature 1 MHz). The propagation speed of the transmitted electric signal can be made extremely high, and as a result, it becomes possible to accommodate a high-speed driving semiconductor element 4 whose electric signal propagates at a high speed in the semiconductor element housing package.
【００１７】また前記絶縁基体１ を構成するムライト
質焼結体は中心粒径１．５ 〜２．０ μｍ の均粒の
ムライト原料粉末を焼成することによって製作され、焼
成時、粒子径の大きなムライト原料粉末が粒子径の小さ
なムライト原料粉末を吸収して異常粒成長を起こすこと
は一切なく、得られるムライト質焼結体はその表面に形
成されるボイドの最大径が２０．０μｍ 以下、絶縁基
体１ の全表面積に対するボイドの面積が４．０ ％以
下となる。そのため絶縁基体１ の表面に薄膜形成技術
によって配線導体８ を被着したとしても該配線導体８
は絶縁基体１ の表面に形成されたボイドにより断線
することは殆どなく、絶縁基体１ 表面に所定の配線導
体８ を強固に被着形成することができる。The mullite sintered body constituting the insulating substrate 1 is produced by firing uniform mullite raw material powder with a center grain size of 1.5 to 2.0 μm. The mullite raw material powder never absorbs the mullite raw material powder with a small particle size and causes abnormal grain growth, and the obtained mullite sintered body has a void formed on its surface with a maximum diameter of 20.0 μm or less and is insulating. The area of voids with respect to the total surface area of the substrate 1 is 4.0% or less. Therefore, even if the wiring conductor 8 is deposited on the surface of the insulating substrate 1 by thin film formation technology, the wiring conductor 8
There is almost no disconnection due to voids formed on the surface of the insulating substrate 1, and the predetermined wiring conductor 8 can be firmly adhered to the surface of the insulating substrate 1.
【００１８】尚、前記ムライト質焼結体から成る絶縁基
体１表面のボイドはその最大径が２０．０μｍ を越え
るか、或いはボイドの面積が絶縁基体１ の全表面積に
対し４．０ ％を越えると絶縁基体１表面に薄膜形成技
術により配線導体８ を被着させる際、配線導体８ に
多くの断線を発生してしまう。従って、絶縁基体１表面
に形成されるボイドはその最大径が２０．０μｍ 以下
に、また絶縁基体１ の全表面積に対するボイドの面積
が４．０ ％以下に特定される。[0018] The maximum diameter of the voids on the surface of the insulating substrate 1 made of the mullite sintered body exceeds 20.0 μm, or the area of the voids exceeds 4.0% of the total surface area of the insulating substrate 1. When the wiring conductor 8 is deposited on the surface of the insulating substrate 1 using a thin film formation technique, many disconnections occur in the wiring conductor 8. Therefore, the maximum diameter of the voids formed on the surface of the insulating substrate 1 is specified to be 20.0 μm or less, and the area of the voids to the total surface area of the insulating substrate 1 is specified to be 4.0% or less.
【００１９】また前記配線導体８ はまたその露出する
外表面にニッケル、金等の耐蝕性に優れ、且つ良導電性
の金属をメッキにより１．０ 乃至２０．０μｍ の厚
みに層着させておくと配線導体８ の酸化腐食を有効に
防止するとともに配線導体８ にボンディングワイヤ９
を極めて強固に取着させることができる。従って、配
線導体８ の露出する外表面にはニッケル、金等の耐蝕
性に優れ、且つ良導電性である金属をメッキにより１．
０ 乃至２０．０μｍ の厚みに層着させておくことが
好ましい。Further, the wiring conductor 8 is coated with a layer of a corrosion-resistant and highly conductive metal such as nickel or gold on its exposed outer surface by plating to a thickness of 1.0 to 20.0 μm. This effectively prevents oxidation corrosion of the wiring conductor 8 and the bonding wire 9 to the wiring conductor 8.
can be attached extremely firmly. Therefore, the exposed outer surface of the wiring conductor 8 is plated with a metal such as nickel or gold that has excellent corrosion resistance and good conductivity.
It is preferable to form a layer with a thickness of 0 to 20.0 μm.
【００２０】前記配線導体８ はまたその一部 に窒
化タンタル、タンタルシリカ、ニクロム等の抵抗材料を
薄膜形成技術により被着させ、その電気抵抗値を調整す
れば配線導体８ のインピーダンス特性を外部電気回路
のインピーダンス特性に容易に整合させることができ、
また容量素子を被着させておけば配線導体８ に電磁誘
導によってノイズが発生した場合、そのノイズを有効に
除去することが可能となる。更には配線導体８ に抵抗
素子、容量素子を被着形成させておけば、半導体素子収
納用パッケージ内に一つの電気回路を構成することがで
き、該パッケージが搭載される外部の電気回路基板の回
路配線を簡素となすことも可能となる。従って、配線導
体８ にはその一部にインピーダンス特性を整合させる
ための抵抗材料やノイズを有効に除去するための容量素
子を被着形成させておくことが好ましい。The wiring conductor 8 can also be partially coated with a resistive material such as tantalum nitride, tantalum silica, nichrome, etc. using a thin film forming technique, and by adjusting its electric resistance value, the impedance characteristics of the wiring conductor 8 can be adjusted to match the external electric current. Can be easily matched to the impedance characteristics of the circuit,
Further, by attaching a capacitive element, if noise is generated in the wiring conductor 8 due to electromagnetic induction, it becomes possible to effectively remove the noise. Furthermore, by forming a resistive element and a capacitive element on the wiring conductor 8, one electric circuit can be constructed within the package for housing semiconductor elements, and the external electric circuit board on which the package is mounted can be constructed. It is also possible to simplify circuit wiring. Therefore, it is preferable that a resistive material for matching the impedance characteristics and a capacitive element for effectively removing noise be deposited on a portion of the wiring conductor 8.
【００２１】かくして、本発明の配線基板を半導体素子
収納用パッケージに適用した場合、絶縁基体１ の凹部
底面に半導体素子４ を取着固定するとともに、半導体
素子４ の各電極をボンディングワイヤ９ を介し配線
導体８ に電気的に接続し、しかる後、絶縁基体１ の
上面に蓋体２を樹脂等の封止部材で取着し、絶縁容器３
を気密に封止することによって最終製品としての半導
体装置となる。Thus, when the wiring board of the present invention is applied to a package for housing a semiconductor element, the semiconductor element 4 is attached and fixed to the bottom surface of the recess of the insulating base 1, and each electrode of the semiconductor element 4 is connected via the bonding wire 9. The wiring conductor 8 is electrically connected, and then the lid 2 is attached to the top surface of the insulating base 1 with a sealing material such as resin, and the insulating container 3 is closed.
By airtightly sealing the semiconductor device, the final product becomes a semiconductor device.
【００２２】（実験例）次に本発明の作用効果を以下に
述べる実験例に基づき説明する。(Experimental Example) Next, the effects of the present invention will be explained based on the following experimental example.
【００２３】まず表面に形成されているボイドの最大径
及びボイドの面積率（絶縁基体の全表面積に対するボイ
ドの面積） が表１ に示す値である幅５０ｍｍ、長さ
５０ｍｍのムライト質焼結体試料を準備する。First, a mullite sintered body with a width of 50 mm and a length of 50 mm has the maximum diameter of voids formed on the surface and the void area ratio (area of voids relative to the total surface area of the insulating substrate) shown in Table 1. Prepare the sample.
【００２４】次に前記ムライト質焼結体試料の表面に薄
膜形成技術の一つである蒸着法により幅２０．０μｍ
、長さ１０ｍｍ、厚さ５．０ｍｍのアルミニウムから成
る配線導体を５０本被着させ、しかる後、各配線導体の
両端に断線測定器の端子を当接させるとともに各配線導
体の断線状態を調べ、断線している配線導体の数を求め
るとともに断線比率を算出した。Next, a film with a width of 20.0 μm was applied to the surface of the mullite sintered body sample by vapor deposition, which is one of the thin film forming techniques.
, 50 wiring conductors made of aluminum with a length of 10 mm and a thickness of 5.0 mm were deposited, and then the terminals of a disconnection measuring device were brought into contact with both ends of each wiring conductor, and the disconnection state of each wiring conductor was checked. The number of disconnected wiring conductors was determined, and the disconnection ratio was calculated.
【００２５】尚、試料番号１ は本発明と比較するため
の比較試料であり、従来一般に使用されているムライト
質焼結体である。Sample No. 1 is a comparative sample for comparison with the present invention, and is a mullite sintered body commonly used in the past.
【００２６】上記の結果を表１ に示す。The above results are shown in Table 1.
【００２７】[0027]
【表１】[Table 1]
【００２８】[0028]
【発明の効果】以上、実験結果からも判るように表面に
最大径が３０．０μｍ でボイドの面積率が６．０ ％
であるムライト質焼結体を絶縁基体として使用したもの
（試料番号 １）はその表面に配線導体を被着しても被
着された配線導体のうち５４％が断線してしまうのに対
し、本発明のムライト質焼結体を絶縁基体として使用し
たものは配線導体の断線率が１０％以下であり、特にボ
イドの最大径を１０．０μｍ 以下、或いはボイドの面
積率を１．０ ％以下とすると配線基板の断線率を２
％以下までさげることができる。[Effect of the invention] As can be seen from the above experimental results, the maximum diameter of the surface is 30.0 μm and the area ratio of voids is 6.0%.
In the case of using a mullite sintered body as an insulating substrate (sample number 1), even if wiring conductors were applied to the surface, 54% of the applied wiring conductors were disconnected. When the mullite sintered body of the present invention is used as an insulating substrate, the disconnection rate of the wiring conductor is 10% or less, and in particular, the maximum diameter of voids is 10.0 μm or less, or the area ratio of voids is 1.0% or less. Then, the disconnection rate of the wiring board is 2
It can be reduced to below %.
【００２９】従って、本発明の配線基板にいてはムライ
ト質焼結体から成る絶縁基体の表面に薄膜形成技術によ
って配線導体を断線を生じることなく強固に取着するこ
とが可能となる。Therefore, in the wiring board of the present invention, it is possible to firmly attach the wiring conductor to the surface of the insulating base made of the mullite sintered body by the thin film forming technique without causing disconnection.
【図１】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the wiring board of the present invention applied to a package for housing semiconductor elements.
１・・絶縁基体 ８・・薄膜形成技術による配線導体 1. Insulating base 8. Wiring conductor using thin film formation technology
Claims (1)
導体を被着して成る配線基板において、前記絶縁基体を
ムライト質焼結体で形成するとともに絶縁基体表面に形
成されるボイドの最大径を２０．０μｍ以下、絶縁基体
の全表面積に対するボイドの面積を４．０ ％以下とし
たことを特徴とする配線基板。1. A wiring board in which a wiring conductor is adhered to the surface of an insulating substrate by a thin film formation technique, wherein the insulating substrate is formed of a mullite sintered body, and the maximum diameter of a void formed on the surface of the insulating substrate is A wiring board characterized in that the void area is 20.0 μm or less and the area of voids is 4.0% or less with respect to the total surface area of the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2948191A JP2962846B2 (en) | 1991-01-29 | 1991-01-29 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2948191A JP2962846B2 (en) | 1991-01-29 | 1991-01-29 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04243982A true JPH04243982A (en) | 1992-09-01 |
| JP2962846B2 JP2962846B2 (en) | 1999-10-12 |
Family
ID=12277280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2948191A Expired - Fee Related JP2962846B2 (en) | 1991-01-29 | 1991-01-29 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962846B2 (en) |
-
1991
- 1991-01-29 JP JP2948191A patent/JP2962846B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2962846B2 (en) | 1999-10-12 |
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