JP2962921B2 - Manufacturing method of semiconductor device storage package - Google Patents
Manufacturing method of semiconductor device storage packageInfo
- Publication number
- JP2962921B2 JP2962921B2 JP3608592A JP3608592A JP2962921B2 JP 2962921 B2 JP2962921 B2 JP 2962921B2 JP 3608592 A JP3608592 A JP 3608592A JP 3608592 A JP3608592 A JP 3608592A JP 2962921 B2 JP2962921 B2 JP 2962921B2
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- semiconductor element
- insulating base
- wiring layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Electroplating Methods And Accessories (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は高密度集積回路素子のよ
うな極めて多数の電極を有する半導体素子を収容するた
めの半導体素子収納用パッケージの製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device housing package for housing a semiconductor device having an extremely large number of electrodes such as a high density integrated circuit device.
【０００２】[0002]
【従来技術及びその課題】従来、高密度集積回路素子の
ような極めて多数の電極を有する半導体素子を収容する
ための半導体素子収納用パッケージは図3 に示すよう
に、アルミナセラミックス等の電気絶縁材料からなる絶
縁基体21と椀状の蓋体22とから構成されており、絶縁基
体21の上面には半導体素子23が載置固定される載置部B
と該半導体素子23の各電極が接続される薄膜配線層24
が、また下面には半導体素子23を外部電気回路に接続す
る複数個の外部リード端子25が、さらに内部には前記薄
膜配線層24と外部リード端子25を接続するメタライズ配
線層26が取着形成されている。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element having an extremely large number of electrodes, such as a high-density integrated circuit element, is made of an electrically insulating material such as alumina ceramic as shown in FIG. A mounting portion B on which a semiconductor element 23 is mounted and fixed on the upper surface of the insulating base 21.
And the thin film wiring layer 24 to which each electrode of the semiconductor element 23 is connected.
A plurality of external lead terminals 25 for connecting the semiconductor element 23 to an external electric circuit are formed on the lower surface, and a metallized wiring layer 26 for connecting the thin film wiring layer 24 and the external lead terminals 25 is formed inside. Have been.
【０００３】かかる従来の半導体素子収納用パッケージ
は絶縁基体21の上面に設けた半導体素子載置部B 上に半
導体素子23を接着剤を介して載置固定するとともに半導
体素子23の各電極を薄膜配線層24にボンディングワイヤ
27を介して接続させ、しかる後、前記絶縁基体21の上面
外周部に椀状蓋体22の下面を樹脂、ガラス、ロウ材等の
封止材により接合させ、絶縁基体21と蓋体22とで構成さ
れる容器内部に半導体素子23を気密に封止することによ
って最終製品としての半導体装置となる。In such a conventional package for housing a semiconductor element, a semiconductor element 23 is mounted and fixed on a semiconductor element mounting portion B provided on the upper surface of an insulating base 21 with an adhesive, and each electrode of the semiconductor element 23 is thinned. Bonding wire on wiring layer 24
27, and thereafter, the lower surface of the bowl-shaped lid 22 is joined to the outer peripheral portion of the upper surface of the insulating substrate 21 with a sealing material such as a resin, glass, or brazing material. A semiconductor device as a final product is obtained by hermetically sealing the semiconductor element 23 inside the container constituted by.
【０００４】尚、前記半導体素子収納用パッケージは通
常、外部リード端子25の表面にニッケル、金等のメッキ
金属層28が電解メッキ方法により層着されており、該メ
ッキ金属層28によって外部リード端子25が酸化腐食する
のを防止したり、外部リード端子25と外部電気回路との
電気的接続を良好なものとしている。In the package for accommodating a semiconductor element, a plating metal layer 28 of nickel, gold, or the like is usually formed on the surface of the external lead terminal 25 by an electrolytic plating method. This prevents oxidation corrosion of the external lead terminal 25 and improves the electrical connection between the external lead terminal 25 and the external electric circuit.
【０００５】また前記外部リード端子25表面へのメッキ
金属層28の層着は、外部リード端子25の数が数十乃至数
百、多い時には数千本もあり、且つその各々が互いに電
気的に独立しているため全ての外部リード端子25の表面
にメッキ金属層28を層着させる場合、外部リード端子25
の一本一本をそれぞれ別個に電解メッキしなければなら
ず、その作業性が極めて煩雑であるため通常は次の方
法、即ち、(1) まず絶縁基体21に取着形成した薄膜配線
層24と外部リード端子25とを接続するメタライズ配線層
26のそれぞれから引き出しパターン29を分岐させてメタ
ライズ配線層26の一部を絶縁基体21の側面に導出させる
とともに該導出部を絶縁基体21の側面に被着させた接続
導体30で共通に接続し、(2) 次に前記各外部リード端子
25の外表面に電解メッキ方法により一度にメッキ金属層
28を層着させ、(3) 最後に前記各メタライズ配線層26を
共通に接続する接続導体30を絶縁基体21側面から除去
し、各メタライズ配線層26を個々に電気的に接続させる
ことによって全ての外部リード端子25の外表面に一度に
メッキ金属層28を層着させている。The number of external lead terminals 25 to be deposited on the surface of the external lead terminals 25 is several tens to several hundreds, and when the number of external lead terminals 25 is large, there are several thousands. Since the plating metal layer 28 is layered on the surface of all the external lead terminals 25 because they are independent, the external lead terminals 25
Each of these must be separately electroplated, and the workability is extremely complicated.Therefore, usually, the following method is used: (1) First, the thin film wiring layer 24 formed by attaching to the insulating base 21 first. Metallization wiring layer that connects the external lead terminals 25
Each of the lead patterns 29 is branched from each of them, and a part of the metallized wiring layer 26 is led out to the side surface of the insulating base 21, and the lead-out portion is commonly connected by a connection conductor 30 attached to the side surface of the insulating base 21. (2) Next, each of the external lead terminals
25 plating metal layer at once on the outer surface by electrolytic plating method
(3) Finally, the connection conductor 30 that connects the metallized wiring layers 26 in common is removed from the side surface of the insulating base 21 and all the metallized wiring layers 26 are individually electrically connected to each other. The plating metal layer 28 is deposited on the outer surface of the external lead terminal 25 at a time.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、各外部リ
ード端子25の表面にメッキ金属層28を一度に層着させる
ために各メタライズ配線層26の個々には引き出しパター
ン29が分岐されている。そのためこのメタライズ配線層
26を介して半導体素子23と外部電気回路との間で電気信
号の出し入れを行った場合、メタライズ配線層26を伝達
する電気信号は引き出しパターン29の分岐部及び引き出
しパターン29の先端で反射が起こり、これがノイズとな
って信号に入り込むとともに半導体素子23に伝達され、
半導体素子23に誤動作を起こさせるという欠点を有して
いた。However, in this conventional package for accommodating a semiconductor element, each metallized wiring layer 26 is individually formed in order to deposit a plated metal layer 28 on the surface of each external lead terminal 25 at one time. In the drawing, the drawer pattern 29 is branched. Therefore, this metallized wiring layer
When an electric signal is transmitted and received between the semiconductor element 23 and the external electric circuit through the electric circuit 26, the electric signal transmitted through the metallized wiring layer 26 is reflected at a branch portion of the extraction pattern 29 and at the tip of the extraction pattern 29. This becomes noise and enters the signal and is transmitted to the semiconductor element 23,
The semiconductor device 23 has a drawback of causing a malfunction.
【０００７】[0007]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的はメタライズ配線層から引き出しパターン
を分岐させることなく全ての外部リード端子の表面にメ
ッキ金属層を一度に層着させることができる半導体素子
収納用パッケージの製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to deposit a plating metal layer on the surface of all external lead terminals at once without branching a drawing pattern from a metallized wiring layer. It is an object of the present invention to provide a method of manufacturing a semiconductor device housing package that can be used.
【０００８】[0008]
【課題を解決するための手段】本発明は、上面に薄膜配
線層が被着され、下面にメッキ金属層で被覆された外部
リード端子がロウ付けされた絶縁基体と蓋体とから成
り、内部に半導体素子を収容するための空所を有する半
導体素子収納用パッケージであって、前記絶縁基体は下
記(1) 乃至(5) の工程により形成されていることを特徴
とするものである。 (1) 絶縁基体に複数個のスルーホールを形成するととも
に該スルーホールを介して絶縁基体の上面から下面にか
けて複数個のメタライズ配線層を形成する工程と、(2)
前記絶縁基体の下面に導出させたメタライズ配線層の個
々に外部リード端子をロウ付けする工程と、(3) 前記絶
縁基体の上面に金属薄膜を、メタライズ配線層の全てが
共通に電気的接続されるようにして被着させるとともに
該金属薄膜の表面を樹脂膜で被覆する工程と、(4) 前記
外部リード端子の表面にメッキ金属層を層着させ、該メ
ッキ金属層で外部リード端子の表面を被覆する工程と、
(5) 前記絶縁基体上面の樹脂膜を除去するとともに金属
薄膜を所定パターンにエッチング加工し、薄膜配線層と
なす工程。SUMMARY OF THE INVENTION The present invention comprises an insulating base and a lid, on which a thin film wiring layer is attached on the upper surface, and external lead terminals covered with a plating metal layer on the lower surface are brazed. Wherein the insulating substrate is formed by the following steps (1) to (5). (1) forming a plurality of through holes in the insulating substrate and forming a plurality of metallized wiring layers from the upper surface to the lower surface of the insulating substrate through the through holes; (2)
A step of brazing external lead terminals to each of the metallized wiring layers led out to the lower surface of the insulating base, and (3) a metal thin film on the upper surface of the insulating base, and all of the metallized wiring layers are electrically connected in common. (4) applying a plating metal layer on the surface of the external lead terminal, and coating the surface of the external lead terminal with the plating metal layer. A step of coating;
(5) A step of removing the resin film on the upper surface of the insulating base and etching the metal thin film into a predetermined pattern to form a thin film wiring layer.
【０００９】[0009]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
【００１０】図1 は本発明の製造方法によって製造され
る半導体素子収納用パッケージの一実施例を示し、1 は
絶縁基体、2 は蓋体である。この絶縁基体1 と蓋体2 と
で内部に半導体素子4 を収容する容器3 が構成される。FIG. 1 shows an embodiment of a semiconductor device housing package manufactured by the manufacturing method of the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 3 for housing the semiconductor element 4 therein.
【００１１】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その上面略
中央部に半導体素子を載置固定する載置部A を有し、該
載置部A に半導体素子4 が接着剤を介し固定される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. And a semiconductor element 4 is fixed to the mounting portion A via an adhesive.
【００１２】前記絶縁基体1 はまたその上面で半導体素
子載置部A 周辺から外周方向に延びる複数個の薄膜配線
層5 が被着されており、該薄膜配線層5 の半導体素子載
置部Ａ周辺には半導体素子4 の各電極がボンディングワ
イヤ6 を介して接続され、また外周方向に延ばした部位
は絶縁基体1 の上面からスルーホール( 貫通孔) を介し
下面にかけて形成したメタライズ配線層7 に接続され
る。On the upper surface of the insulating substrate 1, a plurality of thin film wiring layers 5 extending from the periphery of the semiconductor element mounting portion A to the outer peripheral direction are adhered. In the periphery, each electrode of the semiconductor element 4 is connected via a bonding wire 6, and a portion extending in the outer peripheral direction is connected to a metallized wiring layer 7 formed from the upper surface of the insulating base 1 to the lower surface via a through hole (through hole). Connected.
【００１３】前記薄膜配線層5 はアルミニウム等の金属
材料から成り、半導体素子4 の各電極をメタライズ配線
層7 に電気的に接続する作用を為す。The thin-film wiring layer 5 is made of a metal material such as aluminum, and functions to electrically connect each electrode of the semiconductor element 4 to the metallized wiring layer 7.
【００１４】また前記薄膜配線層5 が接続されるメタラ
イズ配線層7 はその絶縁基体1 下面において外部リード
端子8 が銀ロウ等のロウ材を介してロウ付けされてお
り、該メタライズ配線層7 は薄膜配線層5 を介して接続
された半導体素子4 の電極を外部電気回路に接続される
外部リード端子8 に電気的に接続する作用を為す。The metallized wiring layer 7 to which the thin film wiring layer 5 is connected has external lead terminals 8 brazed on the lower surface of the insulating base 1 via a brazing material such as silver brazing. It functions to electrically connect the electrodes of the semiconductor element 4 connected via the thin film wiring layer 5 to the external lead terminals 8 connected to the external electric circuit.
【００１５】更に前記メタライズ配線層7 にロウ付けさ
れる外部リード端子8 はコバール金属(Fe-Ni-Co 合金)
や42アロイ(Fe-Ni合金) 等の金属材料から成り、該外部
リード端子8 は半導体素子4 の各電極を直接、外部電気
回路に接続する作用を為す。Further, external lead terminals 8 brazed to the metallized wiring layer 7 are made of Kovar metal (Fe-Ni-Co alloy).
The external lead terminal 8 serves to connect each electrode of the semiconductor element 4 directly to an external electric circuit.
【００１６】尚、前記外部リード端子8 はコバール金属
等のインゴット( 塊) を従来周知の圧延加工法や打ち抜
き加工法等、従来周知の金属加工法を採用することによ
って所定形状に形成され、その一端がメタライズ配線層
7 に銀ロウ等のロウ材を介しロウ付けされる。The external lead terminals 8 are formed into a predetermined shape by employing a conventionally known metal working method such as a known rolling method or a punching method for ingots (lumps) of Kovar metal or the like. One end is metallized wiring layer
7 is brazed through a brazing material such as silver brazing.
【００１７】また前記外部リード端子8 はその外表面に
ニッケル、金等の耐蝕性に優れ、且つ良導電性である金
属材料から成るメッキ金属層9 が従来周知の電解メッキ
法によって1.0 乃至20.0μm の厚みに層着されており、
これによって外部リード端子8 は酸化腐食するのが有効
に防止されるとともに外部リード端子8 と外部電気回路
との電気的接続が良好なもとなる。The external lead terminal 8 is provided on its outer surface with a plating metal layer 9 made of a metal material having excellent corrosion resistance and good conductivity, such as nickel or gold, having a thickness of 1.0 to 20.0 μm by a conventionally known electrolytic plating method. It is layered to the thickness of
This effectively prevents the external lead terminals 8 from being oxidized and corroded, and provides a good electrical connection between the external lead terminals 8 and an external electric circuit.
【００１８】かくしてこの半導体素子収納用パッケージ
では、絶縁基体1 上面の半導体素子載置部A に半導体素
子4 を接着剤を介して固定するとともに該半導体素子4
の各電極を薄膜配線層5 にボンディングワイヤ6 を介し
て接続し、しかる後、絶縁基体1 の上面外周部に椀状蓋
体2 の下面を樹脂、ガラス、ロウ材等から成る封止材に
より接合させ、絶縁基体1 と蓋体2 とから成る容器3 内
部に半導体素子4 を気密に収容することによって最終製
品としての半導体装置となる。Thus, in this semiconductor element housing package, the semiconductor element 4 is fixed to the semiconductor element mounting portion A on the upper surface of the insulating base 1 via an adhesive, and
Each electrode is connected to the thin film wiring layer 5 via a bonding wire 6, and then the lower surface of the bowl-shaped lid 2 is formed on the outer periphery of the upper surface of the insulating base 1 with a sealing material made of resin, glass, brazing material or the like. The semiconductor device 4 is bonded and airtightly accommodated in a container 3 including an insulating base 1 and a lid 2 to obtain a semiconductor device as a final product.
【００１９】次に上述の半導体素子収納用パッケージに
おける絶縁基体の製造方法について図2(a)乃至(e) によ
り説明する。Next, a method of manufacturing the insulating base in the above-mentioned semiconductor device housing package will be described with reference to FIGS. 2 (a) to 2 (e).
【００２０】まず図2(a)に示す如く、絶縁基体1 に複数
個のスルーホールa を形成するとともに該スルーホール
a を介して絶縁基体1 の上面から下面にかけて複数個の
メタライズ配線層7 を形成する。First, as shown in FIG. 2A, a plurality of through holes a are formed in the insulating base 1 and the through holes a are formed.
A plurality of metallized wiring layers 7 are formed from the upper surface to the lower surface of the insulating base 1 via a.
【００２１】前記絶縁基体1 は、酸化アルミニウム質焼
結体、窒化アルミニウム質焼結体等の電気絶縁材料から
成り、例えば酸化アルミニウム質焼結体から成る場合、
アルミナ(Al 2 O 3 ) 、シリカ(SiO2 ) 、カルシア(Ca
O) 、マグネシア(MgO) 等のセラミック原料粉末に適当
な有機溶剤、溶媒を添加混合して泥漿状となすとともに
これを従来周知のドクターブレード法やカレンダーロー
ル法等を採用し、シート状に成形してセラミックグリー
ンシートを得、次に前記セラミックグリーンシートを打
ち抜き加工法により所定形状となすとともに高温(1600
℃）で焼成することによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body or an aluminum nitride sintered body.
Alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (Ca
O), magnesia (MgO) and other ceramic raw material powders are mixed with a suitable organic solvent and solvent to form a slurry, which is then formed into a sheet by using the well-known doctor blade method or calendar roll method. To obtain a ceramic green sheet, and then form the ceramic green sheet into a predetermined shape by a
C).
【００２２】また前記絶縁基体1 に設けられるスルーホ
ールa は絶縁基体1 となるセラミックグリーンシートに
従来周知の孔明け加工法を施すことによって所定位置に
形成される。The through-hole a provided in the insulating base 1 is formed at a predetermined position by subjecting a ceramic green sheet serving as the insulating base 1 to a conventionally known drilling method.
【００２３】更に前記絶縁基体1 に設けたスルーホール
a を介して絶縁基体1 の上面から下面にかけて形成され
るメタライズ配線層7 はタングステン、モリブデン、マ
ンガン等の高融点金属粉末から成り、該タングステン等
の高融点金属粉末に適当な有機溶剤、溶媒を添加混合し
て得た金属ペーストを絶縁基体1 となるセラミックグリ
ーンシートの上下面及びスルーホールa 内に予め従来周
知のスクリーン印刷法を採用し印刷充填しておくことに
よって形成される。Further, through holes provided in the insulating base 1
The metallized wiring layer 7 formed from the upper surface to the lower surface of the insulating base 1 through a is made of a refractory metal powder such as tungsten, molybdenum, manganese, etc., and an appropriate organic solvent or solvent is added to the refractory metal powder such as tungsten. The metal paste obtained by addition and mixing is formed by printing and filling the upper and lower surfaces of the ceramic green sheet serving as the insulating substrate 1 and the through holes a in advance by using a conventionally known screen printing method.
【００２４】次に図2(b)に示す如く、前記絶縁基体1 に
設けたメタライズ配線層7 のうち絶縁基体1 の下面に導
出させた部位に外部リード端子8 をロウ付けする。Next, as shown in FIG. 2B, an external lead terminal 8 is brazed to a portion of the metallized wiring layer 7 provided on the insulating base 1 and led out to the lower surface of the insulating base 1.
【００２５】前記外部リード端子8 のロウ付けはメタラ
イズ配線層7 に銀ロウ等のロウ材と外部リード端子8 を
順次載置させ、しかる後、これを約850 ℃の温度に加熱
し、ロウ材を加熱溶融させることによって行われる。The external lead terminals 8 are brazed by sequentially placing a brazing material such as silver brazing and the external lead terminals 8 on the metallized wiring layer 7 and then heating them to a temperature of about 850 ° C. Is heated and melted.
【００２６】次に図2(c)に示す如く、前記下面に外部リ
ード端子8 をロウ付けした絶縁基体1 の上面に金属薄膜
5aを、メタライズ配線層7 の全てが共通に電気的接続さ
れるようにして被着させるとともに該金属薄膜7 の表面
を樹脂膜10で被覆する。Next, as shown in FIG. 2 (c), a metal thin film is formed on the upper surface of the insulating base 1 with the external lead terminals 8 brazed to the lower surface.
5a is applied so that all of the metallized wiring layers 7 are electrically connected in common, and the surface of the metal thin film 7 is covered with a resin film 10.
【００２７】前記金属薄膜5aはアルミニウム等の金属材
料からなり、従来周知の蒸着法やスパッタリング法等の
薄膜形成技術よって絶縁基体1 の上面に厚さ約 5.0μm
程度に被着される。The metal thin film 5a is made of a metal material such as aluminum, and has a thickness of about 5.0 μm on the upper surface of the insulating substrate 1 by a known thin film forming technique such as a vapor deposition method or a sputtering method.
Deposited to a degree.
【００２８】前記金属薄膜5aは絶縁基体1 上に形成する
薄膜配線層5 となるとともに後述する外部リード端子8
の外表面にメッキ金属層9 を電解メッキ法により層着さ
せる際、全ての外部リード端子8 を共通に接続する共通
接続導体としての作用をなす。The metal thin film 5a becomes a thin film wiring layer 5 formed on the insulating base 1 and an external lead terminal 8 described later.
When the plating metal layer 9 is layered on the outer surface of the substrate by electrolytic plating, it acts as a common connection conductor for connecting all the external lead terminals 8 in common.
【００２９】また前記金属薄膜5a上に被着されている樹
脂膜10は外部リード端子8 の外表面にメッキ金属層9 を
電解メッキ法により層着させる際、金属薄膜5aにメッキ
金属層9 が層着されるのを有効に防止する作用を為し、
環化イソプレン等の樹脂を従来周知のスクリーン印刷法
やスピンコート法等により約10〜50μm 程度の厚みに被
着させることによって、或いはポリエステルから成るシ
ールを貼着することによって形成される。When the plating metal layer 9 is applied to the outer surface of the external lead terminal 8 by electrolytic plating, the plating metal layer 9 is formed on the metal thin film 5a. Acts to effectively prevent layering,
It is formed by applying a resin such as cyclized isoprene to a thickness of about 10 to 50 μm by a conventionally known screen printing method, spin coating method, or the like, or by attaching a polyester seal.
【００３０】次に図2(d)に示す如く、前記絶縁基体1 の
下面に被着させた外部リード端子８の外表面にメッキ金
属層９ を層着させ、メッキ金属層9 によって外部リー
ド端子8 を被覆する。Next, as shown in FIG. 2D, a plating metal layer 9 is deposited on the outer surface of the external lead terminal 8 attached to the lower surface of the insulating base 1, and the external lead terminal is formed by the plating metal layer 9. 8 is coated.
【００３１】前記メッキ金属層9 はニッケル、金等の耐
蝕性に優れ、且つ良導電性の金属から成り、従来周知の
電解メッキ法により1.0 乃至20.0μm の厚みに層着され
る。The plating metal layer 9 is made of a metal having excellent corrosion resistance and good conductivity, such as nickel or gold, and is deposited to a thickness of 1.0 to 20.0 μm by a conventionally well-known electrolytic plating method.
【００３２】また前記外部リード端子8 の外表面を電解
メッキ法によりメッキ金属層9 を被着させる場合、各外
部リード端子8 はそれがロウ付けされているメタライズ
配線層8 を金属薄膜5aで共通に接続しているため、1 つ
の外部リード端子8 に電解メッキの電力を印加すれば全
ての外部リード端子8 表面にメッキ金属層9 を均一厚み
に層着させることができ、外部リード端子8 へのメッキ
金属層9 の層着の作業性が大幅に向上する。When a plating metal layer 9 is applied to the outer surface of the external lead terminal 8 by electrolytic plating, each external lead terminal 8 shares the metallized wiring layer 8 to which it is brazed with a metal thin film 5a. When the electrolytic plating power is applied to one external lead terminal 8, the plating metal layer 9 can be deposited on the surface of all the external lead terminals 8 to a uniform thickness. The workability of depositing the plated metal layer 9 is greatly improved.
【００３３】更に前記各外部リード端子8 の表面に電解
メッキ法によりメッキ金属層9 を一度に層着させる場
合、各外部リード端子8 がロウ付けされているメタライ
ズ配線層8 はその各々が金属薄膜5aで共通に接続されて
いるためメタライズ配線層8 にわざわざ引き出しパター
ンを分岐させる必要は一切なく、その結果、メタライズ
配線層8 を伝達する電気信号が引き出しパターンの分岐
部、或いは引き出しパターンの先端部で反射し、ノイズ
を発生することはなく、該ノイズが半導体素子に伝達さ
れて半導体素子に誤動作を起こさせることもない。Further, when a plating metal layer 9 is deposited on the surface of each of the external lead terminals 8 at a time by electrolytic plating, the metallized wiring layers 8 to which the external lead terminals 8 are brazed are each made of a metal thin film. Since the connection is common in 5a, there is no need to branch the extraction pattern to the metallization wiring layer 8 at all, and as a result, the electric signal transmitted through the metallization wiring layer 8 may be branched into the extraction pattern or the leading end of the extraction pattern. Does not generate noise, and the noise is not transmitted to the semiconductor element to cause the semiconductor element to malfunction.
【００３４】そして最後に前記絶縁基体1 はその上面に
被着させた樹脂膜10を除去するとともに金属配線5aをフ
ォトリソグラフィー技術等により所定パターンの薄膜配
線層5 となすことによって図2(e)に示す如く、製品とし
ての絶縁基体1 が完成する。Finally, the insulating substrate 1 is formed by removing the resin film 10 deposited on the upper surface of the insulating substrate 1 and forming the metal wiring 5a into a thin film wiring layer 5 having a predetermined pattern by photolithography or the like (FIG. 2 (e)). As shown in (1), an insulating substrate 1 as a product is completed.
【００３５】尚、この場合、薄膜配線層5 は薄膜形成技
術及びフォトリソグラフィー技術等を採用することによ
って形成されることから極めて微細なパターンとなすこ
とができ、その結果、半導体素子の電極数が極めて多い
ものになったとしても該半導体素子の各電極をメタライ
ズ配線層8 に確実に電気的接続することができる。In this case, since the thin film wiring layer 5 is formed by employing a thin film forming technique and a photolithography technique, it can be formed into an extremely fine pattern. As a result, the number of electrodes of the semiconductor element is reduced. Even if the number becomes extremely large, each electrode of the semiconductor element can be reliably electrically connected to the metallized wiring layer 8.
【００３６】尚、本発明は上述の実施例に限定されるも
のではなく本発明の要旨を逸脱しない範囲であれば種々
の変更は可能である。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
【００３７】[0037]
【発明の効果】本発明の半導体素子収納用パッケージの
製造方法によれば、絶縁基体に設けた外部リード端子が
ロウ付けされるメタライズ配線層の全てを薄膜配線層と
なる金属薄膜で共通に接続したことからメタライズ配線
層にわざわざ引き出しパターンを分岐させる必要は一切
ない。そのためメタライズ配線層に電気信号を伝達させ
たとしても該電気信号はメタライズ配線層に引き出しパ
ターンの分岐部がないことから引き出しパターンの分岐
部、或いは引き出しパターンの先端部において反射し、
ノイズを発生することは殆どなく、該ノイズが半導体素
子に伝達されて半導体素子に誤動作を生じさせることも
ない。According to the method of manufacturing a package for housing a semiconductor element of the present invention, all the metallized wiring layers to which external lead terminals provided on an insulating base are to be brazed are commonly connected by a metal thin film serving as a thin film wiring layer. As a result, there is no need to branch the extraction pattern into the metallized wiring layer. Therefore, even if the electric signal is transmitted to the metallized wiring layer, the electric signal is reflected at the branch part of the drawn pattern or at the leading end of the drawn pattern because there is no branch part of the drawn pattern in the metallized wiring layer,
Noise is hardly generated, and the noise is not transmitted to the semiconductor element to cause a malfunction in the semiconductor element.
【図１】本発明の製造方法によって製造された半導体素
子収納用パッケージの一実施例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device housing package manufactured by a manufacturing method of the present invention.
【図２】(a)(b)(c)(d)(e)は本発明の製造方法を説明す
るための各工程毎の断面図である。FIGS. 2 (a), (b), (c), (d), and (e) are cross-sectional views at respective steps for explaining a manufacturing method of the present invention.
【図３】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 3 is a cross-sectional view of a conventional semiconductor element storage package.
１・・・・絶縁基体 ２・・・・蓋体 ３・・・・容器 ４・・・・半導体素子 ５・・・・薄膜配線層 ５ａ・・・金属薄膜 ７・・・・メタライズ配線層 ８・・・・外部リード端子 ９・・・・メッキ金属層 Ａ・・・・半導体素子載置部 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Container 4 ... Semiconductor element 5 ... Thin film wiring layer 5a ... Metal thin film 7 ... Metallized wiring layer 8 ···· External lead terminals 9 ··· Plating metal layer A ··· Semiconductor element mounting part
Claims (1)
キ金属層で被覆された外部リード端子がロウ付けされた
絶縁基体と蓋体とから成り、内部に半導体素子を収容す
るための空所を有する半導体素子収納用パッケージであ
って、前記絶縁基体は下記(1) 乃至(5) の工程により形
成されていることを特徴とする半導体素子収納用パッケ
ージの製造方法。 (1) 絶縁基体に複数個のスルーホールを形成するととも
に該スルーホールを介して絶縁基体の上面から下面にか
けて複数個のメタライズ配線層を形成する工程と、 (2) 前記絶縁基体の下面に導出させたメタライズ配線層
の個々に外部リード端子をロウ付けする工程と、 (3) 前記絶縁基体の上面に金属薄膜を、メタライズ配線
層の全てが共通に電気的接続されるようにして被着させ
るとともに該金属薄膜の表面を樹脂膜で被覆する工程
と、 (4) 前記外部リード端子の表面にメッキ金属層を層着さ
せ、該メッキ金属層で外部リード端子の表面を被覆する
工程と、 (5) 前記絶縁基体上面の樹脂膜を除去するとともに金属
薄膜を所定パターンにエッチング加工し、薄膜配線層と
なす工程。An insulating base having a thin-film wiring layer attached to an upper surface thereof and an external lead terminal brazed to a lower surface covered with a plating metal layer, and a lid, for housing a semiconductor element therein; A method for manufacturing a semiconductor element storage package, comprising: a semiconductor element storage package having a void, wherein the insulating base is formed by the following steps (1) to (5). (1) forming a plurality of through holes in the insulating substrate and forming a plurality of metallized wiring layers from the upper surface to the lower surface of the insulating substrate through the through holes; (2) leading out to the lower surface of the insulating substrate And (3) depositing a metal thin film on the upper surface of the insulating base such that all of the metallized wiring layers are electrically connected in common. (4) a step of coating a surface of the external lead terminal with a plating metal layer on the surface of the external lead terminal, and covering the surface of the external lead terminal with the plating metal layer. 5) A step of removing the resin film on the upper surface of the insulating base and etching the metal thin film into a predetermined pattern to form a thin film wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3608592A JP2962921B2 (en) | 1992-02-24 | 1992-02-24 | Manufacturing method of semiconductor device storage package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3608592A JP2962921B2 (en) | 1992-02-24 | 1992-02-24 | Manufacturing method of semiconductor device storage package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05235231A JPH05235231A (en) | 1993-09-10 |
| JP2962921B2 true JP2962921B2 (en) | 1999-10-12 |
Family
ID=12459912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3608592A Expired - Fee Related JP2962921B2 (en) | 1992-02-24 | 1992-02-24 | Manufacturing method of semiconductor device storage package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962921B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196851A (en) * | 1989-01-25 | 1990-08-03 | Nippon Petrochem Co Ltd | Adhesive resin composition and production thereof, laminate using the same composition |
| JP3114926B2 (en) * | 1997-06-24 | 2000-12-04 | 日本特殊陶業株式会社 | Masking method for wiring board plating |
-
1992
- 1992-02-24 JP JP3608592A patent/JP2962921B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05235231A (en) | 1993-09-10 |
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