JPH0888449A - Ceramic interconnection board - Google Patents
Ceramic interconnection boardInfo
- Publication number
- JPH0888449A JPH0888449A JP6223044A JP22304494A JPH0888449A JP H0888449 A JPH0888449 A JP H0888449A JP 6223044 A JP6223044 A JP 6223044A JP 22304494 A JP22304494 A JP 22304494A JP H0888449 A JPH0888449 A JP H0888449A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- wiring layer
- metallized wiring
- resistor
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子が収容搭載
される半導体素子収納用パッケージや混成集積回路装置
等に用いられるセラミック配線基板に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic wiring board used for a semiconductor element housing package in which semiconductor elements are housed and mounted, a hybrid integrated circuit device or the like.
【０００２】[0002]
【従来技術】従来、セラミック配線基板、例えば半導体
素子を収容するための半導体素子収納用パッケージに使
用されるセラミック配線基板は一般に、アルミナセラミ
ックス等の電気絶縁材料から成り、その上面に半導体素
子を搭載するための凹部を有する絶縁基体と、前記絶縁
基体の凹部周辺から外周縁にかけて導出されたタングス
テン、モリブデン等の高融点金属から成るメタライズ配
線層とから構成されており、絶縁基体の凹部底面に半導
体素子をガラス、樹脂、ロウ材等の接着剤を介して搭載
固定するとともに半導体素子の各電極を凹部周辺に位置
するメタライズ配線層にボンディングワイヤを介して電
気的に接続し、しかる後、前記絶縁基体の上面に、金属
やセラミックス等から成る蓋体を絶縁基体の凹部を塞ぐ
ようにガラス、樹脂、ロウ材等から成る封止材を介して
接合させ、絶縁基体の凹部内に半導体素子を気密に収容
することによって製品としての半導体装置となる。2. Description of the Related Art Conventionally, a ceramic wiring board, for example, a ceramic wiring board used for a semiconductor element housing package for housing a semiconductor element is generally made of an electrically insulating material such as alumina ceramics, and the semiconductor element is mounted on the upper surface thereof. And a metallized wiring layer made of a refractory metal such as tungsten or molybdenum, which is led out from the periphery of the recess of the insulating base to the outer periphery, and a semiconductor is formed on the bottom of the recess of the insulating base. The element is mounted and fixed via an adhesive such as glass, resin, or a brazing material, and each electrode of the semiconductor element is electrically connected to a metallized wiring layer located around the recess via a bonding wire. A lid made of metal, ceramics, or the like is placed on the upper surface of the base body so as to cover the recess of the insulating base body with glass or resin. , It is bonded via a sealing material made of brazing material or the like, a semiconductor device as a product by housing airtightly semiconductor element in the recess of the insulating substrate.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この従
来のセラミック配線基板は絶縁基体に設けたメタライズ
配線層がタングステンやモリブデン等により形成されて
おり、内部に収容する半導体素子から見たメタライズ配
線層のインピーダンスが半導体素子の特性インピーダン
スに比べて低くなっていることからメタライズ配線層に
半導体素子の電極を接続させ、メタライズ配線層を介し
て半導体素子に電気信号の出し入れを行った場合、前記
半導体素子の特性インピーダンスと半導体素子側から見
たメタライズ配線層のインピーダンスとが不整合である
ことに起因してメタライズ配線層を伝わる電気信号に反
射によるノイズや減衰が発生し、半導体素子を正常に作
動させることができないという欠点を有していた。However, in this conventional ceramic wiring board, the metallized wiring layer provided on the insulating substrate is formed of tungsten, molybdenum, or the like, and the metallized wiring layer viewed from the semiconductor element housed inside is formed. Since the impedance is lower than the characteristic impedance of the semiconductor element, the electrodes of the semiconductor element are connected to the metallized wiring layer, and when an electric signal is taken in and out of the semiconductor element through the metallized wiring layer, Due to the mismatch between the characteristic impedance and the impedance of the metallized wiring layer viewed from the semiconductor element side, noise and attenuation due to reflection occur in the electric signal transmitted through the metallized wiring layer, and the semiconductor element operates normally. It had the drawback of not being able to.
【０００４】特に、上記欠点はコンピュータ等、情報処
理装置の高速情報処理化が進み、メタライズ配線層を介
して半導体素子に出し入れされる電気信号が高周波領域
のものになるとより顕著となった。In particular, the above-mentioned drawbacks become more noticeable when an information processing apparatus such as a computer is advanced in high-speed information processing and an electric signal which is put in and out of a semiconductor element through a metallized wiring layer is in a high frequency region.
【０００５】そこで上記欠点を解消するためにセラミッ
ク配線基板に抵抗体を被着形成し、該抵抗体をメタライ
ズ配線層に対し直列に接続させ終端抵抗とすることによ
って、半導体素子側から見たメタライズ配線層のインピ
ーダンスを半導体素子の特性インピーダンスに整合させ
ることが試みられている。Therefore, in order to solve the above-mentioned drawbacks, a resistor is adhered to the ceramic wiring substrate, and the resistor is connected in series to the metallized wiring layer to form a terminating resistor, whereby the metallization seen from the semiconductor element side is obtained. Attempts have been made to match the impedance of the wiring layer with the characteristic impedance of the semiconductor element.
【０００６】しかしながら、前記各メタライズ配線層に
終端抵抗としての抵抗体を直列に接続させたセラミック
配線基板は各抵抗体の抵抗値が隣接するメタライズ配線
層や抵抗体の影響を受けて大きく変化し、その結果、半
導体素子の特性インピーダンスと半導体素子側から見た
メタライズ配線層のインピーダンスとが依然として不整
合となり、メタライズ配線層を伝わる電気信号に反射に
よるノイズや減衰が発生して半導体素子を正常に作動さ
せることができないという欠点を有していた。However, in a ceramic wiring board in which a resistor serving as a terminating resistor is connected in series to each metallized wiring layer, the resistance value of each resistor greatly changes under the influence of the adjacent metallized wiring layer or resistor. As a result, the characteristic impedance of the semiconductor element and the impedance of the metallized wiring layer viewed from the semiconductor element side are still mismatched, and noise and attenuation due to reflection occur in the electric signal transmitted through the metallized wiring layer, and the semiconductor element is normally operated. It had the drawback that it could not be activated.
【０００７】[0007]
【発明の目的】本発明は、上記欠点に鑑み案出されたも
のであり、その目的は半導体素子に出し入れされる電気
信号にノイズや減衰が発生するのを有効に除去し、半導
体素子を常に安定に作動させることができるセラミック
配線基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to effectively eliminate the occurrence of noise and attenuation in electric signals which are taken in and out of a semiconductor element, and keep the semiconductor element always It is to provide a ceramic wiring board that can be stably operated.
【０００８】[0008]
【課題を解決するための手段】本発明は、絶縁基体にメ
タライズ配線層と、該メタライズ配線層に電気的に接続
される抵抗体とを被着形成させて成るセラミック配線基
板であって、前記抵抗体の周囲に前記メタライズ配線層
に電気的に接続されないダミーの抵抗体を配したことを
特徴とするものである。The present invention relates to a ceramic wiring board comprising a metallized wiring layer and a resistor electrically connected to the metallized wiring layer, which are adhered to an insulating substrate. A dummy resistor which is not electrically connected to the metallized wiring layer is arranged around the resistor.
【０００９】[0009]
【作用】本発明のセラミック配線基板によれば、メタラ
イズ配線層に接続させた抵抗体の周囲に、前記メタライ
ズ配線層に対し電気的に接続されないダミーの抵抗体を
配したことからメタライズ配線層に接続された抵抗体の
抵抗値はダミーの抵抗体によって隣接するメタライズ配
線層や抵抗体の影響を受け変化することは殆どなく、そ
の結果、半導体素子側から見たメタライズ配線層のイン
ピーダンスと半導体素子の特性インピーダンスとは常に
整合し、メタライズ配線層を介して半導体素子に出し入
れされる電気信号にノイズや減衰が発生するのを有効に
防止することが可能となって半導体素子を正常に作動さ
せることができる。According to the ceramic wiring board of the present invention, since the dummy resistor which is not electrically connected to the metallized wiring layer is arranged around the resistor connected to the metallized wiring layer, the metallized wiring layer is formed. The resistance value of the connected resistor hardly changes under the influence of the adjacent metallized wiring layer or resistor due to the dummy resistor, and as a result, the impedance of the metallized wiring layer viewed from the semiconductor element side and the semiconductor element The characteristic impedance of the semiconductor element is always matched, and it is possible to effectively prevent noise and attenuation from occurring in the electric signal that is put in and out of the semiconductor element through the metallized wiring layer, and the semiconductor element can be operated normally. You can
【００１０】[0010]
【実施例】次に本発明を実施例に基づき詳細に説明す
る。図１及び図２は、本発明のセラミック配線基板を半
導体素子を収容する半導体素子収納用パッケージに適用
した場合の一実施例を示し、１は絶縁基体、２はメタラ
イズ配線層である。このメタライズ配線層２を絶縁基体
１に取着させたものがセラミック配線基板Ａとなる。EXAMPLES Next, the present invention will be described in detail based on examples. 1 and 2 show an embodiment in which the ceramic wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element, wherein 1 is an insulating substrate and 2 is a metallized wiring layer. The ceramic wiring board A is obtained by attaching the metallized wiring layer 2 to the insulating substrate 1.
【００１１】前記絶縁基体１は、その上面中央部に半導
体素子３を収容するための空所を形成する凹部１ａが設
けてあり、該凹部１ａ底面には半導体素子３がガラス、
樹脂、ロウ材等の接着剤を介して接着固定される。The insulating substrate 1 is provided with a recess 1a which forms a space for accommodating the semiconductor element 3 in the center of the upper surface thereof, and the semiconductor element 3 is made of glass on the bottom surface of the recess 1a.
It is adhesively fixed through an adhesive such as resin or brazing material.
【００１２】前記絶縁基体１は、酸化アルミニウム質焼
結体、ムライト質焼結体、窒化アルミニウム質焼結体、
炭化珪素質焼結体、ガラスセラミックス焼結体等の電気
絶縁材料から成り、例えば酸化アルミニウム質焼結体か
ら成る場合は、酸化アルミニウム、酸化珪素、酸化マグ
ネシウム、酸化カルシウム等の原料粉末に適当な有機バ
インダー、有機溶剤、可塑剤、分散剤等を添加混合して
泥漿状となすとともに該泥漿物を従来周知のドクターブ
レード法やカレンダーロール法等のシート成形法を採用
してシート状となすことによりセラミックグリーンシー
トを得、しかる後、前記セラミックグリーンシートに適
当な打ち抜き加工を施すとともにこれを複数枚積層し、
約１６００℃の温度で焼成することによって製作され
る。The insulating substrate 1 is made of an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body,
When it is made of an electrically insulating material such as a silicon carbide sintered body or a glass ceramics sintered body, and is made of, for example, an aluminum oxide sintered body, it is suitable as a raw material powder of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide or the like. An organic binder, an organic solvent, a plasticizer, a dispersant, etc. are added and mixed to form a slurry, and the slurry is formed into a sheet by using a sheet forming method such as a conventionally known doctor blade method or calender roll method. To obtain a ceramic green sheet by, after that, subjecting the ceramic green sheet to an appropriate punching process and laminating a plurality of these,
It is manufactured by firing at a temperature of about 1600 ° C.
【００１３】また前記絶縁基体１には凹部１ａ周辺から
外周縁にかけて導出する複数個のメタライズ配線層２が
形成されており、該メタライズ配線層２の凹部１ａ周辺
部位には半導体素子３の各電極がボンディングワイヤ４
を介して電気的に接続され、また絶縁基体１の外周縁に
導出された部位には外部電気回路と接続される外部リー
ド端子５が銀ロウ等のロウ材を介し取着されている。Further, a plurality of metallized wiring layers 2 extending from the periphery of the recess 1a to the outer peripheral edge thereof are formed on the insulating base 1, and the electrodes of the semiconductor element 3 are formed on the metallized wiring layer 2 in the periphery of the recess 1a. Bonding wire 4
External lead terminals 5 electrically connected to each other via an external electric circuit are attached to a portion led out to the outer peripheral edge of the insulating substrate 1 via a brazing material such as silver solder.
【００１４】前記メタライズ配線層２は半導体素子３の
各電極を外部リード端子５に電気的に接続させる作用を
為し、タングステン、モリブデン、マンガン等の高融点
金属粉末から成り、該高融点金属粉末に適当な有機溶
剤、溶媒を添加混合して得た金属ペーストを従来周知の
スクリーン印刷法等の厚膜手法を採用し、絶縁基体１と
成るセラミックグリーンシートに予め印刷塗布しておく
ことによって絶縁基体１の凹部１ａ周辺部から外周縁に
かけて導出するよう被着形成される。The metallized wiring layer 2 serves to electrically connect the electrodes of the semiconductor element 3 to the external lead terminals 5, and is made of a refractory metal powder such as tungsten, molybdenum, or manganese. Insulation is performed by applying a suitable organic solvent, a metal paste obtained by adding and mixing the solvent to a ceramic green sheet to be the insulating substrate 1 in advance by applying a thick film method such as a well-known screen printing method. It is formed so as to be led out from the peripheral portion of the concave portion 1a of the base body 1 to the outer peripheral edge.
【００１５】尚、前記メタライズ配線層２はその露出す
る表面にニッケル、金等の耐蝕性に優れ、且つロウ材と
の濡れ性が良い金属を１．０乃至２０．０μｍの厚みに
メッキ法により層着させておくと、メタライズ配線層２
の酸化腐食を有効に防止することができるとともにメタ
ライズ配線層２への外部リード端子５のロウ付けを強固
となすことができる。従って、前記メタライズ配線層２
にはその露出する表面にニッケル、金等を１．０乃至２
０．０μｍの厚みに層着させておくことが好ましい。The exposed surface of the metallized wiring layer 2 is plated with a metal such as nickel or gold having a good corrosion resistance and a good wettability with a brazing material to a thickness of 1.0 to 20.0 μm. If it is layered, the metallized wiring layer 2
It is possible to effectively prevent the above-mentioned oxidative corrosion and to firmly braze the external lead terminal 5 to the metallized wiring layer 2. Therefore, the metallized wiring layer 2
The exposed surface should be coated with nickel, gold, etc. 1.0 to 2
It is preferable that the layers are layered to a thickness of 0.0 μm.
【００１６】また前記メタライズ配線層２はその凹部１
ａ周辺部に図２に示す如く、抵抗体６が直列に接続され
ており、該抵抗体６は例えば、タングステンーレニウム
粉末から成り、上述のメタライズ配線層２と同様の方
法、具体的にはタングステン粉末及びレニウム粉末に適
当な有機溶剤、溶媒を添加混合して得た抵抗体ペースト
を絶縁基体１となるセラミックグリーンシートに予め従
来周知のスクリーン印刷法等の厚膜手法を採用し、各メ
タライズ配線層２間で、両端がメタライズ配線層２に接
触するように印刷塗布しておくことによって絶縁基体１
の凹部１ａ周辺で、メタライズ配線層２に直列に電気的
接続された状態で被着形成される。The metallized wiring layer 2 has a recess 1
As shown in FIG. 2, a resistor 6 is connected in series to the periphery of a, and the resistor 6 is made of, for example, tungsten-rhenium powder, and the same method as that for the metallized wiring layer 2 described above, specifically, A resistor paste obtained by adding and mixing an appropriate organic solvent and a solvent to tungsten powder and rhenium powder is applied to a ceramic green sheet serving as the insulating substrate 1 in advance by a well-known thick film method such as a screen printing method to perform metallization. The insulating substrate 1 is formed by printing and coating between the wiring layers 2 so that both ends contact the metallized wiring layer 2.
Around the concave portion 1a, the metallized wiring layer 2 is deposited and formed so as to be electrically connected in series.
【００１７】前記抵抗体６はメタライズ配線層２の半導
体素子３側から見たインピーダンスを半導体素子３の特
性インピーダンスに整合させる作用を為し、抵抗体６に
よってメタライズ配線層２の半導体素子３側から見たイ
ンピーダンスと半導体素子３の特性インピーダンスとの
整合が完全となることからメタライズ配線層２を介して
半導体素子３に電気信号を出し入れしたとしても電気信
号にノイズや減衰等が発生することは殆どなく、これに
よって半導体素子３を正常、且つ安定に作動させること
が可能となる。The resistor 6 has a function of matching the impedance of the metallized wiring layer 2 viewed from the semiconductor element 3 side with the characteristic impedance of the semiconductor element 3, and the resistor 6 acts from the semiconductor element 3 side of the metallized wiring layer 2. Since the matching between the observed impedance and the characteristic impedance of the semiconductor element 3 is perfect, even if an electric signal is taken in and out of the semiconductor element 3 via the metallized wiring layer 2, noise or attenuation is hardly generated in the electric signal. This makes it possible to operate the semiconductor element 3 normally and stably.
【００１８】また前記抵抗体６はその周囲にメタライズ
配線層２と電気的接続されていないダミーの抵抗体７が
配されている。このダミーの抵抗体７はメタライズ配線
層２に直列接続されている抵抗体６の抵抗値が隣接する
メタライズ配線層２や抵抗体６の影響を受け大きく変化
するのを有効に防止する作用を為し、該ダミーの抵抗体
７によってメタライズ配線層２に直列接続されている抵
抗体６の抵抗値は常に一定となり、その結果、半導体素
子３側から見たメタライズ配線層２のインピーダンスは
半導体素子３の特性インピーダンスに常に整合し、メタ
ライズ配線層２を介して半導体素子３に出し入れされる
電気信号にノイズや減衰が発生するのを皆無となすこと
ができる。A dummy resistor 7 which is not electrically connected to the metallized wiring layer 2 is arranged around the resistor 6. The dummy resistor 7 effectively prevents the resistance value of the resistor 6 connected in series with the metallized wiring layer 2 from being greatly changed by the influence of the adjacent metallized wiring layer 2 or the resistor 6. However, the resistance value of the resistor 6 connected in series to the metallized wiring layer 2 by the dummy resistor 7 is always constant, and as a result, the impedance of the metallized wiring layer 2 viewed from the semiconductor element 3 side is the semiconductor element 3 It is possible to always match with the characteristic impedance of No. 1 and to prevent noise and attenuation from occurring in the electric signal that is put in and out of the semiconductor element 3 through the metallized wiring layer 2.
【００１９】前記ダミーの抵抗体７としては例えば、抵
抗体６と同じ材料が使用され、絶縁基体１のメタライズ
配線層２間に抵抗体ペーストを用いて抵抗体６を形成す
る際、該抵抗体ペーストを隣接する抵抗体６間の位置に
もスクリーン印刷法により所定形状に印刷塗布しておく
ことによって絶縁基体１上で隣接する抵抗体６間に被着
形成される。As the dummy resistor 7, for example, the same material as that of the resistor 6 is used, and when the resistor 6 is formed by using the resistor paste between the metallized wiring layers 2 of the insulating substrate 1, the resistor 6 is formed. The paste is also applied between the adjacent resistors 6 on the insulating substrate 1 by printing and applying the paste in a predetermined shape between the adjacent resistors 6 by the screen printing method.
【００２０】更に前記抵抗体６が接続されたメタライズ
配線層２はその一端に外部リード端子５が銀ロウ等のロ
ウ材を介してロウ付けされており、該外部リード端子５
は絶縁基体１の凹部１ａ内に収容する半導体素子３を外
部電気回路に接続する作用を為し、外部リード端子５を
外部電気回路に接続させることによって半導体素子３の
各電極はボンディングワイヤ４、抵抗体６、メタライズ
配線層２及び外部リード端子５を介して外部電気回路と
電気的に接続されることとなる。Further, an external lead terminal 5 is brazed to one end of the metallized wiring layer 2 to which the resistor 6 is connected via a brazing material such as silver brazing, and the external lead terminal 5
Has a function of connecting the semiconductor element 3 housed in the concave portion 1a of the insulating substrate 1 to an external electric circuit. By connecting the external lead terminal 5 to the external electric circuit, each electrode of the semiconductor element 3 has a bonding wire 4, It is electrically connected to an external electric circuit through the resistor 6, the metallized wiring layer 2 and the external lead terminal 5.
【００２１】前記外部リード端子５は鉄ーニッケルーコ
バルト合金や鉄ーニッケル合金等の金属材料から成り、
鉄ーニッケルーコバルト合金等のインゴット（塊）を圧
延加工法や打ち抜き加工法等、従来周知の金属加工法を
採用することによって所定の板状に形成される。The external lead terminal 5 is made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy,
An ingot (lump) of iron-nickel-cobalt alloy or the like is formed into a predetermined plate shape by adopting a conventionally known metal processing method such as a rolling processing method or a punching processing method.
【００２２】尚、前記外部リード端子５はその外表面に
良導電性で、且つ耐蝕性に優れたニッケル、金等の金属
をメッキ法により１．０乃至２０．０μｍの厚みに層着
させておくと、外部リード端子５の酸化腐食を有効に防
止することができるとともに外部リード端子５と外部電
気回路との電気的接続を良好なものとなすことができ
る。したがって、前記外部リード端子５はその外表面に
ニッケル、金等を１．０乃至２０．０μｍの厚みに層着
させておくことが好ましい。The external lead terminal 5 is formed by depositing a metal such as nickel or gold, which has good conductivity and corrosion resistance, on the outer surface of the external lead terminal 5 by plating to a thickness of 1.0 to 20.0 μm. By so doing, it is possible to effectively prevent oxidative corrosion of the external lead terminals 5 and to make good electrical connection between the external lead terminals 5 and the external electric circuit. Therefore, it is preferable that nickel, gold or the like is laminated on the outer surface of the external lead terminal 5 to a thickness of 1.0 to 20.0 μm.
【００２３】かくして上述の半導体素子収納用パッケー
ジによれば、絶縁基体１の凹部１ａ底面に半導体素子３
をガラス、樹脂、ロウ材等の接着剤を介して接着固定す
るとともに該半導体素子３の各電極をボンディングワイ
ヤ４を介してメタライズ配線層２に電気的に接続し、し
かる後、絶縁基体１の上面に蓋体８を絶縁基体１の凹部
１ａを塞ぐようにガラス、樹脂、ロウ材等の封止材を介
して接合させ、絶縁基体１の凹部１ａ内に半導体素子３
を気密に収容することによって製品としての半導体装置
となる。Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is formed on the bottom surface of the recess 1a of the insulating substrate 1.
Are bonded and fixed through an adhesive such as glass, resin, or a brazing material, and each electrode of the semiconductor element 3 is electrically connected to the metallized wiring layer 2 through a bonding wire 4, and then the insulating substrate 1 The lid 8 is bonded to the upper surface via a sealing material such as glass, resin, or brazing material so as to close the recess 1a of the insulating base 1, and the semiconductor element 3 is placed in the recess 1a of the insulating base 1.
Is hermetically housed to form a semiconductor device as a product.
【００２４】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば、上述の実施例では本発
明のセラミック配線基板を半導体素子を搭載収容する半
導体素子収納用パッケージに適用した場合の例で説明し
たが、これを混成集積回路装置等に使用される配線基板
にも適用し得る。The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-mentioned embodiments, the ceramic of the present invention is used. An example of the case where the wiring board is applied to a semiconductor element housing package in which a semiconductor element is mounted and housed has been described, but this may also be applied to a wiring board used for a hybrid integrated circuit device or the like.
【００２５】[0025]
【発明の効果】本発明のセラミック配線基板によれば、
メタライズ配線層に接続させた抵抗体の周囲に、前記メ
タライズ配線層に対し電気的に接続されないダミーの抵
抗体を配したことからメタライズ配線層に接続された抵
抗体の抵抗値はダミーの抵抗体によって隣接するメタラ
イズ配線層や抵抗体の影響を受け変化することは殆どな
く、その結果、半導体素子側から見たメタライズ配線層
のインピーダンスと半導体素子の特性インピーダンスと
は常に整合し、メタライズ配線層を介して半導体素子に
出し入れされる電気信号にノイズや減衰が発生するのを
有効に防止することが可能となって半導体素子を正常に
作動させることができる。According to the ceramic wiring board of the present invention,
Since a dummy resistor which is not electrically connected to the metallized wiring layer is arranged around the resistor connected to the metallized wiring layer, the resistance value of the resistor connected to the metallized wiring layer is a dummy resistor. It hardly changes under the influence of the adjacent metallized wiring layer or the resistor, and as a result, the impedance of the metallized wiring layer viewed from the semiconductor element side and the characteristic impedance of the semiconductor element always match and the metallized wiring layer is It is possible to effectively prevent noise and attenuation from occurring in the electric signal that is put in and out of the semiconductor element via the semiconductor element, and the semiconductor element can be operated normally.
【図１】本発明のセラミック配線基板を半導体素子収納
用パッケージに適用した場合の一実施例を示す断面図で
ある。FIG. 1 is a cross-sectional view showing an embodiment in which a ceramic wiring board of the present invention is applied to a semiconductor element housing package.
【図２】図１に示す半導体素子収納用パッケージの絶縁
基体の要部拡大平面図である。FIG. 2 is an enlarged plan view of an essential part of an insulating base of the semiconductor element housing package shown in FIG.
１・・・絶縁基体 ２・・・メタライズ配線層 ３・・・半導体素子 ６・・・抵抗体 ７・・・ダミーの抵抗体 Ａ・・・セラミック配線基板 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Metallized wiring layer 3 ... Semiconductor element 6 ... Resistor 7 ... Dummy resistor A ... Ceramic wiring board
Claims (1)
イズ配線層に電気的に接続される抵抗体とを被着形成さ
せて成るセラミック配線基板であって、前記抵抗体の周
囲に前記メタライズ配線層に電気的に接続されないダミ
ーの抵抗体を配したことを特徴とするセラミック配線基
板。1. A ceramic wiring substrate comprising a metallized wiring layer and a resistor electrically connected to the metallized wiring layer, which are adhered to an insulating substrate, wherein the metallized wiring is provided around the resistor. A ceramic wiring board having a dummy resistor which is not electrically connected to the layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6223044A JPH0888449A (en) | 1994-09-19 | 1994-09-19 | Ceramic interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6223044A JPH0888449A (en) | 1994-09-19 | 1994-09-19 | Ceramic interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0888449A true JPH0888449A (en) | 1996-04-02 |
Family
ID=16791965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6223044A Pending JPH0888449A (en) | 1994-09-19 | 1994-09-19 | Ceramic interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0888449A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
| KR101023072B1 (en) * | 2008-09-05 | 2011-03-24 | 주식회사 동부하이텍 | resist array of mismatch structure |
-
1994
- 1994-09-19 JP JP6223044A patent/JPH0888449A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187193A (en) * | 2008-03-21 | 2008-08-14 | Kyocera Corp | Wiring board |
| JP4741624B2 (en) * | 2008-03-21 | 2011-08-03 | 京セラ株式会社 | Wiring board |
| KR101023072B1 (en) * | 2008-09-05 | 2011-03-24 | 주식회사 동부하이텍 | resist array of mismatch structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000340687A (en) | Package for storing semiconductor element | |
| JPH0888449A (en) | Ceramic interconnection board | |
| JP2851732B2 (en) | Electronic component storage package | |
| JP2713841B2 (en) | Package for storing semiconductor elements | |
| JP2735759B2 (en) | Package for storing semiconductor elements | |
| JP2735708B2 (en) | Ceramic wiring board | |
| JP2746813B2 (en) | Package for storing semiconductor elements | |
| JPH07122838A (en) | Manufacture of substrate for mounting electronic device | |
| JP2001035959A (en) | Package for housing semiconductor element | |
| JP3441199B2 (en) | Package for storing semiconductor elements | |
| JP2728593B2 (en) | Package for storing semiconductor elements | |
| JPH05275608A (en) | Semiconductor element housing package | |
| JP2000260896A (en) | Package for housing semiconductor element | |
| JPH05145009A (en) | Package for accommodating semiconductor element | |
| JP4637342B2 (en) | Package for pressure detection device | |
| JPH09266124A (en) | Mounting structure for capacitor elements | |
| JP3176268B2 (en) | Package for storing semiconductor elements | |
| JP2784129B2 (en) | Package for storing semiconductor elements | |
| JPH05235231A (en) | Manufacture of package for containing semiconductor chip | |
| JPH0637205A (en) | Ceramic wiring substrate | |
| JPH0521495A (en) | Semiconductor device | |
| JPH06283624A (en) | Package for housing semiconductor device | |
| JP2003163560A (en) | Container for housing piezoelectric vibrator | |
| JP2003068932A (en) | Wiring board | |
| JP2002009194A (en) | Semiconductor element mounting board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040527 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040622 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20041019 |