JPH04217389A - Thick film multilayer circuit substrate and manufacture thereof - Google Patents
Thick film multilayer circuit substrate and manufacture thereofInfo
- Publication number
- JPH04217389A JPH04217389A JP41142390A JP41142390A JPH04217389A JP H04217389 A JPH04217389 A JP H04217389A JP 41142390 A JP41142390 A JP 41142390A JP 41142390 A JP41142390 A JP 41142390A JP H04217389 A JPH04217389 A JP H04217389A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- holes
- thick film
- film multilayer
- conductor patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 title abstract 5
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000011810 insulating material Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、スルーホールが形成
された回路基板の多層化に用いられる厚膜多層回路基板
及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film multilayer circuit board used for multilayering a circuit board having through holes formed therein, and a method for manufacturing the same.
【０００２】0002
【従来の技術】アルミナ等の絶縁材料で形成された回路
基板では、その表裏面に種々の回路パターンが形成され
、複数の電子部品が実装されている。このような回路基
板では、表裏面間の回路パターンの電気的な接続を図る
技術としてスルーホールを通した導体接続が行われてい
る。2. Description of the Related Art A circuit board made of an insulating material such as alumina has various circuit patterns formed on its front and back surfaces, and a plurality of electronic components are mounted thereon. In such circuit boards, conductor connection through through holes is performed as a technique for electrically connecting circuit patterns between the front and back surfaces.
【０００３】また、独立した回路パターンが形成された
回路基板を積層した多層回路基板も実用化されている。
このような多層回路基板では、複雑な回路のコンパクト
化とともに、電子部品の高密度実装が可能になり、複雑
な機能回路の実現に向け、大きな期待が寄せられている
。[0003] Furthermore, multilayer circuit boards in which circuit boards on which independent circuit patterns are formed are laminated have also been put into practical use. Such multilayer circuit boards make it possible to make complex circuits more compact and to mount electronic components at high density, and there are great expectations for the realization of complex functional circuits.
【０００４】0004
【発明が解決しようとする課題】ところで、スルーホー
ルが形成された回路基板を積層した場合、回路基板に形
成されているスルーホールが、積層された絶縁層や導体
パターンに凹凸を生じさせ、多層化を妨げる。また、絶
縁層で閉じ込められたスルーホール内に空気が残留した
場合、その空気の膨張、収縮が導体パターンとの剥離の
原因になる等、回路基板の信頼性を低下させる原因にな
る。[Problems to be Solved by the Invention] By the way, when circuit boards with through holes formed in them are laminated, the through holes formed in the circuit boards cause unevenness in the laminated insulating layers and conductor patterns. prevent the development of Furthermore, if air remains in the through-holes confined by the insulating layer, the expansion and contraction of the air may cause separation from the conductor pattern, reducing the reliability of the circuit board.
【０００５】そこで、この発明は、スルーホールが形成
された回路基板の多層化における凹凸の発生を防止する
とともに、スルーホール内の空気の残留を阻止した厚膜
多層回路基板及びその製造方法の提供を目的とする。SUMMARY OF THE INVENTION Accordingly, the present invention provides a thick film multilayer circuit board and a method for manufacturing the same, which prevents the occurrence of unevenness in multilayering of a circuit board in which through holes are formed, and also prevents air from remaining in the through holes. With the goal.
【０００６】[0006]
【課題を解決するための手段】即ち、この発明の厚膜多
層回路基板は、表裏面に形成された第１の導体パターン
（６ａ、６ｂ、６ｃ、６ｄ）がスルーホール（４ａ、４
ｂ）を介して接続された回路基板（２）と、この回路基
板の前記スルーホールに充填された絶縁物（レジスト８
）と、前記導体パターンを覆って形成された絶縁層（レ
ジスト１２ａ、１２ｂ）と、この絶縁層上に形成された
第２の導体パターン（１４ａ、１４ｂ、１４ｃ、１４ｄ
）とを備えたことを特徴とする。[Means for Solving the Problems] That is, in the thick film multilayer circuit board of the present invention, the first conductor patterns (6a, 6b, 6c, 6d) formed on the front and back surfaces are the through holes (4a, 4).
b) and the insulator (resist 8) filled in the through hole of this circuit board (2) connected via
), an insulating layer (resist 12a, 12b) formed covering the conductive pattern, and a second conductive pattern (14a, 14b, 14c, 14d) formed on this insulating layer.
).
【０００７】また、この発明の厚膜多層回路基板の製造
方法は、表裏面に形成された第１の導体パターン（６ａ
、６ｂ、６ｃ、６ｄ）がスルーホール（４ａ、４ｂ）を
介して接続された回路基板（２）の前記スルーホールに
絶縁物（レジスト８）を充填した後、前記回路基板の表
面を覆う絶縁層（レジスト１２ａ、１２ｂ）を形成し、
この絶縁層の上に第２の導体パターン（１４ａ、１４ｂ
、１４ｃ、１４ｄ）を形成することを特徴とする。The method for manufacturing a thick film multilayer circuit board of the present invention also provides a first conductor pattern (6a) formed on the front and back surfaces.
, 6b, 6c, 6d) are connected through the through-holes (4a, 4b) through the through-holes of the circuit board (2) are filled with an insulating material (resist 8), and then the insulating material covering the surface of the circuit board is filled. forming a layer (resist 12a, 12b);
A second conductor pattern (14a, 14b) is formed on this insulating layer.
, 14c, 14d).
【０００８】[0008]
【作用】また、この発明の厚膜多層回路基板では、スル
ーホールに絶縁物が埋め込まれ、そのスルーホールによ
る凹部の発生がなく、回路基板表面が平坦化するため、
導体パターンと絶縁層との多層化が可能であり、しかも
、スルーホールを通して回路基板の表裏面側の回路パタ
ーンを導通させることができ、両面多層化が実現される
。[Function] In addition, in the thick film multilayer circuit board of the present invention, the through holes are filled with an insulator, so that no recesses are formed due to the through holes, and the surface of the circuit board is flattened.
Multi-layering of conductor patterns and insulating layers is possible, and circuit patterns on the front and back sides of the circuit board can be electrically connected through through holes, realizing multi-layering on both sides.
【０００９】また、この発明の厚膜多層回路基板の製造
方法では回路基板に形成されたスルーホールに絶縁物が
充填され、その絶縁物によってスルーホールが隠蔽され
る。その上に絶縁層が形成され、この絶縁層の上に第２
の導体パターンが積層されるので、その平坦化が図られ
るとともに、スルーホール内の空気は絶縁物によって排
除され、平坦な厚膜多層回路基板が得られる。Further, in the method of manufacturing a thick film multilayer circuit board of the present invention, the through holes formed in the circuit board are filled with an insulating material, and the through holes are hidden by the insulating material. An insulating layer is formed on the insulating layer, and a second insulating layer is formed on the insulating layer.
Since the conductor patterns are stacked, the conductor patterns are flattened, and the air in the through holes is removed by the insulator, resulting in a flat thick film multilayer circuit board.
【００１０】0010
【実施例】図１はこの発明の厚膜多層回路基板の一実施
例を示し、図２及び図３はこの発明の厚膜多層回路基板
の製造方法の一実施例を示す。この厚膜多層回路基板に
は、図２の（Ａ）に示すように、アルミナやセラミック
等の絶縁材料で形成された回路基板２が用いられ、この
回路基板２にはその表裏面側に実装すべき回路間を導通
させるためのスルーホール４ａ、４ｂが形成されている
。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the thick film multilayer circuit board of the present invention, and FIGS. 2 and 3 show an embodiment of the method of manufacturing the thick film multilayer circuit board of the present invention. As shown in FIG. 2(A), this thick film multilayer circuit board uses a circuit board 2 made of an insulating material such as alumina or ceramic. Through holes 4a and 4b are formed to provide electrical continuity between the circuits to be connected.
【００１１】この回路基板２の表裏面には、図２の（Ｂ
）及び図４に示すように、導体ペーストの印刷等により
第１の導体パターン６ａ、６ｂ、６ｃ、６ｄが形成され
、各導体パターン６ａ〜６ｄはスルーホール４ａ、４ｂ
の内壁部を通して接続されている。この実施例の場合で
は、各スルーホール４ａ、４ｂを以て２回路間の電気的
な接続が行われている。The front and back surfaces of this circuit board 2 are as shown in FIG.
) and as shown in FIG. 4, first conductor patterns 6a, 6b, 6c, and 6d are formed by printing conductor paste, etc., and each conductor pattern 6a to 6d has a through hole 4a, 4b.
connected through the inner wall of the In the case of this embodiment, electrical connection between two circuits is made using each through hole 4a, 4b.
【００１２】そして、各スルーホール４ａ、４ｂには、
図２の（Ｃ）に示すように、絶縁物としてレジスト８が
印刷やディスペンサによって充填され、このレジスト８
で各スルーホール４ａ、４ｂが埋め尽くされて導体パタ
ーン６ａ〜６ｄと同一平面を成している。[0012] In each through hole 4a, 4b,
As shown in FIG. 2C, a resist 8 is filled as an insulating material by printing or using a dispenser.
The through holes 4a and 4b are filled with the conductor patterns 6a to 6d so that they are flush with each other.
【００１３】また、この各スルーホール４ａ、４ｂにレ
ジスト８を充填した後、回路基板２の表裏面側の導体パ
ターン６ａ〜６ｄから露出する部分には、図２の（Ｄ）
に示すように、レジスト１０ａ、１０ｂが印刷によって
設置され、このレジスト１０ａ、１０ｂは導体パターン
６ａ〜６ｄと同様の厚さに設定されている。したがって
、各スルーホール４ａ、４ｂがレジスト８で充填されて
いるとともに、導体パターン６ａ〜６ｄ以外の部分がレ
ジスト１０ａ、１０ｂで覆われているため、回路基板２
の表裏面は多層化に理想的な平坦面を成している。After filling each of the through holes 4a and 4b with the resist 8, the portions exposed from the conductor patterns 6a to 6d on the front and back sides of the circuit board 2 are filled with the resist 8 shown in FIG. 2(D).
As shown in FIG. 1, resists 10a and 10b are installed by printing, and the resists 10a and 10b are set to have the same thickness as the conductor patterns 6a to 6d. Therefore, each through hole 4a, 4b is filled with resist 8, and the parts other than the conductive patterns 6a to 6d are covered with resist 10a, 10b, so that the circuit board 2
The front and back surfaces form flat surfaces that are ideal for multilayering.
【００１４】この回路基板２の表裏面には、図３の（Ｅ
）に示すように、絶縁層としてのレジスト１２ａ、１２
ｂが一様に形成され、各導体パターン６ａ〜６ｄの絶縁
が図られる。The front and back surfaces of this circuit board 2 are shown in (E) in FIG.
), resists 12a, 12 as insulating layers
b are formed uniformly, and insulation of each conductor pattern 6a to 6d is achieved.
【００１５】このレジスト１２ａ、１２ｂの表面には、
図３の（Ｆ）に示すように、特定の回路を形成するため
の第２の導体パターン１４ａ、１４ｂ、１４ｃ、１４ｄ
が選択的に形成され、各導体パターン１４ａ〜１４ｄの
間隔内には、図３の（Ｇ）に示すように、導体パターン
１４ａ〜１４ｄと同一の厚さで絶縁層としてのレジスト
１６ａ、１６ｂが形成され、導体パターン１４ａ〜１４
ｄとレジスト１２ａ、１２ｂとの凹凸が補償される結果
、回路基板２の平坦化が図られる。図示しないが、導体
パターン１４ａ〜１４ｄと回路基板２に直に形成されて
いる導体パターン６ａ〜６ｄは必要に応じて電気的に接
続され、その接続はレジスト１２ａ、１２ｂを貫通する
導体パターンによって行われる。[0015] On the surfaces of these resists 12a and 12b,
As shown in FIG. 3(F), second conductor patterns 14a, 14b, 14c, 14d for forming a specific circuit
are selectively formed, and as shown in FIG. 3(G), resists 16a and 16b as insulating layers are formed with the same thickness as the conductor patterns 14a to 14d, as shown in FIG. 3(G). formed, conductor patterns 14a to 14
As a result of compensating for the unevenness between d and the resists 12a and 12b, the circuit board 2 can be planarized. Although not shown, the conductor patterns 14a to 14d and the conductor patterns 6a to 6d formed directly on the circuit board 2 are electrically connected as necessary, and the connection is made by a conductor pattern penetrating through the resists 12a and 12b. be exposed.
【００１６】このように多層化された回路基板２の表面
には、図１に示すように、絶縁層としてのレジスト１８
ａ、１８ｂが印刷によって形成され、回路基板２の外表
面の電気的な絶縁が図られている。As shown in FIG. 1, a resist 18 is formed on the surface of the multilayered circuit board 2 as an insulating layer.
a and 18b are formed by printing, and the outer surface of the circuit board 2 is electrically insulated.
【００１７】以上のように、スルーホール４ａ、４ｂの
部分に絶縁物が充填されて回路基板２の平坦化が図られ
ているとともに、スルーホール４ａ、４ｂ内の空気が絶
縁物によって排除されてレジスト１２ａ、１２ｂ及び導
体パターン１４ａ〜１４ｄ等が積層され、回路が多層化
されている。As described above, the through holes 4a and 4b are filled with an insulator to flatten the circuit board 2, and the air inside the through holes 4a and 4b is removed by the insulator. Resist 12a, 12b, conductor patterns 14a to 14d, etc. are laminated to form a multilayered circuit.
【００１８】また、スルーホール４ａ、４ｂによる凹凸
がレジスト８によって補償され、回路基板２の平坦化が
図られるので、各導体パターン１４ａ〜１４ｄが平板状
となり、パターン印刷の精度が高められ、信頼性の高い
回路パターンが得られるものである。Moreover, the unevenness caused by the through holes 4a and 4b is compensated by the resist 8, and the circuit board 2 is flattened, so that each of the conductor patterns 14a to 14d has a flat plate shape, and the precision of pattern printing is improved, making it reliable. A circuit pattern with high quality can be obtained.
【００１９】なお、実施例では、回路基板の表裏面側に
各２層、即ち、４層の回路パターンが形成された場合に
ついて説明したが、回路基板が平坦化されるので５層以
上の多層化も可能であり、この発明の厚膜多層回路基板
は、実施例の４層のものに限定されるものではない。In the embodiment, a case was explained in which two layers each, that is, four layers of circuit patterns were formed on the front and back sides of the circuit board, but since the circuit board is flattened, a multilayer pattern of five or more layers is explained. The thick film multilayer circuit board of the present invention is not limited to the four-layer circuit board of the embodiment.
【００２０】[0020]
【発明の効果】この発明の厚膜多層回路基板によれば、
スルーホールに絶縁物を充填して回路基板が平坦化され
るため、スルーホールによって部分的に回路基板の厚さ
が変化することがなく、平坦化によって積層段数を増加
することができ、しかも、多層化とともにスルーホール
を通して回路基板の表裏面側の回路パターン間の接続が
できるため、表裏面側を多層化した厚膜多層回路基板が
提供できる。[Effects of the Invention] According to the thick film multilayer circuit board of the present invention,
Since the circuit board is flattened by filling the through holes with an insulator, the thickness of the circuit board does not change partially due to the through holes, and the number of stacked layers can be increased by flattening. Since circuit patterns on the front and back sides of the circuit board can be connected through through holes in addition to multilayering, it is possible to provide a thick film multilayer circuit board in which the front and back sides are multilayered.
【００２１】また、この発明の厚膜多層回路基板の製造
方法によれば、スルーホールが形成されている回路基板
に絶縁物を充填した後、絶縁層を形成し、その上に導体
パターンを形成するので、スルーホールによる凹凸を防
止して平坦化でき、絶縁層及び導体パターンの積層段数
を増加させることができるとともに、スルーホール内の
空気を絶縁物の充填によって排除でき、高密度化ととも
に信頼性を高めることができる。Further, according to the method for manufacturing a thick film multilayer circuit board of the present invention, after filling the circuit board in which through holes are formed with an insulating material, an insulating layer is formed, and a conductive pattern is formed on the insulating layer. As a result, unevenness caused by through holes can be prevented and flattened, the number of laminated layers of insulating layers and conductor patterns can be increased, and air in through holes can be eliminated by filling with insulating material, resulting in higher density and reliability. You can increase your sexuality.
【図１】この発明の厚膜多層回路基板の一実施例を示す
断面図である。FIG. 1 is a sectional view showing an embodiment of a thick film multilayer circuit board of the present invention.
【図２】この発明の厚膜多層回路基板の製造方法の一実
施例を示す断面図である。FIG. 2 is a sectional view showing an embodiment of the method for manufacturing a thick film multilayer circuit board of the present invention.
【図３】この発明の厚膜多層回路基板の製造方法の一実
施例を示す断面図である。FIG. 3 is a sectional view showing an embodiment of the method for manufacturing a thick film multilayer circuit board of the present invention.
【図４】図２に示した厚膜多層回路基板の製造方法の一
実施例における回路基板を示す部分斜視図である。4 is a partial perspective view showing a circuit board in one embodiment of the method for manufacturing the thick film multilayer circuit board shown in FIG. 2; FIG.
Claims (2)
ンがスルーホールを介して接続された回路基板と、この
回路基板の前記スルーホールに充填された絶縁物と、前
記導体パターンを覆って形成された絶縁層と、この絶縁
層上に形成された第２の導体パターンと、を備えたこと
を特徴とする厚膜多層回路基板。1. A circuit board to which a first conductive pattern formed on the front and back surfaces is connected via a through hole, an insulating material filled in the through hole of this circuit board, and a first conductive pattern covering the conductive pattern. A thick film multilayer circuit board comprising: an insulating layer; and a second conductor pattern formed on the insulating layer.
ンがスルーホールを通して接続された回路基板の前記ス
ルーホールに絶縁物を充填した後、前記回路基板の表面
を覆う絶縁層を形成し、この絶縁層の上に第２の導体パ
ターンを形成することを特徴とする厚膜多層回路基板の
製造方法。2. After filling the through holes of the circuit board to which the first conductor patterns formed on the front and back surfaces are connected through the through holes with an insulator, forming an insulating layer covering the front surface of the circuit board, A method for manufacturing a thick film multilayer circuit board, comprising forming a second conductor pattern on the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41142390A JP3057766B2 (en) | 1990-12-18 | 1990-12-18 | Thick film multilayer circuit board and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41142390A JP3057766B2 (en) | 1990-12-18 | 1990-12-18 | Thick film multilayer circuit board and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04217389A true JPH04217389A (en) | 1992-08-07 |
| JP3057766B2 JP3057766B2 (en) | 2000-07-04 |
Family
ID=18520435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41142390A Expired - Fee Related JP3057766B2 (en) | 1990-12-18 | 1990-12-18 | Thick film multilayer circuit board and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3057766B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997016056A1 (en) * | 1995-10-23 | 1997-05-01 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
| EP1198000A1 (en) * | 1994-04-28 | 2002-04-17 | Fujitsu Limited | Semiconductor device and assembly board |
| JP2007535143A (en) * | 2004-04-29 | 2007-11-29 | シーメンス アクチエンゲゼルシヤフト | Method for producing printed wiring boards and / or corresponding structures |
-
1990
- 1990-12-18 JP JP41142390A patent/JP3057766B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1198000A1 (en) * | 1994-04-28 | 2002-04-17 | Fujitsu Limited | Semiconductor device and assembly board |
| EP1715512A2 (en) * | 1994-04-28 | 2006-10-25 | Fujitsu Limited | Semiconductor device and method of forming the same |
| EP1715512A3 (en) * | 1994-04-28 | 2013-02-13 | Fujitsu Semiconductor Limited | Semiconductor device and method of forming the same |
| WO1997016056A1 (en) * | 1995-10-23 | 1997-05-01 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
| EP1318708A2 (en) * | 1995-10-23 | 2003-06-11 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
| EP1318708A3 (en) * | 1995-10-23 | 2003-06-18 | Ibiden Co., Ltd. | Resin filler and multilayer printed wiring board |
| EP1445996A2 (en) * | 1995-10-23 | 2004-08-11 | Ibiden Co., Ltd. | Build-up multilayer printed circuit board |
| EP1445996A3 (en) * | 1995-10-23 | 2004-08-18 | Ibiden Co., Ltd. | Build-up multilayer printed circuit board |
| JP2007535143A (en) * | 2004-04-29 | 2007-11-29 | シーメンス アクチエンゲゼルシヤフト | Method for producing printed wiring boards and / or corresponding structures |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3057766B2 (en) | 2000-07-04 |
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