JP2712295B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP2712295B2
JP2712295B2 JP63129372A JP12937288A JP2712295B2 JP 2712295 B2 JP2712295 B2 JP 2712295B2 JP 63129372 A JP63129372 A JP 63129372A JP 12937288 A JP12937288 A JP 12937288A JP 2712295 B2 JP2712295 B2 JP 2712295B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrate
resistor
paste
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63129372A
Other languages
Japanese (ja)
Other versions
JPH01298796A (en
Inventor
祐司 大谷
長坂　　崇
豊 福田
英樹 中川原
秀樹 谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP63129372A priority Critical patent/JP2712295B2/en
Publication of JPH01298796A publication Critical patent/JPH01298796A/en
Application granted granted Critical
Publication of JP2712295B2 publication Critical patent/JP2712295B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は混成集積回路に関するものである。Description: TECHNICAL FIELD The present invention relates to a hybrid integrated circuit.

［従来技術及び課題］ 従来の多層混成集積回路（多層ハイブリッドIC）にお
いては、第２図に示すように受動素子である厚膜抵抗体
１は多層よりなる基板２の表面においてターミナルとな
る導体3,4間に形成される。ところが、この厚膜抵抗体
１の占有面積は導体3,4を含めて1.6mm□程度必要となっ
ている。従って、このような厚膜抵抗体１を使用する場
合において抵抗体の数が多いときには基板サイズの小型
化（高密度化）に対応できないという問題があった。[Prior Art and Problems] In a conventional multi-layer hybrid integrated circuit (multi-layer hybrid IC), as shown in FIG. 2, a thick film resistor 1 as a passive element is a conductor 3 serving as a terminal on the surface of a multi-layer substrate 2. , 4 are formed. However, the area occupied by the thick film resistor 1 needs to be about 1.6 mm □ including the conductors 3 and 4. Therefore, when such a thick film resistor 1 is used, when the number of resistors is large, there is a problem that it is not possible to cope with a reduction in the size of the substrate (higher density).

この発明の目的は、上記課題に鑑み抵抗体等の受動素
子の占有面積を少なくし基板の小型化を図ることができ
る混成集積回路を提供することにある。An object of the present invention is to provide a hybrid integrated circuit that can reduce the area occupied by passive elements such as resistors and reduce the size of a substrate in view of the above problems.

［課題を解決するための手段］ この発明は、上層基板と下層基板との間に中間基板が
積層された３層以上よりなる混成集積回路であって、層
間の配線接続を施すために開けられた、少なくとも前記
中間層基板のホール部に対して抵抗体を組込んだことを
特徴とする混成集積回路をその要旨としている。[Means for Solving the Problems] The present invention relates to a hybrid integrated circuit having three or more layers in which an intermediate substrate is stacked between an upper layer substrate and a lower layer substrate. In addition, a gist of the present invention is a hybrid integrated circuit characterized in that a resistor is incorporated into at least a hole portion of the intermediate layer substrate.

［作用］ 中間層の配線接続を行うためのホール部に抵抗体が組
込まれ、層の表面においてはその抵抗体の占有面積は
“0"となる。[Operation] A resistor is incorporated in a hole portion for wiring connection of an intermediate layer, and the area occupied by the resistor on the surface of the layer is "0".

［実施例］ 以下、この発明を具体化した一実施例を図面に従って
説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

第１図は本実施例の混成集積回路基板の断面図であ
り、この実施例では３層構造とされている。FIG. 1 is a cross-sectional view of a hybrid integrated circuit board according to the present embodiment, which has a three-layer structure.

この混成集積回路において、中間層に抵抗体を配置す
る場合について以下述べる。この実施例は、導体ペース
トと絶縁ペーストを交互に印刷する方法により多層化し
たものである。The case where a resistor is arranged in the intermediate layer in this hybrid integrated circuit will be described below. In this embodiment, the conductive paste and the insulating paste are multilayered by alternately printing.

１枚の焼成したアルミナグリーンシート25上に導体ペ
ースト26のパターンを形成し、次に、そのアルミナ基板
25上に導体ペースト26に連通するホール部としてのビア
ホール27を有する絶縁ペースト（ガラスペーストあるい
はガラスセラミックペースト）28を印刷する。A pattern of conductive paste 26 is formed on one baked alumina green sheet 25, and then the alumina substrate
An insulating paste (glass paste or glass ceramic paste) 28 having a via hole 27 as a hole communicating with the conductor paste 26 is printed on 25.

その後、ビアホール27に導体ペースト29や抵抗体30を
スクリーン印刷法により充填する。さらに、絶縁ペース
ト28上において、前記導体ペースト29や抵抗体30に接続
するように導体ペースト32のパターンを印刷にて形成す
る。次に、絶縁ペースト28上に導体ペースト32に連通す
るビアホール33を有する絶縁ペースト31を印刷する。そ
して、前記ビアホール33に導体ペースト34をスクリーン
印刷法により充填する。その後、焼成することにより混
成集積回路が形成される。After that, the via hole 27 is filled with the conductor paste 29 and the resistor 30 by a screen printing method. Further, a pattern of the conductor paste 32 is formed on the insulating paste 28 by printing so as to be connected to the conductor paste 29 and the resistor 30. Next, the insulating paste 31 having the via holes 33 communicating with the conductor paste 32 is printed on the insulating paste. Then, a conductive paste 34 is filled in the via hole 33 by a screen printing method. Thereafter, firing is performed to form a hybrid integrated circuit.

この混成集積回路においては、通常の層間配線接続を
行うビアホール27に抵抗体30が組込まれ、絶縁ペースト
（基板）31の表面においては、その抵抗体の占有面積は
“0"となり、抵抗体の数が多くてもその占有面積を少な
くし基板の小型化を図ることができる。In this hybrid integrated circuit, a resistor 30 is incorporated in a via hole 27 for making a normal interlayer wiring connection, and the area occupied by the resistor on the surface of the insulating paste (substrate) 31 is “0”, and Even if the number is large, the occupied area can be reduced and the size of the substrate can be reduced.

又、ビアホールの抵抗体形成プロセスは従来のビアホ
ールへの導体充填工程を抵抗体充填工程に置き換えるだ
けでよくなるため、従来の工程に特別の工程を付加する
ことなく容易に行うことができる。In addition, since the process of forming a resistor in a via hole only requires replacing the process of filling a conductor into a conventional via hole with a process of filling a resistor, the process can be easily performed without adding a special process to the conventional process.

なお、この発明は上記実施例に限定されるものではな
く、抵抗体の代わりに誘電体を受動素子としてスクリー
ン印刷法で組込んでもよい。The present invention is not limited to the above embodiment, and a dielectric may be used as a passive element instead of a resistor by a screen printing method.

多層の基板を全部アルミナにしてもよく、又、アルミ
ナ以外に基板材料として、例えば、ガラスセラミック
や、あるいはガラスエポキシ等の樹脂材料であってもよ
い。The multilayer substrate may be entirely made of alumina, or a substrate material other than alumina, for example, a resin material such as glass ceramic or glass epoxy.

又、この発明の構造は両面スルーホール基板における
スルーホール部にも適用できる。Further, the structure of the present invention can be applied to a through-hole portion in a double-sided through-hole substrate.

［発明の効果］ 以上詳述したようにこの発明によれば、回路基板が３
層以上であって、少なくともその中間層に設けられたホ
ール部が抵抗体等の受動素子として効率良く利用される
ため、層上の抵抗体等の受動素子の占有面積を少なく
し、十分な回路基板の小型化を図ることができる優れた
効果を発揮する。[Effects of the Invention] As described in detail above, according to the present invention, the circuit board has 3
Layer or more, and at least the hole provided in the intermediate layer is efficiently used as a passive element such as a resistor. An excellent effect that the size of the substrate can be reduced is exhibited.

特に、回路規模が大きくなる反面、基板の小型化（高
密度化）が益々要求されるこの分野においては、この発
明によれば基板が高密度化すればするほど有利となる効
果がある。In particular, in this field where the size of the circuit is increased, but the size (density) of the substrate is increasingly required, according to the present invention, the higher the density of the substrate, the more advantageous the effect.

【図面の簡単な説明】[Brief description of the drawings]

第１図は、この発明を具体化した混成集積回路の断面
図。第２図は、従来の混成集積回路の断面図。 25はアルミナ基板、27はビアホール、28は絶縁ペース
ト、30は抵抗体ペースト、31は絶縁ペースト。FIG. 1 is a sectional view of a hybrid integrated circuit embodying the present invention. FIG. 2 is a cross-sectional view of a conventional hybrid integrated circuit. 25 is an alumina substrate, 27 is a via hole, 28 is an insulating paste, 30 is a resistor paste, and 31 is an insulating paste.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中川原 英樹 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (72)発明者 谷川 秀樹 愛知県刈谷市昭和町１丁目１番地 日本 電装株式会社内 (56)参考文献 特開 昭58−21390（ＪＰ，Ａ) 特開 昭64−64394（ＪＰ，Ａ) ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hideki Nakagawara 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Inside Denso Co., Ltd. (72) Inventor Hideki Tanigawa 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Nihon Denso Co., Ltd. (56) References JP-A-58-21390 (JP, A) JP-A-64-64394 (JP, A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】上層基板と下層基板との間に中間基板が積
層された３層以上よりなる混成集積回路であって、 層間の配線接続を施すために開けられた、少なくとも前
記中間層基板のホール部に対して抵抗体を組込んだこと
を特徴とする混成集積回路。1. A hybrid integrated circuit comprising at least three layers in which an intermediate substrate is stacked between an upper substrate and a lower substrate, wherein at least one of the intermediate substrates is opened for connection between layers. A hybrid integrated circuit characterized by incorporating a resistor in a hole portion.
JP63129372A 1988-05-26 1988-05-26 Hybrid integrated circuit Expired - Lifetime JP2712295B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63129372A JP2712295B2 (en) 1988-05-26 1988-05-26 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63129372A JP2712295B2 (en) 1988-05-26 1988-05-26 Hybrid integrated circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9193475A Division JPH1065342A (en) 1997-07-18 1997-07-18 Multilayer circuit board and manufacture thereof

Publications (2)

Publication Number Publication Date
JPH01298796A JPH01298796A (en) 1989-12-01
JP2712295B2 true JP2712295B2 (en) 1998-02-10

Family

ID=15007953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63129372A Expired - Lifetime JP2712295B2 (en) 1988-05-26 1988-05-26 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP2712295B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164699A (en) * 1990-12-17 1992-11-17 Hughes Aircraft Company Via resistors within-multi-layer, 3 dimensional structures substrates
US5500278A (en) * 1991-07-17 1996-03-19 Nippondenso Co., Ltd. Multilayer substrate
JP3671457B2 (en) * 1995-06-07 2005-07-13 株式会社デンソー Multilayer board
JP4032459B2 (en) 1997-08-05 2008-01-16 株式会社デンソー Hybrid integrated circuit substrate and method of manufacturing the same
US6622374B1 (en) 2000-09-22 2003-09-23 Gould Electronics Inc. Resistor component with multiple layers of resistive material
JP2007251216A (en) * 2007-07-05 2007-09-27 Denso Corp Wiring board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821390A (en) * 1981-07-31 1983-02-08 株式会社日立製作所 Method of producing ceramic substrate
JPS58213890A (en) * 1982-06-07 1983-12-12 Kureha Chem Ind Co Ltd Method and device for producing laminated molding of fibrous material having electrophoresis charge
JPS6464394A (en) * 1987-09-04 1989-03-10 Fujitsu Ltd Hybrid integrated circuit substrate

Also Published As

Publication number Publication date
JPH01298796A (en) 1989-12-01

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