JPH04211150A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH04211150A JPH04211150A JP3774291A JP3774291A JPH04211150A JP H04211150 A JPH04211150 A JP H04211150A JP 3774291 A JP3774291 A JP 3774291A JP 3774291 A JP3774291 A JP 3774291A JP H04211150 A JPH04211150 A JP H04211150A
- Authority
- JP
- Japan
- Prior art keywords
- protective resin
- circuit board
- resin
- protective
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims abstract description 179
- 229920005989 resin Polymers 0.000 claims abstract description 179
- 230000001681 protective effect Effects 0.000 claims abstract description 151
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 97
- 239000000377 silicon dioxide Substances 0.000 claims description 48
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000002245 particle Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 17
- 229920001721 polyimide Polymers 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 9
- 229920002647 polyamide Polymers 0.000 claims description 6
- 239000000565 sealant Substances 0.000 claims description 5
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 230000035882 stress Effects 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 18
- 239000002904 solvent Substances 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 10
- 230000007423 decrease Effects 0.000 description 7
- 239000002952 polymeric resin Substances 0.000 description 7
- 229920003002 synthetic resin Polymers 0.000 description 7
- 239000000945 filler Substances 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920006122 polyamide resin Polymers 0.000 description 2
- -1 (9) Polymers 0.000 description 1
- 208000002197 Ehlers-Danlos syndrome Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- SBZXBUIDTXKZTM-UHFFFAOYSA-N diglyme Chemical compound COCCOCCOC SBZXBUIDTXKZTM-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000008262 pumice Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、回路基板に形成された
配線導体に半導体素子が突起状電極を介して電気的に接
続された構造を有する回路基板装置に関する。
［０００２］BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board device having a structure in which semiconductor elements are electrically connected to wiring conductors formed on a circuit board via projecting electrodes. [0002]
【従来技術及び本願の解決すべき課題】半田バンプ（突
起状電極）を有する半導体チップ（フリップチップが回
路基板上の配線導体に固着され且つ電気的に接続された
構造の回路基板装置がある。この種の回路基板装置では
、フリップチップと回路基板の熱膨張係数差に起因する
熱疲労によって半田バンプに亀裂が生じる不良モードが
発生し易い。半田バンプの熱疲労特性を向上する策とし
て半田バンプの形状を改良することが知られている。
例えば、特開昭６３−６２３３３号公報では半田バンプ
を柱状に高く形成して、半田バンプの熱疲労を緩和する
方法が開示されている。しかしながら、柱状の半田バン
プを形成するためには予め大面積の半田バンプを形成す
る必要があり、フリップチップの小形・高密度実装化の
点で不利である。また、柱状の半田バンプを形成するこ
と自体容易ではない。そこで、本願は上記の問題を解決
し、熱疲労特性に優れた回路基板装置を提供することを
目的とする。BACKGROUND OF THE INVENTION There is a circuit board device having a structure in which a semiconductor chip (flip chip) having solder bumps (protruding electrodes) is fixed to a wiring conductor on a circuit board and electrically connected. In this type of circuit board device, a failure mode in which cracks occur in the solder bumps is likely to occur due to thermal fatigue caused by the difference in thermal expansion coefficient between the flip chip and the circuit board. It is known to improve the shape of solder bumps. For example, Japanese Patent Application Laid-Open No. 63-62333 discloses a method of forming solder bumps in a columnar shape to alleviate thermal fatigue of the solder bumps. However, In order to form columnar solder bumps, it is necessary to form large-area solder bumps in advance, which is disadvantageous in terms of miniaturization and high-density packaging of flip chips.Furthermore, forming columnar solder bumps itself is disadvantageous. Therefore, the present application aims to solve the above problems and provide a circuit board device with excellent thermal fatigue characteristics.
【０００３］
【課題を解決のための手段】本発明の回路基板装置は、
半導体素子と、一方の主面に配線導体が形成された回路
基板とを有し、半導体素子の一方の主面と回路基板の一
方の主面とが離間して対向するように配置され、半導体
素子が配線導体に突起状電極を介して電気的に接続され
ている。回路基板の一方の主面と半導体素子の一方の主
面とが対向する領域に粒状シリカとポリイミド系又はポ
リアミド系の樹脂を含有する保護樹脂が充填されている
。保護樹脂の線膨張係数は回路基板の線膨張係数より小
さく半導体素子の線膨張係数よりも大きい。粒状シリカ
の平均粒径は５μｍ〜２５μｍである。保護樹脂は、８
５．５重量％〜９６．５重電％の粒状シリカを含有して
いる。また、本発明では、回路基板の一方の主面と半導
体素子の一方の主面とが対向する領域に粒状シリカとポ
リイミド系又はポリアミド系の樹脂を含有する第１の保
護樹脂が充填され、半導体素子及び第１の保護樹脂は第
２の保護樹脂で被覆されている。更に第２の保護樹脂は
樹脂封止体で被覆されている。第１の保護樹脂の線膨張
係数は回路基板の線膨張係数より小さく半導体素子の線
膨張係数よりも大きい。第２の保護樹脂の線膨張係数は
第１の保護樹脂の線膨張係数よりも大きく、樹脂封止体
の線膨張係数よりも小さい。第２の保護樹脂は粒状シリ
カとポリイミド系又はポリアミド系の樹脂を含有する。
第１の保護樹脂と第２の保護樹脂は多孔質であり、第２
の保護樹脂の気孔率は第１の保護樹脂のそれよりも小さ
い。第１の保護樹脂に含有されている粒状シリカの平均
粒径は５μｍ〜２５μｍで、第２の保護樹脂に含有され
ている粒状シリカの平均粒径は第１の保護樹脂に含有さ
れている粒状シリカの平均粒径よりも５μｍ以上大きい
。
第１の保護樹脂は粒径のシリカを８５．５重量％〜９６
゜５重量％含有しており、第２の保護樹脂は第１の保護
樹脂よりも２重電％以上少ない粒状シリカを含有してい
る。
［０００４］[Means for Solving the Problems] The circuit board device of the present invention has the following features:
The semiconductor device has a semiconductor element and a circuit board on which a wiring conductor is formed on one main surface, and is arranged so that one main surface of the semiconductor element and one main surface of the circuit board face each other with a distance between them. The element is electrically connected to the wiring conductor via a protruding electrode. A region where one main surface of the circuit board and one main surface of the semiconductor element face each other is filled with a protective resin containing granular silica and a polyimide-based or polyamide-based resin. The linear expansion coefficient of the protective resin is smaller than that of the circuit board and larger than that of the semiconductor element. The average particle size of the granular silica is 5 μm to 25 μm. The protective resin is 8
It contains 5.5% by weight to 96.5% by weight of granular silica. Further, in the present invention, a region where one main surface of the circuit board and one main surface of the semiconductor element face each other is filled with a first protective resin containing granular silica and a polyimide-based or polyamide-based resin, The element and the first protective resin are coated with a second protective resin. Furthermore, the second protective resin is covered with a resin sealant. The linear expansion coefficient of the first protective resin is smaller than that of the circuit board and larger than that of the semiconductor element. The linear expansion coefficient of the second protective resin is larger than that of the first protective resin and smaller than that of the resin sealant. The second protective resin contains granular silica and a polyimide-based or polyamide-based resin. The first protective resin and the second protective resin are porous, and the second protective resin is porous.
The porosity of the protective resin is smaller than that of the first protective resin. The average particle size of the granular silica contained in the first protective resin is 5 μm to 25 μm, and the average particle size of the granular silica contained in the second protective resin is the same as that of the granular silica contained in the first protective resin. 5 μm or more larger than the average particle size of silica. The first protective resin contains silica with a particle size of 85.5% to 96% by weight.
5% by weight, and the second protective resin contains more than 2% less particulate silica than the first protective resin. [0004]
【作用】本願の「請求項１」に記載の発明によれば、粒
状シリカとポリイミド系又はポリアミド系の樹脂を含有
する保護樹脂が半導体素子と回路基板の間に充填されて
いる。このため、保護樹脂の線膨張係数を半導体素子と
回路基板のそれの中間の値に設定できるし、比較的大き
な皮弾性率も得られる。したがって、半導体素子と回路
基板の熱膨張係数差に起因する熱応力や回路基板のそり
等に起因する機械的応力の突起状電極への影響を保護樹
脂によって有効に緩和することができる。 「請求項２
」「請求項３」はその−例として望ましい。また、 「
請求項４」に記載の発明によれば、第１の保護樹脂−第
２の保護樹脂−樹脂封止体の系で線膨張係数が階段的に
増大するので、それぞれの樹脂界面における熱応力が小
さくなる。第２の保護樹脂が第１の保護樹脂よりも気孔
率が小さいと、水分等の異物に対する大きな浸入防止効
果が得られる。
［０００５］According to the invention described in Claim 1 of the present application, a protective resin containing granular silica and a polyimide or polyamide resin is filled between the semiconductor element and the circuit board. Therefore, the linear expansion coefficient of the protective resin can be set to a value intermediate between those of the semiconductor element and the circuit board, and a relatively large skin elastic modulus can be obtained. Therefore, the influence of thermal stress caused by the difference in coefficient of thermal expansion between the semiconductor element and the circuit board and mechanical stress caused by warping of the circuit board on the protruding electrode can be effectively alleviated by the protective resin. “Claim 2
"Claim 3" is desirable as an example. Also, "
According to the invention described in claim 4, the coefficient of linear expansion increases stepwise in the system of the first protective resin, the second protective resin, and the resin sealant, so that the thermal stress at the interface of each resin increases. becomes smaller. When the second protective resin has a lower porosity than the first protective resin, a large effect of preventing infiltration of foreign substances such as moisture can be obtained. [0005]
【実施例】以下、本発明の一実施例としてフリップチッ
プが固着された回路基板を有する電力用ハイブリッドＩ
Ｃについて説明する。本実施例の電力用ハイブリッドＩ
Ｃは、第１図に示すように、支持板（１）、外部リード
（２）、回路基板（３）、半導体素子としてのフリップ
チップ（４）、電力用半導体チップ（５）、第１の保護
樹脂（６）、第２の保護樹脂（７）、第３の保護樹脂（
８）及び樹脂封止体（９）とを有する。支持板（１）と
外部リド（２）は金属板材の打ち抜きによって形成され
、支持板（１）の厚みは外部リード（２）の厚みよりも
大きい。
支持板（１）の一方の主面には回路基板（３）と電力用
半導体チップ（５）がそれぞれ接着剤と半田を介して固
着されている。支持板（１）は電力用半導体チップ（５
）と回路基板（３）の放熱板として機能する。回路基板
（３）はＡｌ２Ｏ３（アルミナ）セラミックス基板（線
膨張係数６ 、８ Ｘ １０−６／’Ｃ）から成り、そ
の一方の主面には厚膜導体ペーストを焼成して形成され
た配線導体（１０）が設けられている。本明細書では電
極部、配線部を総称して配線導体と称する。フリップチ
ップ（４）はトランジスタやモノリシックＩＣを構成す
るシリコン半導体チップ（線膨張係数３．０×１０−６
／℃）から成り、その一方の主面には電極及び半田バン
プ（１１）が形成されている。
半田バンプ（１１）は多層の金属層の上に半球状の半田
層が形成されて成るが、第１図及び第２図ではその詳し
い図示を省略する。フリップチップ（４）は従来例と同
様に半田バンプ（１１）が配線導体（１０）に固着され
ており、その一方の主面が回路基板（３）の一方の主面
に対向するように配置されている。なお、本実施例では
、フリップチップ（４）の固着を周知の半田リフロー法
で行った。フリップチップ（４）の一方の主面と回路基
板（３）の一方の主面との間隔は約１００μｍとなって
おり、フリップチップ（４）と回路基板（３）とが対向
する領域には本発明に基づいて第１の保護樹脂（６）が
充填されている。回路基板（３）の上面にはその略全面
にわたって第１の保護樹脂（６）とは異なる第２の保護
樹脂（７）が形成されており、フリップチップ（４）の
上面及び第１の保護樹脂（６）は第２の保護樹脂（７）
によって被覆されている。また、電力用半導体チップ（
５）の上面には上記第１及び第２の保護樹脂（６）
（７）とは異なる第３の保護樹脂（８）が形成されてい
る。このため、電力用半導体チップ（５）と回路基板（
３）の配線導体（１０）とを電気的に接続するリード細
線（１２）は、その一方の端部側が第３の保護樹脂（８
）に被覆され、他方の端部側が第２の保護樹脂（７）に
被覆される。支持板（１）の全面と外部リード（２）の
端部は周知のトランスファモルト法で形成されたエポキ
シ樹脂（線膨張係数２０×１０−６／℃）から成る樹脂
封止体（９）によって封止されており、第２及び第３の
保護樹脂（７） （８）は樹脂封止体（９）によって
被覆されている。
［０００６１本実施例の電力用ハイブリットＩＣの従来
と異なる点は、フリップチップ（４）と回路基板（３）
との間に充填された第１の保護樹脂（６）と回路基板（
３）の全面を被覆する第２の保護樹脂（７）とが従来の
この種の保護樹脂とその組成が著しく異なることにある
。即ち、従来の回路基板装置ではフリップチップ（４）
の下面側も含めて回路基板（３）の上面はシリコンラバ
（線膨張係数２． Ｏｘ １０−４／℃）等から成る軟
質性の保護樹脂で被覆されていた。本実施例では、フリ
ップチップ（４）と回路基板（３）との間に充填された
第１の保護樹脂（６）がポリイミド系のファインポリマ
レジンとその平均粒径が１２．５μｍに規定された粒状
シリカから構成されており且つその混合比が重量比でフ
ァインポリマレジン二粒状シリカ＝１：９となっている
硬質性の樹脂である。このため、第１の保護樹脂（６）
は回路基板（３）とフリップチップ（４）の両方に対し
て良好な接着性を有するとともにその線膨張係がフリッ
プチップ（４）と回路基板（３）のそれらの中間（約５
Ｘ １０−６／℃）となっている。第２の保護樹脂（
７）は第１の保護樹脂（６）と同様にポリイミド系のフ
ァインポリマレジンと粒状シリカから構成される硬質性
の保護樹脂であるが、第１の保護樹脂（６）とは粒状シ
リカの粒径及び混合比が異なっている。即ち、第２の保
護樹脂（７）に含有される粒状シリカの平均粒径は第１
の保護樹脂（６）のそれより大きく約３１．５μｍであ
り、ファインボリマレジンと粒状シリカの混合比は重量
比でファインポリマレジン二粒状シリカ＝２＝８となっ
ている。このため、第２の保護樹脂（７）の線膨張係数
は第１の保護樹脂（６）のそれよりも大きく、約１０×
１０−６／℃である。なお、回路基板（３）及びフリッ
プチップ（４）に対する接着性は第１の保護樹脂と同程
度に得られる。電力用半導体チップ（５）を被覆する第
３の保護樹脂（８）は第１及び第２の保護樹脂（６）
（７）とは異なりシリカを含有しないポリイミド樹脂
である。本実施例では、熱処理後に常温において硬質性
を有するリジットタイプの樹脂を硬質性樹脂と称し、常
温において軟質性を有する樹脂を軟質性樹脂と称する。
第１及び第２の保護樹脂（６） （７）はいずれも熱
処理によって硬化させる前では、例えばジエチレングリ
コールジメチルエーテル（２５℃における粘度０．９８
１ＣＰの溶剤）等の揮発性溶剤を含有しており、常温で
流動性のある樹脂である。しかしながら、揮発性溶剤の
含有率は第１の保護樹脂（６）と第２の保護樹脂（７）
とで異なっており、第１の保護樹脂（６）は熱処理によ
って硬化させる前において、その全重量に対して揮発性
溶剤を３０重量％含有する。第２の保護樹脂（７）は熱
処理によって硬化させる前において、その全重量に対し
て揮発性溶剤を２５重量％含有している。第１図に示す
ようにフリップチップ（４）と回路基板（３）の間に第
１の保護樹脂（６）を充填するにはフリップチップ（４
）が固着された回路基板（３）を用意し、揮発性溶剤を
含有する第１の保護樹脂（６）をフリップチップ（４）
の側面に塗布する。第１の保護樹脂（６）は上記のよう
に揮発性溶剤を多く含有しており且つ粒状シリカの平均
粒径が１２．５μｍと小さいから、フリップチップ（４
）と回路基板（３）との間に良好に流れ込み、ここを充
填することができる。
［０００７］次に、この組立体を室温中で１時間程度保
管して、第１の保護樹脂（６）中に含有される揮発性溶
剤の一部を発揮させる。これにより、第１の保護樹脂（
６）の流動性が損なわれる。次に、揮発性溶剤を含有す
る第２の保護樹脂（７）を回路基板（３）の全面に形成
してフリップチップ（４）と第１の保護樹脂（６）を被
覆する。第２の保護樹脂（７）は第１の保護樹脂（６）
に比べてシリカの平均粒径が大きく且つ揮発性溶剤の含
有率が小さいので、第１の保護樹脂（６）に比べて流動
性が劣る。続いて、第１の保護樹脂（６）と第２の保護
樹脂（７）に室温で５時間、４０℃で４時間、１５０℃
で３時間の熱処理を段階的に施して、第１の保護樹脂（
６）と第２の保護樹脂（７）に含有される揮発性溶剤を
実質的に全て揮発させる。第１の保護樹脂（６）は溶剤
が揮発することによって、熱処理前に比べてその体積が
減少する。しかしながら、ファインポリマレジンに比べ
て粒状シリカを多量に含有する第１の保護樹脂（６）は
溶剤の揮発によって生じる気泡が第１の保護樹脂（６）
中に分散して形成された構造となる。つまり、第１の保
護樹脂（６）は粒状シリカと粒状シリカ間を結合するフ
ァインポリマレジンと溶剤の揮発によって生じた気泡（
空孔）から構成された「軽石」状と呼べる多孔質構造と
なっている。したがって、第１の保護樹脂（６）の上面
はフリップチップ（４）の一方の主面に固着されている
から当接し、第１の保護樹脂（６）とフリップチップ（
４）との間に隙間が形成されない。第２の保護樹脂（７
）も溶剤が揮発することによって同様に多孔質構造とな
るが、揮発性溶剤の含有率が小さい分だけ第１の保護樹
脂（６）よりも気孔率は小さい。
［０００８］上記の実施例によれば、フリップチップ（
４）と回路基板（３）との間にこれらの線膨張係数の中
間の線膨張係数を有する第１の保護樹脂（６）が充填さ
れる。このため、フリップチップ（４）と回路基板（３
）の熱膨張係数差に起因する半田バンプ（１１）への熱
応力を第１の保護樹脂（６）によって有効に緩和するこ
とができる。即ち、第１の保護樹脂（６）は含有する粒
状シリカの平均粒径と混合比がそれぞれ１２．５μｍ、
９０重量％に規定されている。この結果、第１の保護樹
脂（６）の線膨張係数を半田バンプ（１１）の熱応力緩
和に最適な線膨張係数（５Ｘ １０−６／℃）に設定で
きる。また、熱処理前では第１の保護樹脂（６）は流動
性に優れているから、フリップチップ（４）と回路基板
（３）の間に第１の保護樹脂（６）を短時間でかつ十分
に充填することが可能である。
［０００９］第３図に示すように、粒状シリカの混合比
が小さくなると、第１の保護樹脂（６）の線膨張係数が
増大し、これが回路基板（３）の線膨張係数（６，８Ｘ
１０−６／’Ｃ）を越えると応力緩和用の充填材として
望ましくない。また、粒状シリカの混合比が大きくなる
と線膨張係数が低下し、これがフリップチップ（４）の
線膨張係数（３，Ｏｘ １０−６／’Ｃ）を下回るとや
はり応力緩和用の充填材としては望ましくない。また、
粒状シリカの混合比が同じであっても、その粒径が増大
すると線膨張係数が増大するし、皮膜弾性率が低下し、
望ましくない。第３図では、比較のためにその平均粒径
が第２の保護樹脂（７）と同じ３１．５μｍとしたとき
の線膨張係数を示す。図示のように、粒状シリカの混合
比が９０重電電であっても、平均粒径が３１．５μｍと
なると、線膨張係数が回路基板（３）のそれよりも大き
くなり、応力緩和用の充填材として良好に機能しなくな
る。また、皮膜弾性率が低下し、回路基板（３）のソリ
等に起因する機械的応力の緩和作用も低下すると考えら
れる。粒状シリカの平均粒径が小さいと、線膨張係数は
小さく皮膜弾性率は大きいが、熱処理前の第１の保護樹
脂（６）にチキソ性（ｔｈｉｘｏｔｒｏｐｙ）が生じて
見掛は上の粘性が増加する。このため、第１の保護樹脂
（６）をフリップチップ（４）と回路基板（３）との間
に良好に流し込むことが困難となる。以上のように、本
実施例では、応力緩和用の充填材として望ましい線膨張
係数及び皮膜弾性率が得られ且つ形成時の流動性も良好
となるように第１の保護樹脂（６）の粒状シリカの混合
比及び平均粒径が規定されている。[Example] Hereinafter, as an example of the present invention, a power hybrid I having a circuit board to which a flip chip is fixed.
C will be explained. Electric power hybrid I of this embodiment
As shown in FIG. 1, C includes a support plate (1), an external lead (2), a circuit board (3), a flip chip (4) as a semiconductor element, a power semiconductor chip (5), and a first Protective resin (6), second protective resin (7), third protective resin (
8) and a resin sealing body (9). The support plate (1) and the external lead (2) are formed by punching out a metal plate, and the thickness of the support plate (1) is greater than the thickness of the external lead (2). A circuit board (3) and a power semiconductor chip (5) are fixed to one main surface of the support plate (1) via adhesive and solder, respectively. The support plate (1) is a power semiconductor chip (5
) and the circuit board (3). The circuit board (3) is made of an Al2O3 (alumina) ceramic substrate (linear expansion coefficient 6, 8 x 10-6/'C), and one main surface thereof has a wiring conductor formed by firing a thick film conductor paste. (10) is provided. In this specification, the electrode portion and the wiring portion are collectively referred to as a wiring conductor. The flip chip (4) is a silicon semiconductor chip (linear expansion coefficient 3.0 x 10-6) that constitutes a transistor or monolithic IC.
/°C), and electrodes and solder bumps (11) are formed on one main surface thereof. The solder bump (11) is formed by forming a hemispherical solder layer on a multilayer metal layer, but detailed illustration thereof is omitted in FIGS. 1 and 2. Similar to the conventional example, the flip chip (4) has solder bumps (11) fixed to the wiring conductor (10), and is arranged so that one main surface thereof faces one main surface of the circuit board (3). has been done. In this example, the flip chip (4) was fixed by a well-known solder reflow method. The distance between one main surface of the flip chip (4) and one main surface of the circuit board (3) is approximately 100 μm, and the area where the flip chip (4) and the circuit board (3) face each other is A first protective resin (6) is filled according to the invention. A second protective resin (7) different from the first protective resin (6) is formed on the upper surface of the circuit board (3) over almost the entire surface thereof, and a second protective resin (7) different from the first protective resin (6) is formed on the upper surface of the flip chip (4) and the first protective resin. Resin (6) is second protective resin (7)
covered by. In addition, power semiconductor chips (
5) The above first and second protective resins (6) are on the top surface.
A third protective resin (8) different from (7) is formed. For this reason, the power semiconductor chip (5) and the circuit board (
One end of the thin lead wire (12) that electrically connects the wiring conductor (10) of 3) is coated with the third protective resin (8).
), and the other end side is covered with a second protective resin (7). The entire surface of the support plate (1) and the ends of the external leads (2) are sealed with a resin sealing body (9) made of epoxy resin (linear expansion coefficient 20 x 10-6/°C) formed by the well-known transfer molding method. The second and third protective resins (7) and (8) are covered with a resin sealant (9). [00061 The difference between the power hybrid IC of this example and the conventional one is that the flip chip (4) and the circuit board (3)
The first protective resin (6) filled between the circuit board (
3) The second protective resin (7) that covers the entire surface is significantly different in composition from conventional protective resins of this type. That is, in the conventional circuit board device, the flip chip (4)
The upper surface of the circuit board (3), including the lower surface of the circuit board (3), was covered with a soft protective resin made of silicone rubber (linear expansion coefficient: 2.Ox 10-4/°C). In this example, the first protective resin (6) filled between the flip chip (4) and the circuit board (3) is made of polyimide-based fine polymer resin with an average particle size of 12.5 μm. It is a hard resin composed of granular silica, and the mixing ratio of fine polymer resin and granular silica is 1:9 by weight. For this reason, the first protective resin (6)
has good adhesion to both the circuit board (3) and the flip chip (4), and its linear expansion coefficient is between those of the flip chip (4) and the circuit board (3) (approximately 5
X 10-6/°C). Second protective resin (
Similar to the first protective resin (6), 7) is a hard protective resin composed of polyimide-based fine polymer resin and granular silica, but the first protective resin (6) is made of granular silica particles. The diameter and mixing ratio are different. That is, the average particle diameter of the granular silica contained in the second protective resin (7) is the same as that of the first protective resin (7).
It is approximately 31.5 μm, which is larger than that of the protective resin (6), and the mixing ratio of fine polymer resin and granular silica is such that the weight ratio of fine polymer resin and granular silica is 2=8. Therefore, the linear expansion coefficient of the second protective resin (7) is larger than that of the first protective resin (6), about 10×
10-6/°C. Note that the adhesiveness to the circuit board (3) and the flip chip (4) can be obtained to the same degree as that of the first protective resin. The third protective resin (8) covering the power semiconductor chip (5) is the same as the first and second protective resin (6).
Unlike (7), this is a polyimide resin that does not contain silica. In this example, a rigid type resin that is hard at room temperature after heat treatment is referred to as a hard resin, and a resin that is soft at room temperature after heat treatment is referred to as a soft resin. Before being cured by heat treatment, the first and second protective resins (6) and (7) are, for example, diethylene glycol dimethyl ether (viscosity 0.98 at 25°C).
It contains volatile solvents such as 1CP solvent) and is a fluid resin at room temperature. However, the content of volatile solvent is different between the first protective resin (6) and the second protective resin (7).
The first protective resin (6) contains 30% by weight of a volatile solvent based on its total weight before being cured by heat treatment. The second protective resin (7) contains 25% by weight of a volatile solvent based on its total weight before being cured by heat treatment. As shown in Figure 1, in order to fill the first protective resin (6) between the flip chip (4) and the circuit board (3), the flip chip (4)
) is fixed to a circuit board (3), and a first protective resin (6) containing a volatile solvent is attached to a flip chip (4).
Apply to the sides of the The first protective resin (6) contains a large amount of volatile solvent as described above, and the average particle size of the granular silica is as small as 12.5 μm.
) and the circuit board (3) and can be filled there. [0007] Next, this assembly is stored at room temperature for about one hour to allow some of the volatile solvent contained in the first protective resin (6) to be released. As a result, the first protective resin (
6) fluidity is impaired. Next, a second protective resin (7) containing a volatile solvent is formed over the entire surface of the circuit board (3) to cover the flip chip (4) and the first protective resin (6). The second protective resin (7) is the first protective resin (6)
Since the average particle size of silica is larger than that of the first protective resin (6) and the content of volatile solvent is small, the fluidity is inferior to that of the first protective resin (6). Subsequently, the first protective resin (6) and the second protective resin (7) were heated at room temperature for 5 hours, at 40°C for 4 hours, and at 150°C.
The first protective resin (
6) and the second protective resin (7) are substantially all volatilized. As the solvent evaporates, the volume of the first protective resin (6) decreases compared to before the heat treatment. However, the first protective resin (6), which contains a large amount of granular silica compared to fine polymer resin, has air bubbles generated by the volatilization of the solvent.
The structure is formed by being dispersed inside. In other words, the first protective resin (6) contains air bubbles (
It has a porous structure that can be called a "pumice stone" made up of pores. Therefore, the upper surface of the first protective resin (6) is fixed to one main surface of the flip chip (4) and comes into contact with the first protective resin (6) and the flip chip (4).
4) No gap is formed between the two. Second protective resin (7
) also has a porous structure due to volatilization of the solvent, but the porosity is smaller than that of the first protective resin (6) due to the lower content of the volatile solvent. [0008] According to the above embodiments, a flip chip (
4) and the circuit board (3) is filled with a first protective resin (6) having a linear expansion coefficient intermediate between these coefficients of linear expansion. For this reason, the flip chip (4) and the circuit board (3)
Thermal stress on the solder bumps (11) caused by the difference in thermal expansion coefficients between the solder bumps (11) can be effectively alleviated by the first protective resin (6). That is, the first protective resin (6) contains granular silica having an average particle diameter and a mixing ratio of 12.5 μm, respectively.
It is specified at 90% by weight. As a result, the linear expansion coefficient of the first protective resin (6) can be set to the optimal linear expansion coefficient (5X 10-6/°C) for alleviating the thermal stress of the solder bumps (11). In addition, since the first protective resin (6) has excellent fluidity before heat treatment, the first protective resin (6) can be quickly and thoroughly applied between the flip chip (4) and the circuit board (3). It is possible to fill the [0009] As shown in FIG. 3, when the mixing ratio of granular silica decreases, the linear expansion coefficient of the first protective resin (6) increases, and this increases the linear expansion coefficient (6,8X
10-6/'C), it is not desirable as a filler for stress relaxation. Furthermore, as the mixing ratio of granular silica increases, the coefficient of linear expansion decreases, and if this is lower than the coefficient of linear expansion (3, Ox 10-6/'C) of the flip chip (4), it cannot be used as a filler for stress relaxation. Undesirable. Also,
Even if the mixing ratio of granular silica is the same, as the particle size increases, the linear expansion coefficient increases and the film elastic modulus decreases.
Undesirable. In FIG. 3, for comparison, the linear expansion coefficient is shown when the average particle size is 31.5 μm, which is the same as the second protective resin (7). As shown in the figure, even if the mixing ratio of granular silica is 90%, when the average particle size is 31.5 μm, the coefficient of linear expansion becomes larger than that of the circuit board (3), and the filling is used for stress relaxation. It will no longer function well as a material. It is also believed that the elastic modulus of the film decreases, and the effect of alleviating mechanical stress caused by warping of the circuit board (3) also decreases. When the average particle size of the granular silica is small, the linear expansion coefficient is small and the film elastic modulus is large, but thixotropy occurs in the first protective resin (6) before heat treatment, and the viscosity increases apparently. do. For this reason, it becomes difficult to properly pour the first protective resin (6) between the flip chip (4) and the circuit board (3). As described above, in this example, the granular shape of the first protective resin (6) was designed to obtain the linear expansion coefficient and film elastic modulus desirable as a filler for stress relaxation, and to have good fluidity during formation. The mixing ratio and average particle size of silica are specified.
【００１０】0010
【変形例】本発明の上記の実施例は下記のように種々の
変更が可能である。
（１） 熱処理前における第１及び第２の保護樹脂（
６）（７）の揮発性溶剤の混合比は同じでもよいが、回
路基板（３）の全面を被覆する樹脂として、又第１の保
護樹脂（６）を被覆する樹脂としては気泡の分布が少な
い（気孔率が小さい）方が望ましい。したがって、第２
の保護樹脂（７）の揮発性溶剤の含有率は第１の保護樹
脂（６）のそれよりも３重量％以上小さくするのが良い
。
（２） 熱処理前における第１の保護樹脂（６）の揮
発性溶剤の混合比は、第１の保護樹脂（６）をフリップ
チップ（４）と回路基板（３）との間に流し込み易いよ
うに、揮発性溶剤を全重量に対して２５重量％以上、望
ましくは３０重量％以上とするのが良い。ただし、フリ
ップチップ（４）と第１の保護樹脂（６）との間に隙間
が生じないように又気泡の分布が保護樹脂として許容で
きる範囲に収まるように４０重量％以下、望ましくは３
５重量％以下とするのが良い。
（３） 第２の保護樹脂（７）の粒状シリカの混合比
は第１の保護樹脂（６）のそれと同じにしても良いが、
第１の保護樹脂（６）−第２の保護樹脂（７）−樹脂封
止体（９）の系においてその線膨張係数が段階的に増加
する構造とする方が、熱応力の緩和、特にリード細線（
１２）の第２の保護樹脂（７）と樹脂封止体（９）との
界面における破断防止上望ましい。したがって、第２の
保護樹脂（７）の粒状シリカの混合比は第１の保護樹脂
（６）のそれよりも２重量％以上、望ましくは５重量％
以上小さくするのが望ましい。なお、混合比を同じとす
る場合には含有されるシリカの粒径を第１の保護樹脂（
６）のそれよりも平均で５μｍ以上、望ましくは１０μ
ｍ以上大きくして、これによって線膨張係数を増大させ
てもよい。
（４） 第１の保護樹脂（６）のシリカの混合比は、
上記のように線膨張係数を考慮すると８５．５〜９６．
５重量％とするのが良い。なお、この範囲においてシリ
カの混合比が小さいと線膨張係数が増加し、シリカの混
合比が大きいと皮膜弾性率が低下するので、更に望まし
い範囲を規定すれば８７．５〜９２．５重量％となる。
（５） 第１の保護樹脂（６）のシリカの平均粒径は
、線膨張係数と皮膜弾性率とチキソ性の３点を鑑みて５
μｍ〜２５μｍ望ましくは７μｍ〜２０μｍとするのが
良い。
（６） ファインポリマレジンとしてポリアミド系の
樹脂を使用しても良い。
（７） 第１の保護樹脂（６）が回路基板（３）の全
面を被覆するようにしても良い。
（８） 突起状電極（１１）を配線導体（１０）にの
み設けても良いし、フリップチップ（４）と配線導体（
４）の両方に設けてもよい。
（９） 突起状電極（１１）と配線導体（１０）又は
フリップチップ（４）の電極との接続が第１の保護樹脂
（６）によって固定されることによって行われる構造と
しても良い。
［００１１］[Modifications] The above-described embodiment of the present invention can be modified in various ways as described below. (1) First and second protective resins before heat treatment (
6) The mixing ratio of the volatile solvents in (7) may be the same, but the distribution of air bubbles may be different for the resin that covers the entire surface of the circuit board (3) and the resin that covers the first protective resin (6). The smaller the porosity, the smaller the porosity. Therefore, the second
The volatile solvent content of the protective resin (7) is preferably 3% by weight or more lower than that of the first protective resin (6). (2) The mixing ratio of the volatile solvent of the first protective resin (6) before heat treatment is such that the first protective resin (6) can be easily poured between the flip chip (4) and the circuit board (3). In addition, it is preferable that the amount of volatile solvent be 25% by weight or more, preferably 30% by weight or more based on the total weight. However, in order to prevent a gap from forming between the flip chip (4) and the first protective resin (6) and to keep the distribution of air bubbles within an acceptable range for the protective resin, the amount should be 40% by weight or less, preferably 3% by weight.
The content is preferably 5% by weight or less. (3) The mixing ratio of granular silica in the second protective resin (7) may be the same as that in the first protective resin (6);
In the system of the first protective resin (6) - second protective resin (7) - resin encapsulant (9), it is better to have a structure in which the coefficient of linear expansion increases stepwise, to alleviate thermal stress, especially Thin lead wire (
12) is desirable in order to prevent breakage at the interface between the second protective resin (7) and the resin sealing body (9). Therefore, the mixing ratio of granular silica in the second protective resin (7) is 2% by weight or more, preferably 5% by weight, compared to that in the first protective resin (6).
It is desirable to make it smaller than that. In addition, when the mixing ratio is the same, the particle size of the silica contained in the first protective resin (
6) on average 5 μm or more, preferably 10 μm
The linear expansion coefficient may be increased by increasing the linear expansion coefficient by m or more. (4) The mixing ratio of silica in the first protective resin (6) is:
Considering the linear expansion coefficient as mentioned above, it is 85.5 to 96.
The content is preferably 5% by weight. Note that in this range, if the silica mixing ratio is small, the linear expansion coefficient increases, and if the silica mixing ratio is large, the film elastic modulus decreases, so if a more desirable range is defined, it is 87.5 to 92.5% by weight. becomes. (5) The average particle size of the silica in the first protective resin (6) is 5, taking into account the linear expansion coefficient, film elastic modulus, and thixotropy
The thickness is preferably 7 μm to 20 μm, preferably 7 μm to 20 μm. (6) Polyamide resin may be used as the fine polymer resin. (7) The first protective resin (6) may cover the entire surface of the circuit board (3). (8) The protruding electrode (11) may be provided only on the wiring conductor (10), or may be provided on the flip chip (4) and the wiring conductor (
4) may be provided in both. (9) A structure may be adopted in which the connection between the protruding electrode (11) and the wiring conductor (10) or the electrode of the flip chip (4) is fixed by the first protective resin (6). [0011]
【発明の効果】以上のように、本発明によれば、信頼性
の高い回路基板装置を容易に提供することができる。As described above, according to the present invention, a highly reliable circuit board device can be easily provided.
【図１】本発明の一実施例を示す電力用ハイブリッドＩ
Ｃの断面図[Fig. 1] Electric power hybrid I showing an embodiment of the present invention
Cross-sectional view of C
【図２】図１の要部を示す拡大断面図[Figure 2] Enlarged sectional view showing the main parts of Figure 1
【図３】シリカフィラーの含有率と皮膜弾性率及び線膨
張係数との関係を示すグラフ[Figure 3] Graph showing the relationship between silica filler content, film elastic modulus, and linear expansion coefficient
（３） 、 、回路基板、 （４） 、 、フリップチ
ップ（半導体素子）、 （６） 、 、第１の保護樹脂
、 （７） 、 、第２の保護樹脂、 （８） 、 、
第３の保護樹脂、 （９） 、 、樹脂封止体、 （１
０） 、 、配線導体、 （１１） 、 、半田バンプ
（突起状電極）(3), ,Circuit board, (4), ,Flip chip (semiconductor element), (6), ,First protective resin, (7), ,Second protective resin, (8), ,
Third protective resin, (9), Resin sealing body, (1
0) , , Wiring conductor, (11) , Solder bump (protruding electrode)
【図１】[Figure 1]
【図２】[Figure 2]
【図３】[Figure 3]
Claims (8)
成された回路基板とを有し、前記半導体素子の一方の主
面と前記回路基板の一方の主面とが離間して対向するよ
うに配置され、前記半導体素子が前記配線導体に突起状
電極を介して電気的に接続されている回路基板装置にお
いて、前記回路基板の一方の主面と前記半導体素子の一
方の主面とが対向する領域に粒状シリカとポリイミド系
又はポリアミド系の樹脂を含有する保護樹脂が充填され
ており、前記保護樹脂の線膨張係数は前記回路基板の線
膨張係数より小さく前記半導体素子の線膨張係数よりも
大きいことを特徴とする回路基板装置。1. A semiconductor device comprising a semiconductor element and a circuit board having a wiring conductor formed on one main surface, one main surface of the semiconductor element and one main surface of the circuit board facing each other with a distance between them. In a circuit board device in which the semiconductor element is electrically connected to the wiring conductor via a protruding electrode, one main surface of the circuit board and one main surface of the semiconductor element A protective resin containing granular silica and a polyimide-based or polyamide-based resin is filled in a region facing each other, and the linear expansion coefficient of the protective resin is smaller than that of the circuit board, and the linear expansion coefficient of the semiconductor element is smaller than that of the circuit board. A circuit board device characterized by being larger than.
μｍである「請求項１」に記載の回路基板装置。[Claim 2] The average particle diameter of the granular silica is 5 μm to 25 μm.
The circuit board device according to claim 1, which is μm.
５重量％の前記粒状シリカを特徴する請求項１」又は「
請求項２」に記載の回路基板装置。3. The protective resin has a content of 85.5% to 96% by weight.
5% by weight of said particulate silica" or "
The circuit board device according to claim 2.
成された回路基板とを有し、前記半導体素子の一方の主
面と前記回路基板の一方の主面とが離間して対向するよ
うに配置され、前記半導体素子が前記配線導体に突起状
電極を介して電気的に接続されている回路基板装置にお
いて、前記回路基板の一方の主面と前記半導体素子の一
方の主面とが対向する領域に粒状シリカとポリイミド系
又はポリアミド系の樹脂を含有する第１の保護樹脂が充
填されており、前記半導体素子及び前記第１の保護樹脂
は第２の保護樹脂で被覆されており、更に前記第２の保
護樹脂は樹脂封止体で被覆されており、前記第１の保護
樹脂の線膨張係数は前記回路基板の線膨張係数より小さ
く前記半導体素子の線膨張係数よりも大きく、前記第２
の保護樹脂の線膨張係数は前記第１の保護樹脂の線膨張
係数よりも大きく、前記樹脂封止体の線膨張係数よりも
小さいことを特徴とする回路基板装置。4. A semiconductor device comprising a semiconductor element and a circuit board having a wiring conductor formed on one main surface, one main surface of the semiconductor element and one main surface of the circuit board facing each other with a distance between them. In a circuit board device in which the semiconductor element is electrically connected to the wiring conductor via a protruding electrode, one main surface of the circuit board and one main surface of the semiconductor element A first protective resin containing granular silica and a polyimide-based or polyamide-based resin is filled in a region facing each other, and the semiconductor element and the first protective resin are covered with a second protective resin. Further, the second protective resin is covered with a resin sealant, and the first protective resin has a linear expansion coefficient smaller than that of the circuit board and larger than that of the semiconductor element, Said second
A circuit board device characterized in that a linear expansion coefficient of the protective resin is larger than a linear expansion coefficient of the first protective resin and smaller than a linear expansion coefficient of the resin encapsulant.
ミド系又はポリアミド系の樹脂を特徴する請求項４」に
記載の回路基板装置。5. The circuit board device according to claim 4, wherein the second protective resin comprises granular silica and a polyimide-based or polyamide-based resin.
は多孔質であり、前記第２の保護樹脂の気孔率は前記第
１の保護樹脂の気孔率よりも小さい「請求項４」又は「
請求項５」に記載の回路基板装置。6. The first protective resin and the second protective resin are porous, and the porosity of the second protective resin is smaller than the porosity of the first protective resin. ” or “
The circuit board device according to claim 5.
シリカの平均粒径は５μｍ〜２５μｍで、前記第２の保
護樹脂に含有されている粒状シリカの平均粒径は前記第
１の保護樹脂に含有されている粒状シリカの平均粒径よ
りも５μｍ以上大きい「請求項５」又は「請求項６」に
記載の回路基板装置。7. The average particle size of the granular silica contained in the first protective resin is 5 μm to 25 μm, and the average particle size of the granular silica contained in the second protective resin is 5 μm to 25 μm. The circuit board device according to claim 5 or 6, wherein the circuit board device is 5 μm or more larger than the average particle diameter of the granular silica contained in the protective resin.
８５．５重量％〜９６．５重量％含有しており、前記第
２の保護樹脂は第１の保護樹脂よりも２重量％以上少な
い粒状シリカを含有している「請求項５」〜「請求項７
」のいずれかに記載の回路基板装置。8. The first protective resin contains 85.5% to 96.5% by weight of silica having the particle size, and the second protective resin contains 2% by weight more silica than the first protective resin. "Claim 5" to "Claim 7" containing granular silica less than % or more
The circuit board device according to any one of the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3037742A JP2869964B2 (en) | 1991-02-08 | 1991-02-08 | Circuit board device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3037742A JP2869964B2 (en) | 1991-02-08 | 1991-02-08 | Circuit board device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01338246 Division | 1989-12-28 | 1989-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04211150A true JPH04211150A (en) | 1992-08-03 |
| JP2869964B2 JP2869964B2 (en) | 1999-03-10 |
Family
ID=12505938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3037742A Expired - Fee Related JP2869964B2 (en) | 1991-02-08 | 1991-02-08 | Circuit board device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2869964B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878611A (en) * | 1994-08-31 | 1996-03-22 | Nec Corp | Semiconductor device |
| EP1043771A2 (en) * | 1999-04-06 | 2000-10-11 | Hitachi, Ltd. | Resin sealed electronic device and method of fabricating the same and ignition coil for internal combustion engine using the same |
| JP2011171436A (en) * | 2010-02-17 | 2011-09-01 | Tdk Corp | Electronic component built-in module and manufacturing method of the same |
| JP2012160572A (en) * | 2011-01-31 | 2012-08-23 | Tdk Corp | Electronic circuit module component and manufacturing method of the same |
| JP2012160707A (en) * | 2011-01-28 | 2012-08-23 | Samsung Electronics Co Ltd | Multilayer semiconductor chip, semiconductor device, and manufacturing method for these |
| CN103383927A (en) * | 2012-05-03 | 2013-11-06 | 三星电子株式会社 | Semiconductor encapsulation and forming method thereof |
| JP2014187355A (en) * | 2013-03-22 | 2014-10-02 | Toyota Motor Engineering & Manufacturing North America Inc | Thermal energy guiding systems including anisotropic thermal guiding coatings and methods for fabricating the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081279A (en) * | 2007-09-26 | 2009-04-16 | Sanyo Electric Co Ltd | Hybrid integrated circuit device |
-
1991
- 1991-02-08 JP JP3037742A patent/JP2869964B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878611A (en) * | 1994-08-31 | 1996-03-22 | Nec Corp | Semiconductor device |
| EP1043771A2 (en) * | 1999-04-06 | 2000-10-11 | Hitachi, Ltd. | Resin sealed electronic device and method of fabricating the same and ignition coil for internal combustion engine using the same |
| EP1043771A3 (en) * | 1999-04-06 | 2002-08-14 | Hitachi, Ltd. | Resin sealed electronic device and method of fabricating the same and ignition coil for internal combustion engine using the same |
| JP2011171436A (en) * | 2010-02-17 | 2011-09-01 | Tdk Corp | Electronic component built-in module and manufacturing method of the same |
| JP2012160707A (en) * | 2011-01-28 | 2012-08-23 | Samsung Electronics Co Ltd | Multilayer semiconductor chip, semiconductor device, and manufacturing method for these |
| JP2012160572A (en) * | 2011-01-31 | 2012-08-23 | Tdk Corp | Electronic circuit module component and manufacturing method of the same |
| CN103383927A (en) * | 2012-05-03 | 2013-11-06 | 三星电子株式会社 | Semiconductor encapsulation and forming method thereof |
| JP2014187355A (en) * | 2013-03-22 | 2014-10-02 | Toyota Motor Engineering & Manufacturing North America Inc | Thermal energy guiding systems including anisotropic thermal guiding coatings and methods for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2869964B2 (en) | 1999-03-10 |
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