JPH04199559A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04199559A
JPH04199559A JP2335413A JP33541390A JPH04199559A JP H04199559 A JPH04199559 A JP H04199559A JP 2335413 A JP2335413 A JP 2335413A JP 33541390 A JP33541390 A JP 33541390A JP H04199559 A JPH04199559 A JP H04199559A
Authority
JP
Japan
Prior art keywords
lead
island
recess
width
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2335413A
Other languages
Japanese (ja)
Inventor
Chihomi Kamimura
上村　千穂美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2335413A priority Critical patent/JPH04199559A/en
Publication of JPH04199559A publication Critical patent/JPH04199559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a solder flow stop without lowering the strength of a suspension lead by widening the width of the vicinity of the indent of the suspension lead, which becomes thin accompanying a multipin configuration, etc., so that the indent may be provided. CONSTITUTION:This is equipped with a semiconductor element 1, an island 2 of a lead frame, a plurality of electrodes 3 provided at the semiconductor element 1, a lead 4 of the lead frame, a wire 5 for connecting the electrode 3 with the lead 4, a solder material 7, a recess 8 provided at the specified part of the lead 4. And for the lead connected with the island 2, the width of the part adjacent to the island 2 is made wider by a specified value than the width of the lead 4, and a recess 8 in which solder flows is constituted in the wide part. Hereby, a suspension lead equipped with a solder flow stop, which has strength even in a multipin frame, can be provided, and a semiconductor device excellent in work efficiency can be gotten.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は樹脂封止型半導体装置に係り、特にリードフ
レームの形状に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resin-sealed semiconductor device, and particularly to the shape of a lead frame.

〔従来の技術〕[Conventional technology]

第３図は従来の半導体装置（以下半導体パッケージと略
称する）の構成を示す透視平面図、第４図は第３図の半
導体パッケージの断面図、第５図はコラ相流れ止め部の
拡大図である。図において、（］）は半導体素子、（２
）はアイラン）・、（３）は電極、（４）はリード、（
５）はワイヤ、（６）は樹脂封止部本体、（７）はロウ
材、（８）は凹部である。Fig. 3 is a perspective plan view showing the configuration of a conventional semiconductor device (hereinafter abbreviated as semiconductor package), Fig. 4 is a sectional view of the semiconductor package in Fig. 3, and Fig. 5 is an enlarged view of the colloidal phase flow stopper. It is. In the figure, (]) is a semiconductor element, (2
) is an eyelan)・, (3) is an electrode, (4) is a lead, (
5) is a wire, (6) is a resin sealing portion main body, (7) is a brazing material, and (8) is a recessed portion.

次に動作について説明する。第３図において、半導体素
子（１）はアイランド（２）上に接合され、その縁部に
多数の電極（３）を有する。リ−１”　（４＋は半導体
素子（１）の周辺に設けられ、例えば金線なとのワイヤ
（５）によって電極（３）に接続される。樹脂封止部本
体（６）は内部リード（４）、ワイヤ（５）、アイラン
ド（２）及び半導体素子（］）を樹脂封止する。Next, the operation will be explained. In FIG. 3, a semiconductor element (1) is bonded onto an island (2) and has a number of electrodes (3) on its edge. The lead (4+) is provided around the semiconductor element (1) and connected to the electrode (3) by a wire (5), such as a gold wire. 4) The wire (5), the island (2) and the semiconductor element (]) are sealed with resin.

ロウ材（７）は、半導体素子（１）をアイランド（２）
に取り付けるためのものである。ここで、吊りり一トヘ
ワイヤリングする場合、吊りリードへのロウ材（７）の
流れ込みを防止するため凹部か（８）か設けられる。The brazing material (7) connects the semiconductor element (1) to the island (2).
It is for attaching to. Here, when wiring to a hanging lead, a recess (8) is provided to prevent the brazing material (7) from flowing into the hanging lead.

この凹部（８）は、写真製版法等によって、リ−１・フ
レームの板厚の半分程度エツチングすることにより形成
されるか、多ビン化等により吊りリードの幅か小さくな
ると、第３図に示すように、凹部の周辺までエツチング
されるため、吊りリードの強度か小さくなる。このため
組立工程中に吊りリードか切断さることかある。This recess (8) can be formed by etching about half the thickness of the lead 1 frame using photolithography, or if the width of the hanging lead becomes smaller due to the use of multiple bins, etc. As shown, since the periphery of the recess is etched, the strength of the suspension lead is reduced. For this reason, the suspension lead may be cut during the assembly process.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

従来の半導体装置は以上のように構成されているので、
多ビン化のため吊りリードの幅が小さくなって半田の流
れ止めの凹部を設けることか困難で、強度か低下し、組
立工程中に吊りリードか切断することかあるなとの問題
点があった。Conventional semiconductor devices are configured as described above, so
Due to the increased number of bins, the width of the hanging leads has become smaller, making it difficult to provide recesses to prevent solder from flowing, resulting in lower strength and the problem that the hanging leads may have to be cut during the assembly process. Ta.

この発明は、上記の問題を解決するためになされたもの
で、吊りリードの強度を低下させずに半田流れ止めを設
けたリードフレームを得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a lead frame provided with a solder flow stopper without reducing the strength of the suspension lead.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体パッケージは、多ピン化等により
、細くなる吊りリード部の凹部周辺の幅を凹部か設けら
れるように広くしたものである。In the semiconductor package according to the present invention, the width around the concave portion of the hanging lead portion, which becomes thin due to the increase in pin count, is increased so that the concave portion can be provided.

〔作用〕[Effect]

この発明における半導体パッケージは、半田の流れ止め
の凹部を設ける位置周辺の吊りリード幅か広くしたので
リード幅の狭い吊りり−トに凹部を設けても充分な強度
か得られる。In the semiconductor package of the present invention, the width of the hanging leads is widened around the position where the recesses for preventing the flow of solder are provided, so that sufficient strength can be obtained even if the recesses are provided in the hanging holes with narrow lead widths.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図において、（１）は半導体素子、（２）はり一ドフレ
ームのアイランド、（３）は半導体素子（１）に設けら
れた複数個の電極、（４）はリードフレームのり一トで
、アイランド（２）と接続されている。（５）は電極（
３）とリード（４）とを接続するワイヤ、（ア）はロウ
材で、半導体素子（１）をアイランド（２）に取り付け
るために使用されている。（８）はリード（４）の所定
の部分に設けられた凹部である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a semiconductor element, (2) is an island on a beam frame, (3) is a plurality of electrodes provided on the semiconductor element (1), and (4) is a lead frame glue. (2) is connected. (5) is the electrode (
3) and the lead (4), the wire (A) is a brazing material and is used to attach the semiconductor element (1) to the island (2). (8) is a recess provided in a predetermined portion of the lead (4).

次に動作について説明する。第１図に示すものは、アイ
ランｌ’　（２１と接続されたり一ト（４）すなわち吊
りり−１・に、アイランド（２）と近接した部分の幅を
り−１”　ｆ４＋の幅よりも所定の値広く形成し、この
幅の広い部分に半田の流れ込む凹部（８）か構成されて
いるので、半導体素子（１）をアイランド（２）に取付
けるときに、流れたロウ材（７）か凹部（８）に収容さ
れる。ここて、凹部（８）を設けたリード（４）の幅は
、所定の幅に構成されているので所定の強度を備えてい
る。Next, the operation will be explained. The one shown in FIG. Since the recess (8) into which the solder flows is formed in the wide part by a predetermined width, when the semiconductor element (1) is attached to the island (2), the solder material (7) that flows out can be removed. The lead (4) is accommodated in the recess (8).The lead (4) provided with the recess (8) has a predetermined width and thus has a predetermined strength.

第２図はこの発明の他の実施例を示すものて、リード（
４）に設ける四部（８）を、アイランド（２）より所定
の距離をあけた箇所にリード（４）の幅を所定の幅に広
くして構成し、上記実施例と同様の動作を期待している
。FIG. 2 shows another embodiment of the present invention.
The fourth part (8) provided in 4) is constructed by increasing the width of the lead (4) to a predetermined width at a location spaced a predetermined distance from the island (2), and the same operation as in the above embodiment is expected. ing.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、凹部周辺のリード幅を
広くした事により、多ビンフレームにおいても強度のあ
る吊りリードか設けられるため、作業性の優れた半導体
装置か得られる効果かある。As described above, according to the present invention, by widening the lead width around the concave portion, a strong hanging lead can be provided even in a multi-bin frame, so that a semiconductor device with excellent workability can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図はこの発明の一実施例による半導体パ
ッケージのリードフレーム形状を表した斜視図、第３図
は従来の半導体パッケージの構成を示す透視平面図で、
第４図は第４図の半導体パッケージの断面図、第５図は
ロウ材流れ止め部の拡大図である。 図において、（１）は半導体素子、（２）はアイランド
、（３）は電極、（４）はリード、（５）はワイヤ、（
６）は樹脂封止部本体、（７）は半導体素子をアイラン
ドに取りつけるだめのロー材、（８）はロー材の流れ込
みを防止するための凹部である。 なお、図中、同一符号は同一、又は相当部分を示す。1 and 2 are perspective views showing the shape of a lead frame of a semiconductor package according to an embodiment of the present invention, and FIG. 3 is a perspective plan view showing the structure of a conventional semiconductor package.
FIG. 4 is a sectional view of the semiconductor package shown in FIG. 4, and FIG. 5 is an enlarged view of the brazing material flow stopper. In the figure, (1) is a semiconductor element, (2) is an island, (3) is an electrode, (4) is a lead, (5) is a wire, (
6) is the main body of the resin sealing part, (7) is a soldering material for attaching the semiconductor element to the island, and (8) is a recessed portion for preventing the soldering material from flowing in. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を搭載するアイランドとこのアイランド周辺
に配置され前記半導体素子の電極と金属細線を介して接
続される複数のリードと前記アイランドをフレーム枠に
支持する吊りリードと、その周辺部を樹脂封止するパッ
ケージ本体（６）とを備えた半導体装置において、前記
アイランド近傍の吊りリードに凹部を設けるとともに、
前記凹部周囲の吊りリード幅を所定の範囲広くした事を
特徴とする半導体装置。An island on which a semiconductor element is mounted, a plurality of leads arranged around the island and connected to the electrodes of the semiconductor element via thin metal wires, a suspension lead that supports the island on a frame, and the peripheral portion thereof is sealed with resin. In the semiconductor device, a recess is provided in the suspension lead near the island, and a recess is provided in the suspension lead near the island;
A semiconductor device characterized in that the width of the hanging lead around the recess is widened by a predetermined range.
JP2335413A 1990-11-28 1990-11-28 Semiconductor device Pending JPH04199559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2335413A JPH04199559A (en) 1990-11-28 1990-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2335413A JPH04199559A (en) 1990-11-28 1990-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04199559A true JPH04199559A (en) 1992-07-20

Family

ID=18288273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2335413A Pending JPH04199559A (en) 1990-11-28 1990-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04199559A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0650360U (en) * 1992-03-12 1994-07-08 株式会社三井ハイテック Lead frame for semiconductor device
JPH0738044A (en) * 1993-07-16 1995-02-07 Hitachi Cable Ltd Lead frame for semiconductor device
EP2822031A3 (en) * 2013-06-25 2015-06-10 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0650360U (en) * 1992-03-12 1994-07-08 株式会社三井ハイテック Lead frame for semiconductor device
JPH0738044A (en) * 1993-07-16 1995-02-07 Hitachi Cable Ltd Lead frame for semiconductor device
EP2822031A3 (en) * 2013-06-25 2015-06-10 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

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