JPH03127559A - Video signal clamp circuit - Google Patents

Video signal clamp circuit

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Publication number
JPH03127559A
JPH03127559A JP1264986A JP26498689A JPH03127559A JP H03127559 A JPH03127559 A JP H03127559A JP 1264986 A JP1264986 A JP 1264986A JP 26498689 A JP26498689 A JP 26498689A JP H03127559 A JPH03127559 A JP H03127559A
Authority
JP
Japan
Prior art keywords
video signal
signal
operational amplifier
transistor
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1264986A
Other languages
Japanese (ja)
Other versions
JP2530229B2 (en
Inventor
Masahiko Tanizawa
正彦 谷澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP1264986A priority Critical patent/JP2530229B2/en
Publication of JPH03127559A publication Critical patent/JPH03127559A/en
Application granted granted Critical
Publication of JP2530229B2 publication Critical patent/JP2530229B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To eliminate distortion of a composite video signal to be outputted by providing a feedback circuit using an operational amplifier. CONSTITUTION:When a composite video signal is inputted to a video signal input terminal, a charge stored in a capacitor C1 except for a period of a horizontal synchronizing signal TH is discharged by a base impedance of a transistor(TR) 2. Since a base level of the TR 2 is lower than a reference voltage Vc at a terminal (a) for the horizontal synchronizing signal period TH, a feedback circuit employing an operational amplifier 1 is active, a diode D is conductive and the base level of the TR 2 is brought into the same level as a reference level Vc. When the horizontal synchronizing signal period TH is finished, the diode D is turned off. Thus, distortion is eliminated from both outputted horizontal synchronizing signal and vertical synchronizing signal.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は通信衛星を利用する映像信号伝送において、
受信側に設置され、受信した複合映像信号の同期信号先
端電位を一定値に固定することにより、複合映像信号に
重畳するエネルギー拡散信号である三角波を除去する映
像信号クランプ回路に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to video signal transmission using communication satellites.
The present invention relates to a video signal clamp circuit that is installed on the receiving side and removes a triangular wave, which is an energy diffusion signal superimposed on the composite video signal, by fixing the synchronization signal tip potential of the received composite video signal to a constant value.

[従来の技術] 通信衛星を利用する映像信号伝送においては、地上固定
業務との干渉を避けるため送信側で映像信号のフレーム
周期と同期した三角波を、複合映像信号に重畳し、この
重畳した信号によって周波数変調を行いエネルギー拡散
を行っている。そして受信側では、周波数検波を行い、
この周波数検波によって得た入力信号から、エネルギー
拡散信号である三角波を除去している。
[Prior art] In video signal transmission using communication satellites, in order to avoid interference with terrestrial fixed services, a triangular wave synchronized with the frame period of the video signal is superimposed on a composite video signal on the transmitting side, and this superimposed signal is Frequency modulation is performed by using the method to spread energy. Then, on the receiving side, frequency detection is performed,
The triangular wave, which is an energy spread signal, is removed from the input signal obtained by this frequency detection.

そして、この三角波を除去するためには、映像信号クラ
ンプ回路を用いて複合映像信号に含まれる同期信号の先
端電位を一定値に固定する。
In order to remove this triangular wave, a video signal clamp circuit is used to fix the tip potential of the synchronization signal included in the composite video signal to a constant value.

第2図は従来の映像信号クランプ回路の構成の一例を示
す接続図で、図においてTRI、TR2はそれぞれトラ
ンジスタで、TRI、TR2はエミッタフォロワ回路を
構成する。C1,C2はそれぞれコンデンサ、Dはダイ
オードである。
FIG. 2 is a connection diagram showing an example of the configuration of a conventional video signal clamp circuit. In the figure, TRI and TR2 are transistors, and TRI and TR2 constitute an emitter follower circuit. C1 and C2 are each a capacitor, and D is a diode.

第2図に示す映像信号入力端へ、第3図(A)に示すよ
うな複合映像信号が入力されると、T□で示す水平同期
信号の間取外においては、コンデンサC1に蓄積された
電荷はトランジスタTR2のベースインピーダンスによ
って放電され、これによって低周波成分が除去される。
When a composite video signal as shown in FIG. 3 (A) is input to the video signal input terminal shown in FIG. The charges are discharged by the base impedance of transistor TR2, thereby removing low frequency components.

またTHに示す水平同期信号の間は、ダイオードDがO
NL、コンデンサC1に充電電流iが流れ、基準電位を
V。1ダイオードDの順方向電圧をVFとした場合、ト
ランジスタTR2のベース電位はVC−VFとなり、同
期信号先端電位をVC−V、に固定する。エネルギー拡
散信号である三角波が第3図(A)の波形に重畳してい
る場合でも、この三角波に含まれる低周波成分はコンデ
ンサC1によって除去される。そして同期信号先端電位
を同一電位に固定することにより、映像信号振幅への三
角波の影響を除去することができる。
Also, during the horizontal synchronization signal indicated by TH, the diode D is OFF.
NL, a charging current i flows through the capacitor C1, and the reference potential becomes V. When the forward voltage of one diode D is VF, the base potential of the transistor TR2 becomes VC-VF, and the synchronizing signal tip potential is fixed at VC-V. Even when a triangular wave, which is an energy diffusion signal, is superimposed on the waveform of FIG. 3(A), the low frequency component contained in this triangular wave is removed by the capacitor C1. By fixing the synchronizing signal tip potential to the same potential, the influence of the triangular wave on the video signal amplitude can be removed.

し発明が解決しようとする課題] 上記のような従来の映像信号クランプ回路は以上のよう
に構成され動作するので、コンデンサC1の充電が進む
につれて充電電流iが減少しVFの値が小さくなって行
き、水平同期信号THの初めと終わりとではトランジス
タTR2のベース定位が変化してしまい、出力端がち出
力される複合映像信号には第3図(B)に示すような歪
みが生じてしまう。
[Problems to be Solved by the Invention] Since the conventional video signal clamp circuit as described above is configured and operates as described above, as the charging of the capacitor C1 progresses, the charging current i decreases and the value of VF becomes smaller. As a result, the base localization of the transistor TR2 changes between the beginning and end of the horizontal synchronizing signal TH, and distortion as shown in FIG. 3(B) occurs in the composite video signal output from the output terminal.

また等化パルスおよび垂直同期パルスからなる垂直同期
信号は、映像信号輝度成分が無い上に、垂直同期パルス
の部分ではダイオードDがoNしている時間が長く、し
たがって等化パルスの部分に較ベコンデンサC1への充
電電流iが少なく、VFの値も小さくなり、第4図に示
すような歪みが生じてしまう等の問題点があった。
In addition, the vertical synchronization signal consisting of the equalization pulse and the vertical synchronization pulse has no video signal luminance component, and the time during which the diode D is on is long in the vertical synchronization pulse part, so compared to the equalization pulse part. There were problems such as a small charging current i to the capacitor C1 and a small value of VF, resulting in distortion as shown in FIG.

この発明はかかる課題を解決するためになされたもので
、出力される複合映像信号に歪みを生じさせない映像信
号クランプ回路を得ることを目的としている。
The present invention has been made to solve this problem, and an object of the present invention is to provide a video signal clamp circuit that does not cause distortion in the output composite video signal.

[課題を解決するための手段] この発明にかかる映像信号クランプ回路は、オペレーシ
ョナル・アンプを用いてVFの変化の影響をフィードバ
ックにより減少させることとしたものである。
[Means for Solving the Problems] A video signal clamp circuit according to the present invention uses an operational amplifier to reduce the influence of changes in VF through feedback.

[作用] この発明においては、オペレーショナル・アンプを用い
てVPの変化の影響をフィードバックにより減少させる
こととしたので、ダイオードDがONL順方向電圧■P
が変1ヒする場合でも、トランジスタTR2のベース電
位を■cに保つことが可能となる。
[Function] In this invention, since an operational amplifier is used to reduce the influence of changes in VP through feedback, the diode D reduces the ONL forward voltage ■P
Even if the voltage changes, it is possible to maintain the base potential of the transistor TR2 at c.

[実施例1 以下、この発明の実施例を図面について説明する。第1
図はこの発明の一実施例を示す接続図で、図において第
2図と同一符号は同−又は相当部分を示し、(1)はオ
ペレーショナル・アンプ(以下、オペアンプと言う) 
、(a)、(b)、(C)はそれぞれ端子点を示す。
[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a connection diagram showing one embodiment of the present invention. In the figure, the same symbols as in Figure 2 indicate the same or corresponding parts, and (1) is an operational amplifier (hereinafter referred to as an operational amplifier).
, (a), (b), and (C) indicate terminal points, respectively.

第1図に示すようなオペアンプ(1)を用いたフィード
バック回路の動作は良く知られているが、ここで簡単に
説明すると、端子(b)の方が端子(a)より電位が高
い場合には端子(c)の電位は負の飽和電圧になり、ダ
イオードDをOFFする。また端子(a)の方が端子(
b)より電位が高い場合には、端子(a)と端子(b)
とが同電位になるまで、端子(C)の電圧を上昇させる
ように動作する。
The operation of a feedback circuit using an operational amplifier (1) as shown in Figure 1 is well known, but to briefly explain it here, when the potential of the terminal (b) is higher than that of the terminal (a), The potential at terminal (c) becomes a negative saturation voltage, turning off diode D. Also, terminal (a) is better than terminal (
b) If the potential is higher than terminal (a) and terminal (b)
It operates to increase the voltage at terminal (C) until they reach the same potential.

次に、この実施例の動作について説明する。映像信号入
力端に第3図(A、 )に示すような複合映像信号が入
力されると、従来の回路と同様にTHで示す水平同期信
号の間取外においては、コンデンサC1に蓄積された電
荷はトランジスタTR2のベースインピーダンスによっ
て放電される。
Next, the operation of this embodiment will be explained. When a composite video signal as shown in Figure 3 (A, ) is input to the video signal input terminal, when the horizontal synchronizing signal shown as TH is removed, similar to the conventional circuit, the signal is accumulated in the capacitor C1. The charge is discharged by the base impedance of transistor TR2.

TIに示す水平同期信号に入ると、TR2のべ−スミ位
くすなわち端子(b)の電位)は端子(a>の基準電位
VCより低くなるため、オペアンプ(1)を用いたフィ
ードバック回路が動作し、ダイオードDがONして、T
R2のベース電位を端子(a)の基準電位Vcと同じ電
位にする。そしてT!1に示す水平同期信号が終了する
とダイオードDはOFFする。
When the horizontal synchronization signal indicated by TI is entered, the base level of TR2 (that is, the potential at terminal (b)) becomes lower than the reference potential VC at terminal (a>), so the feedback circuit using the operational amplifier (1) operates. Then, diode D turns on and T
The base potential of R2 is set to the same potential as the reference potential Vc of terminal (a). And T! When the horizontal synchronization signal shown in 1 ends, diode D is turned off.

以上のような動作により、THに示す水平同期信号にお
いては、TR2のベース電位をダイオードDの順方向電
圧V、とは関係なく基準電位■。
Due to the above operation, in the horizontal synchronization signal indicated by TH, the base potential of TR2 is set to the reference potential ■ regardless of the forward voltage V of the diode D.

に保つことができる。can be kept.

また垂直同期信号においても、同様にしてダイオードD
の順方向電圧VFの影響を回避することができ、出力さ
れる水平同期信号、垂直同期信号ともに歪みを除去する
ことができる。
Similarly, in the vertical synchronization signal, the diode D
The influence of the forward voltage VF can be avoided, and distortion can be removed from both the output horizontal synchronization signal and vertical synchronization signal.

[発明の効果] この発明は以上説明したように、オペレーショナル・ア
ンプを用いたフィードバック回路を設けることにより、
出力される複合映像信号の歪みを除去することができる
という効果がある。
[Effects of the Invention] As explained above, the present invention provides a feedback circuit using an operational amplifier, thereby achieving the following effects.
This has the effect that distortion of the output composite video signal can be removed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す接続図、第2図は従
来の回路の構成を示す接続図、第3図は複合映像信号の
波形図、第4図は垂直同期信号の波形を示す図。 1・・・オペアンプ、TRI、TR2・・・1−ランジ
スタ、C1,C2・・・コンデンサ、D・ダイオード。 なお、各図中同一符号は同一または相当部分を示すもの
とする。
Fig. 1 is a connection diagram showing an embodiment of the present invention, Fig. 2 is a connection diagram showing the configuration of a conventional circuit, Fig. 3 is a waveform diagram of a composite video signal, and Fig. 4 is a waveform diagram of a vertical synchronization signal. Figure shown. 1... operational amplifier, TRI, TR2... 1-transistor, C1, C2... capacitor, D diode. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 映像信号のフレーム周期と同期した三角波を複合映像信
号に重畳して周波数変調を行い、エネルギーを拡散して
送出した信号を受信側で周波数検波し、この周波数検波
によって得た入力信号中の同期信号先端電位を一定値に
固定して上記三角波を除去する映像信号クランプ回路に
おいて、上記入力信号が結合コンデンサを介してそのベ
ースに加えられるエミッタフォロワ回路用トランジスタ
、 このエミッタフォロワ回路用トランジスタのベースが反
転入力端子に接続されるオペレーショナル・アンプ、 このオペレーショナル・アンプの非反転入力端子に接続
される基準電位、上記オペレーショナル・アンプの出力
端子にそのアノードが接続され上記エミッタフォロワ回
路用トランジスタのベースにそのカソードが接続される
ダイオード、 を備えたことを特徴とする映像信号クランプ回路。
[Claims] Frequency modulation is performed by superimposing a triangular wave synchronized with the frame period of the video signal on the composite video signal, the energy is spread, and the transmitted signal is frequency-detected on the receiving side, and the signal obtained by this frequency detection is A transistor for an emitter follower circuit to which the input signal is applied to its base via a coupling capacitor in a video signal clamp circuit that removes the triangular wave by fixing a synchronization signal tip potential in an input signal to a constant value; an operational amplifier whose base is connected to the inverting input terminal of the transistor for the emitter follower circuit, a reference potential connected to the non-inverting input terminal of this operational amplifier, and an anode of which is connected to the output terminal of the operational amplifier for the emitter follower circuit. A video signal clamp circuit comprising: a diode whose cathode is connected to the base of a transistor.
JP1264986A 1989-10-13 1989-10-13 Video signal clamp circuit Expired - Fee Related JP2530229B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1264986A JP2530229B2 (en) 1989-10-13 1989-10-13 Video signal clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1264986A JP2530229B2 (en) 1989-10-13 1989-10-13 Video signal clamp circuit

Publications (2)

Publication Number Publication Date
JPH03127559A true JPH03127559A (en) 1991-05-30
JP2530229B2 JP2530229B2 (en) 1996-09-04

Family

ID=17410979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1264986A Expired - Fee Related JP2530229B2 (en) 1989-10-13 1989-10-13 Video signal clamp circuit

Country Status (1)

Country Link
JP (1) JP2530229B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229371B1 (en) 1998-03-18 2001-05-08 Nec Corporation Clamp circuit
JP2008054933A (en) * 2006-08-31 2008-03-13 Shizuoka Prefecture Work supporting apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6229371B1 (en) 1998-03-18 2001-05-08 Nec Corporation Clamp circuit
JP2008054933A (en) * 2006-08-31 2008-03-13 Shizuoka Prefecture Work supporting apparatus

Also Published As

Publication number Publication date
JP2530229B2 (en) 1996-09-04

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