JPH04196255A - Semiconductor chip carrier - Google Patents
Semiconductor chip carrierInfo
- Publication number
- JPH04196255A JPH04196255A JP2326754A JP32675490A JPH04196255A JP H04196255 A JPH04196255 A JP H04196255A JP 2326754 A JP2326754 A JP 2326754A JP 32675490 A JP32675490 A JP 32675490A JP H04196255 A JPH04196255 A JP H04196255A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- insulating substrate
- heat dissipation
- semiconductor chip
- metal plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000017525 heat dissipation Effects 0.000 claims description 50
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000011148 porous material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
本発明は、熱放散型の半導体チップキャリアに関するも
のである。The present invention relates to a heat-dissipating semiconductor chip carrier.
半導体の高密度化や高出力化などに伴って、半導体チッ
プからの発熱が高くなっており、半導体チップを実装す
る半導体チップキャリアとして、半導体チップの発熱を
放熱することができるものが要求されている。
このために、基体となる絶縁基板内に金属板を埋め込ん
で設け、半導体チップから発生する熱をこの金属板に吸
熱させ、そして金属板から放熱させるようにした熱放散
型の半導体チップキャリアが各種提供されている。As semiconductors become more dense and output, the amount of heat generated from semiconductor chips is increasing, and there is a need for semiconductor chip carriers that can radiate the heat generated by semiconductor chips. There is. To this end, there are various heat dissipation type semiconductor chip carriers in which a metal plate is embedded in an insulating substrate that serves as a base, and the heat generated from the semiconductor chip is absorbed by the metal plate and then radiated from the metal plate. provided.
しかし絶縁基板内に金属板を埋め込んで形成される半導
体チップキャリアにあって、金属板は絶縁基板内に設け
られているために金属板から熱を効率良く放散させるこ
とが困難であるという問題があった。
本発明は上記の点に鑑みて為されたものであり、放熱を
効率良くおこなわせることができる半導体チップキャリ
アを提供することを目的とするものである。However, semiconductor chip carriers that are formed by embedding a metal plate within an insulating substrate have a problem in that it is difficult to efficiently dissipate heat from the metal plate because the metal plate is provided within the insulating substrate. there were. The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor chip carrier that can efficiently dissipate heat.
本発明に係る半導体チップキャリアは、絶縁基板１内に
金属板２を埋設し、絶縁基板１に金属板２が底面となる
キャビティ凹所３を設けてこのキャビティ凹所３に半導
体チップ４を実装し、絶縁基板１に表面から金属板２に
至る放熱四部５を穿設し、放熱凹部５の内周に伝熱層６
を形成すると共に絶縁基板１の表面に伝熱層６と連続す
る放熱層７を形成して成ることを特徴とするものである
The semiconductor chip carrier according to the present invention includes a metal plate 2 buried in an insulating substrate 1, a cavity recess 3 whose bottom surface is the metal plate 2, and a semiconductor chip 4 mounted in the cavity recess 3. Four heat dissipating parts 5 are formed in the insulating substrate 1 from the surface to the metal plate 2, and a heat transfer layer 6 is provided on the inner periphery of the heat dissipating recess 5.
It is characterized by forming a heat dissipation layer 7 continuous with the heat transfer layer 6 on the surface of the insulating substrate 1.
本発明にあっては、絶縁基板１に表面から金属板２に至
る放熱凹部５を穿設し、放熱凹部５の内周に伝熱層６を
形成すると共に絶縁基板１の表面に伝熱層６と連続する
放熱層７を形成するようにしているために、半導体チッ
プ４から金属板２に吸収された熱は放熱凹部５の伝熱層
６から絶縁基板１の表面の放熱層７に伝導され、放熱層
７から放熱される。In the present invention, a heat dissipation recess 5 is formed in the insulating substrate 1 from the surface to the metal plate 2, and a heat transfer layer 6 is formed on the inner periphery of the heat dissipation recess 5. Since the heat dissipation layer 7 is formed continuous with the heat dissipation layer 6, the heat absorbed from the semiconductor chip 4 into the metal plate 2 is conducted from the heat transfer layer 6 of the heat dissipation recess 5 to the heat dissipation layer 7 on the surface of the insulating substrate 1. The heat is dissipated from the heat dissipation layer 7.
以下本発明を実施例によって詳述する。
絶縁基板１は、銅箔を積層したエポキシ樹脂積層板など
の銅張り積層板を加工して得られるプリント配線板等に
よって作成されるものであり、第１図（ａ）に示すよう
に絶縁基板１内にはアルミニウムや銅など熱伝導性の良
好な金属板２が埋設しである。この金属板２は絶縁基板
１を構成する積層板を成形する際に同時に埋入させるこ
とができる。この絶縁基板１の下面には金属板２の面積
よりも小さい面積でキャビティ凹所３が設けてあり、キ
ャビティ凹所３の底面は金属板２によって形成されるよ
うにしである。また絶縁基板１の下面にはキャビティ凹
所３を中心に放射状に複数本の回路く図示省略）が銅箔
のエツチング加工などで作成しである。ＩＣチップなど
半導体チップ４はキャビティ凹所３内において金属板２
の表面に実装されるものであり、半導体チップ４の外部
接続端子部と回路の一端部との間に金線などのワイヤー
１１をボンディングして半導体チップ４を回路に接続し
である。絶縁基板１にはさらに複数本の端子１２．１２
・・・がその下面から突出するように基部を絶縁基板１
に埋入して取り付けてあって、各端子１２は回路の他端
部に接続してあり、半導体チップ４は回路を介して端子
１２に接続されるようにしである。
一方、絶縁基板１の上面にはドリル加工や座ぐり加工な
どで細孔形状に放熱凹部５，５・・・が穿設しである。
各放熱凹部５，５・・・は下端が金属板２に至るように
形成されるものであり、第１図（ｂ）に示すように縦横
に配列して多数段けである。放熱凹部５は縦断面形状を
第２図（ａ）のように矩形にしたり、第２図（ｂ Ｈｃ
）のように楔形にしたり、第２図（ｄ）のように半円
形にしたりして形成することができる。そして各放熱凹
部５，５・・・の内周には金属板２の表面も含めて伝熱
層６が形成してあり、また絶縁基板１の放熱凹部５を設
けた側の表面に放熱層７が形成してあり、この伝熱層６
と放熱層７とは一体に連続するように形成しである。放
熱層７は絶縁基板１の表面（放熱層７を形成した面）の
面積の３０％以上の面積で形成するのが好ましい、上限
は特にないが、実用的には９５％である。これら伝熱層
６や放熱ｆｆｌ７は銅などの金属をメツキしたりして形
成することができる上記のようにして作成される半導体
チップキャリアにあって、半導体チップ４から発熱され
た熱は金属板２に吸熱され、さらに金属板２から放熱凹
部の伝熱層６を伝って絶縁基板１の表面の放熱層７に伝
熱され、放熱層７から外部に放熱されるものである。ま
た放熱層７の表面にヒートシンク１３を接合して取り付
けて、放熱層７からさらにヒートシンク１３に伝熱して
ヒートシンク］３から放熱させるようにすることも可能
である。
第３図は本発明の他の実施例を示すものであり、金属板
２を絶縁基板１のほぼ全面に埋設するようにしであるに
のものでは金属板２と端子１２との間の絶縁を確保する
ために、金属板２に貫通孔１４を設けてこの貫通孔１４
内に端子１２が通されるようにしである。
第４図（ａ Ｈｂ ）の実施例では、放熱凹部５を環状
の渭５ａとして形成してあり、放熱層７は絶縁基板１の
上面のほぼ全面に亙るように形成しである。第５図の実
施例では放熱凹部５を細長い渭５ｂとして形成しである
。また上記各実施例では、半導体チップ４を実装するキ
ャビティ凹所３を設けた側と反対側の面において絶縁基
板１に放熱凹部５を形成すると共に伝熱層６と放熱層７
とを形成するようにしたが、第６図に示すように、キャ
ビティ凹所３を設けた側の面において絶縁基板１に放熱
凹部５を形成すると共に伝熱層６と放熱層７とを形成す
るようにすることもできる。
上記各実施例における半導体チップキャリアはＰＧＡタ
イプであるが、第７図（ａ ）（ｂ ）に示す実施例や
第８図に示す実施例のようにＱＦＰタイプに形成するこ
ともできる。
さらに、放熱凹部５を第９図（ａ ）（ｂ ）のように
広い面積で形成することも可能である。しかしこの場合
には放熱四部５が広過ぎてヒートシンク１３を取り付け
ることができない場合がある。また第１０図のように、
金属板２に伝熱用金属板１５を熱伝導性接着剤１６で貼
り付けることによって放熱凹部５が形成されるようにす
ることもできる。しかしこの場合は製造コストが問題に
なる。
次ぎに具体例で放熱効果を実証する。
ニー例」２
第１図に示す半導体チップキャリアにおいて、放熱凹部
５を孔径Ｑ、６ｍｍ、個数５２個に設定して設け、放熱
層７をその面積を絶縁基板１の外形面積の３０％に設定
して設け、キャビティ凹所３に２ＳＤ−１５８０パワー
トランジスタ（ローム社製）を実装して液状エポキシ樹
脂で封止した二輿ｌ
放熱凹部５を孔径０．８ｍｍ、個数４０個に設定して設
けた他は例１と同じ。
二叢ユ
放熱凹部５を孔径１．２ｍｍ、個数２４個に設定して設
けた他は例１と同し。
一桝Ａ
放熱凹部５を孔径１．２ｍｍ、個数２４個に設定して設
け、放熱層７をその面積を絶縁基板１の外形面積の９０
％に設定して設けた他は例１と同じ。
二鮭旦
第９図に示す半導体チップキャリアにおいて、放熱凹部
５を１５ｍｍＸ１５ｍｍの平面大きさて設け、例１と同
様にパワートランジスタを実装した。
Ｉ−凹ｊ
第１０図に示す半導体チップキャリアにおいて、金属板
２に１５ｍｍＸ１５ｍｍＸ０．３ｍｍの銅の伝熱用金属
板１５を接着し、例１と同様にパワートランジスタを実
装した。
上記例１〜例６の半導体チップキャリアを無風状態、風
速ｌ ｍ ／ ｓ 、風速３ｍ／ｓ、風速５ｍ／Ｓの状
態に置いて、パワートランジスタにＩＷの電力をかけ続
けて発熱させ、一定温度に飽和したところで熱抵抗測定
機（Ｋｕｗａｎｏ Ｅ！ｅｃｔｒｉｃａｌ Ｉｎｓｔｒ
ｕｍｅｎｔｓ社製）によって熱抵抗値を測定した。結果
を次表に示す。
表にみられるように、第１図の半導体チップキャリアに
係る例１〜例４のものにおいて特に良好な結果が得られ
る。The present invention will be explained in detail below with reference to Examples. The insulating substrate 1 is made of a printed wiring board or the like obtained by processing a copper-clad laminate such as an epoxy resin laminate laminated with copper foil, and as shown in FIG. A metal plate 2 having good thermal conductivity, such as aluminum or copper, is buried in the interior of the metal plate 1 . This metal plate 2 can be embedded simultaneously when forming the laminated plate constituting the insulating substrate 1. A cavity recess 3 is provided on the lower surface of the insulating substrate 1 with an area smaller than the area of the metal plate 2, and the bottom surface of the cavity recess 3 is formed by the metal plate 2. Further, on the lower surface of the insulating substrate 1, a plurality of circuits (not shown) are formed radially around the cavity recess 3 by etching copper foil. A semiconductor chip 4 such as an IC chip is placed in the metal plate 2 in the cavity recess 3.
The semiconductor chip 4 is connected to the circuit by bonding a wire 11 such as a gold wire between the external connection terminal portion of the semiconductor chip 4 and one end of the circuit. The insulating substrate 1 further includes a plurality of terminals 12.12.
... is protruded from the bottom surface of the insulating substrate 1.
Each terminal 12 is connected to the other end of the circuit, and the semiconductor chip 4 is connected to the terminal 12 via the circuit. On the other hand, on the upper surface of the insulating substrate 1, heat dissipation recesses 5, 5, . Each of the heat dissipation recesses 5, 5, . . . is formed so that its lower end reaches the metal plate 2, and as shown in FIG. 1(b), it is arranged vertically and horizontally in multiple stages. The heat dissipation recess 5 may have a rectangular longitudinal cross-sectional shape as shown in FIG.
It can be formed into a wedge shape as shown in ) or a semicircle as shown in FIG. 2(d). A heat transfer layer 6 is formed on the inner periphery of each heat dissipation recess 5, 5, etc., including the surface of the metal plate 2, and a heat dissipation layer 6 is formed on the surface of the insulating substrate 1 on the side where the heat dissipation recess 5 is provided. 7 is formed, and this heat transfer layer 6
and the heat dissipation layer 7 are formed so as to be integral and continuous. The heat dissipation layer 7 is preferably formed in an area that is 30% or more of the area of the surface of the insulating substrate 1 (the surface on which the heat dissipation layer 7 is formed). Although there is no particular upper limit, it is practically 95%. These heat transfer layer 6 and heat dissipation ffl7 can be formed by plating metal such as copper. 2, the heat is further transferred from the metal plate 2 through the heat transfer layer 6 of the heat dissipation recess to the heat dissipation layer 7 on the surface of the insulating substrate 1, and the heat is radiated to the outside from the heat dissipation layer 7. It is also possible to bond and attach a heat sink 13 to the surface of the heat dissipation layer 7 so that heat is further transferred from the heat dissipation layer 7 to the heat sink 13 and radiated from the heat sink 3. FIG. 3 shows another embodiment of the present invention, in which the metal plate 2 is embedded almost over the entire surface of the insulating substrate 1, in which the insulation between the metal plate 2 and the terminal 12 is removed. In order to ensure this, a through hole 14 is provided in the metal plate 2.
The terminal 12 is passed through the inside. In the embodiment shown in FIG. 4 (a Hb ), the heat dissipation recess 5 is formed as an annular edge 5a, and the heat dissipation layer 7 is formed to cover almost the entire upper surface of the insulating substrate 1. In the embodiment shown in FIG. 5, the heat radiation recess 5 is formed as an elongated arm 5b. Further, in each of the above embodiments, the heat dissipation recess 5 is formed in the insulating substrate 1 on the side opposite to the side where the cavity recess 3 for mounting the semiconductor chip 4 is provided, and the heat transfer layer 6 and the heat dissipation layer 7 are formed in the insulating substrate 1.
However, as shown in FIG. 6, a heat dissipation recess 5 is formed in the insulating substrate 1 on the side where the cavity recess 3 is provided, and a heat transfer layer 6 and a heat dissipation layer 7 are formed. You can also do this. Although the semiconductor chip carrier in each of the above embodiments is of the PGA type, it can also be formed of the QFP type as in the embodiment shown in FIGS. 7(a) and 8(b) and the embodiment shown in FIG. Furthermore, it is also possible to form the heat dissipation recess 5 with a wide area as shown in FIGS. 9(a) and 9(b). However, in this case, the heat sink 13 may not be able to be attached because the heat dissipating portion 5 is too wide. Also, as shown in Figure 10,
The heat dissipation recess 5 can also be formed by attaching the heat transfer metal plate 15 to the metal plate 2 with a thermally conductive adhesive 16. However, in this case, manufacturing cost becomes an issue. Next, the heat dissipation effect will be demonstrated with a specific example. Knee Example 2 In the semiconductor chip carrier shown in FIG. 1, heat dissipation recesses 5 are provided with a hole diameter Q of 6 mm and a number of 52, and the area of the heat dissipation layer 7 is set to 30% of the external area of the insulating substrate 1. A 2SD-1580 power transistor (manufactured by ROHM Co., Ltd.) was mounted in the cavity recess 3 and sealed with liquid epoxy resin.The heat dissipation recess 5 was set to have a hole diameter of 0.8 mm and a number of 40 pieces. The rest is the same as Example 1. The same as Example 1 except that the two-row heat dissipation recesses 5 were provided with a hole diameter of 1.2 mm and a number of 24 pieces. One square A Heat dissipation recesses 5 with a hole diameter of 1.2 mm and a number of 24 are provided, and the heat dissipation layer 7 has an area of 90% of the external area of the insulating substrate 1.
It is the same as Example 1 except that it is set to %. In the semiconductor chip carrier shown in FIG. 9, a heat dissipation recess 5 was provided with a planar size of 15 mm x 15 mm, and a power transistor was mounted in the same manner as in Example 1. I-Concave j In the semiconductor chip carrier shown in FIG. 10, a 15 mm x 15 mm x 0.3 mm copper heat transfer metal plate 15 was adhered to the metal plate 2, and a power transistor was mounted in the same manner as in Example 1. The semiconductor chip carriers of Examples 1 to 6 above were placed in a state of no wind, a wind speed of 1 m/s, a wind speed of 3 m/s, and a wind speed of 5 m/s, and the power transistor was continuously applied with IW power to generate heat to maintain a constant temperature. When the temperature is saturated, the thermal resistance measuring machine (Kuwano E! electrical Instr.
The thermal resistance value was measured using a method (manufactured by Uments Co., Ltd.). The results are shown in the table below. As seen in the table, particularly good results are obtained in Examples 1 to 4 of the semiconductor chip carrier shown in FIG.
上述のように本発明にあっては、絶縁基板に表面から金
属板に至る放熱凹部を穿設し、放熱凹部の内周に伝熱層
を形成すると共に絶縁基板の表面に伝熱層と連続する放
熱層を形成するようにしたので、半導体チップから金属
板に吸収された熱は放熱凹部の伝熱層から絶縁基板の表
面の放熱層に伝導されることになり、絶縁基板の表面に
おいて放熱層から良好に放熱させることができるもので
ある。As described above, in the present invention, a heat dissipation recess is formed in the insulating substrate from the surface to the metal plate, a heat transfer layer is formed on the inner periphery of the heat dissipation recess, and a heat transfer layer is formed on the surface of the insulating substrate that is continuous with the heat transfer layer. As a result, the heat absorbed from the semiconductor chip into the metal plate is conducted from the heat transfer layer in the heat radiation recess to the heat radiation layer on the surface of the insulating substrate, and the heat is radiated on the surface of the insulating substrate. This allows for good heat dissipation from the layer.
第１図（ａ Ｈｂ ）は本発明の一実施例の断面図と平
面図、第２図（ａ）乃至（ｄ）は同上の一部の拡大した
断面図、第３図は同上の他の実施例の断面図、第４図（
ａ ）（ｂ ）は同上のさらに他の実施例の断面図と平
面図、第５図はさらに他の実施例の平面図、第６図はさ
らに他の実施例の断面図、第７図（ａ ）（ｂ ）はさ
らに他の実施例の断面図と平面図、第８図はさらに他の
実施例の断面図、第９図（ａ＞（ｂ）はさらに他例の断
面図と平面図、第１０図はさらに他例の断面図である。
１は絶縁基板、２は金属板、３はキャビティ凹所、４は
半導体チップ、５は放熱凹部、６は伝熱層、７は放熱層
である。FIG. 1 (a Hb) is a sectional view and a plan view of one embodiment of the present invention, FIGS. 2 (a) to (d) are enlarged sectional views of a part of the same, and FIG. Cross-sectional view of the embodiment, Fig. 4 (
a) and (b) are a sectional view and a plan view of still another embodiment same as the above, FIG. 5 is a plan view of still another embodiment, FIG. 6 is a sectional view of still another embodiment, and FIG. a) and (b) are a cross-sectional view and a plan view of yet another embodiment, FIG. 8 is a cross-sectional view of yet another embodiment, and FIG. 9 (a>(b) is a cross-sectional view and a plan view of yet another embodiment). , FIG. 10 is a sectional view of still another example. 1 is an insulating substrate, 2 is a metal plate, 3 is a cavity recess, 4 is a semiconductor chip, 5 is a heat dissipation recess, 6 is a heat transfer layer, and 7 is a heat dissipation layer. It is.
Claims (1)
が底面となるキャビティ凹所を設けてこのキャビティ凹
所に半導体チップを実装し、絶縁基板に表面から金属板
に至る放熱凹部を穿設し、放熱凹部の内周に伝熱層を形
成すると共に絶縁基板の表面に伝熱層と連続する放熱層
を形成して成ることを特徴とする半導体チップキャリア
。（２）放熱凹部を細孔状に形成すると共に絶縁基板に
多数個設けることを特徴とする請求項１に記載の半導体
チップキャリア。(1) A metal plate is buried in an insulating substrate, a cavity recess is provided in the insulating substrate with the metal plate as the bottom surface, a semiconductor chip is mounted in this cavity recess, and a heat dissipation recess is formed in the insulating substrate from the surface to the metal plate. 1. A semiconductor chip carrier characterized in that a heat transfer layer is formed on the inner periphery of a heat dissipation recess, and a heat dissipation layer continuous with the heat transfer layer is formed on the surface of an insulating substrate. (2) The semiconductor chip carrier according to claim 1, wherein the heat dissipation recesses are formed in the shape of pores and a plurality of heat dissipation recesses are provided on the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2326754A JPH06103724B2 (en) | 1990-11-27 | 1990-11-27 | Semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2326754A JPH06103724B2 (en) | 1990-11-27 | 1990-11-27 | Semiconductor chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04196255A true JPH04196255A (en) | 1992-07-16 |
| JPH06103724B2 JPH06103724B2 (en) | 1994-12-14 |
Family
ID=18191314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2326754A Expired - Lifetime JPH06103724B2 (en) | 1990-11-27 | 1990-11-27 | Semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06103724B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009295877A (en) * | 2008-06-06 | 2009-12-17 | Koa Corp | Resistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210851A (en) * | 1989-02-10 | 1990-08-22 | Matsushita Electric Works Ltd | Semiconductor chip carrier |
-
1990
- 1990-11-27 JP JP2326754A patent/JPH06103724B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210851A (en) * | 1989-02-10 | 1990-08-22 | Matsushita Electric Works Ltd | Semiconductor chip carrier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009295877A (en) * | 2008-06-06 | 2009-12-17 | Koa Corp | Resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06103724B2 (en) | 1994-12-14 |
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