JPS6239032A - Chip carrier for electronic element - Google Patents

Chip carrier for electronic element

Info

Publication number
JPS6239032A
JPS6239032A JP17882085A JP17882085A JPS6239032A JP S6239032 A JPS6239032 A JP S6239032A JP 17882085 A JP17882085 A JP 17882085A JP 17882085 A JP17882085 A JP 17882085A JP S6239032 A JPS6239032 A JP S6239032A
Authority
JP
Japan
Prior art keywords
wiring board
metal rod
electronic component
metal bar
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17882085A
Other languages
Japanese (ja)
Inventor
Toru Higuchi
徹 樋口
Toshiyuki Yamaguchi
敏行 山口
Takeshi Kano
武司 加納
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP17882085A priority Critical patent/JPS6239032A/en
Publication of JPS6239032A publication Critical patent/JPS6239032A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE:To suppress the heat generation of an electronic component chip and to contrive to improve its reliability by a method wherein the electronic component chip is mounted on the surface of a printed-wiring board at the fixed position of the metal bar of the printed-wiring board, and at the same time, one end part of the metal bar is provided with a heat-radiating part. CONSTITUTION:A hole 3 for holding a metal bar is penetrated in a printed- wiring board 1 which is formed by providing circuit patterns 4 on the surface of a substrate 2 and the base part of the metal bar 17 is inserted and fixed in the hole 3 for holding the metal bar. One end part of the metal bar 17 is protruded from the surface of the printed-wiring board 1, an electronic component chip 5 is mounted on the surface of the printed-wiring board 1 at the fixed position of the metal bar 17, and at the same time, the other protruded end part of the metal bar 17 is provided with a heat-radiating part 6. By this constitution, the heat of the electronic component chip 5 is radiated through the heat-radiating part 6 along the metal bar 17.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、ＩＣパッケージなどのような電子素子の基板
として用いられる電子素子用チップキャリアに閃するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a chip carrier for an electronic device used as a substrate for an electronic device such as an IC package.

［背景Ｉ支術］ ＩＣパッケージなどのような電子素子は、半導体ナツプ
などの電子部品チップをリードフレームに取り付けた状
態で樹脂封止や気密封止してバッケーノングすることに
よっておこなわれる。そしてこのような電子素子にあっ
て、端子数の増加に伴って電子部品チップを支持するキ
ャリアとしてのり−ド７レームの替わりにプリント配線
板を用いる試みがなされている。[Background I] Electronic devices such as IC packages are manufactured by attaching an electronic component chip such as a semiconductor chip to a lead frame, sealing it with resin or hermetically sealing it, and then baking it. With the increase in the number of terminals in such electronic devices, attempts have been made to use printed wiring boards as carriers for supporting electronic component chips instead of glue boards.

ここにおいて、近時の電子部品チップの高密度化は発熱
を伴い、この熱を逃がす工夫が必要とされる。しかしキ
ャリアとして用いられるプリント配線板は〃フス布エポ
キシ樹脂積層板など樹脂積層板で形成されており、この
ようなプリント配線板は得の伝導性が悪くて放熱を良好
になすことができず、電子部品チップのキャリアとして
プリント配線板を用いることについての難点になってい
るものであった。Here, the recent increase in the density of electronic component chips is accompanied by heat generation, and it is necessary to devise ways to dissipate this heat. However, printed wiring boards used as carriers are made of resin laminates such as cloth epoxy resin laminates, and such printed wiring boards have poor conductivity and cannot dissipate heat well. This has been a problem with using printed wiring boards as carriers for electronic component chips.

［発明の目的］ 本発明は、上記の点に鑑みて為されたものであり、放熱
性に優れた電子部品用チップキャリアを提供することを
目的とするものである。[Object of the Invention] The present invention has been made in view of the above points, and an object of the present invention is to provide a chip carrier for electronic components that has excellent heat dissipation properties.

「発明の開示」 しかして、本発明に係る電子素子用チップキャリアは、
基板２の表面に回路パターン４を設けて形成されるプリ
ント配線板１に金属棒保持用孔３を貫通し、金属棒保持
用孔３内に金属棒１７の基部を挿入固定すると共に金属
棒１７の端部をプリント配線板１の表面より突出させ、
金属棒１７の固定位置にてプリント配線板１の表面に電
子部品チップ３を実装すると共に突出された金属棒１７
の端部に放熱部６を設けて成ることを特徴とするもので
、プリント配線板１内に放熱性に優れた金属棒１７を挿
入してこの金属棒１７の端部に放熱ｎ６を設けることに
より電子部品チップ５の熱を金属棒１７を伝って放熱部
６から放熱するようにし、以て上記目的を達成したもの
である。"Disclosure of the Invention" Therefore, the chip carrier for electronic devices according to the present invention is
A printed wiring board 1 formed by providing a circuit pattern 4 on the surface of a substrate 2 is penetrated through a metal rod holding hole 3, and the base of a metal rod 17 is inserted and fixed into the metal rod holding hole 3. The end of the printed wiring board 1 is made to protrude from the surface of the printed wiring board 1,
The electronic component chip 3 is mounted on the surface of the printed wiring board 1 at the fixed position of the metal rod 17, and the metal rod 17 is protruded.
A metal rod 17 having excellent heat radiation properties is inserted into the printed wiring board 1, and a heat radiation part 6 is provided at the end of the metal rod 17. In this way, the heat of the electronic component chip 5 is transmitted through the metal rod 17 and radiated from the heat radiating section 6, thereby achieving the above object.

以下本発明を実施例により詳述する。プリント配線板１
は例えば金属箔張りの樹脂積層板１２から作成すること
ができる。すなわち、プラス布や紙などを基材とし、こ
の基材にエポキシ樹脂やポリイミド樹脂、７エ７−ル樹
脂などの熱硬化性樹脂、その他種々の熱可塑性樹脂の樹
脂フェスを含浸させ、これを加熱などして乾燥させるこ
とによってプリプレグを調製し、このプリプレグを複数
枚積載すると共に片側または両側の最外層のプリプレグ
の外面に＃Ｉ箔などの金属箔１３を重ね、これを加熱加
圧成形することによって、プリプレグの樹脂が溶融硬化
することで形成される樹脂積層板１２の表面に金属箔１
３が１層された金属箔張り樹＆！積層板を得ることがで
き、そしてこの金属箔張り樹脂積層板の金属Ｍ１３にエ
ツチングなどを施して回路パターン４を形成させること
によって、第２図＜８）に示すような表面に回路パター
ン４を設けたプリント配線板１を得ることができるもの
である。このプリント配線板１には表裏面の回路パター
ン４，１４を導通させるためのスルーホール１８が複数
設けられ、スルーホール１８内面にスルーホールメッキ
１９が施されておりこのスルーホールメッキ１９によっ
てプリント配線板１の表裏面の回路パターン４，４が導
通接続されている。そして、スルーホール１８の一つあ
るいは複数を金属棒保持用孔３として利用するものであ
る。The present invention will be explained in detail below with reference to Examples. Printed wiring board 1
can be made from a resin laminate plate 12 covered with metal foil, for example. That is, a base material such as plastic cloth or paper is used, and this base material is impregnated with a resin face of thermosetting resin such as epoxy resin, polyimide resin, 7-el resin, and various other thermoplastic resins. A prepreg is prepared by drying it by heating, etc., a plurality of sheets of the prepreg are stacked, a metal foil 13 such as #I foil is layered on the outer surface of the outermost layer of prepreg on one or both sides, and this is heated and pressure-molded. By this, the metal foil 1 is placed on the surface of the resin laminate 12 which is formed by melting and hardening the resin of the prepreg.
Metal foiled tree with one layer of 3 &! A laminate can be obtained, and the circuit pattern 4 can be formed on the surface as shown in FIG. The printed wiring board 1 provided can be obtained. This printed wiring board 1 is provided with a plurality of through holes 18 for conducting the circuit patterns 4 and 14 on the front and back surfaces, and through hole plating 19 is applied to the inner surface of the through hole 18. Circuit patterns 4, 4 on the front and back surfaces of the board 1 are electrically connected. One or more of the through holes 18 are used as the metal rod holding holes 3.

金属棒１７は伝導性に優れたものでプリント配線板１の
厚みよりも長く形成され、第２図（ｂ）のように金属棒
１７はプリント配線板１の金属棒保持用孔３内に挿入さ
れて半田、あるいは接着剤等で固定されており、金属棒
１７の基部はプリント配線板１のスルーホール１８内に
埋入されて電気接続されていると共に金属棒１７の端部
はプリント配線板１の表面から突出している、この突出
した金属棒１７の！ａ部には第１図に示す、）：うにヒ
ートパイプ、放熱フィン等で形成される放熱部６が取り
付けである。The metal rod 17 has excellent conductivity and is formed to be longer than the thickness of the printed wiring board 1. As shown in FIG. 2(b), the metal rod 17 is inserted into the metal rod holding hole 3 of the printed wiring board 1. The base of the metal rod 17 is embedded in the through hole 18 of the printed wiring board 1 and electrically connected, and the end of the metal rod 17 is fixed to the printed wiring board 1 with solder or adhesive. This protruding metal rod 17 protrudes from the surface of 1! A heat dissipating section 6 formed of a heat pipe, a heat dissipating fin, etc. shown in FIG. 1 is attached to part a.

このように形成しだらのをチップキャリアとして用い、
半導体チップなどの電子部品チップ５を実装するらので
あるが、実装にあたっては第２図（ｃ）のようにプリン
ト配線板１に固定された金属棒１７の位置にてプリント
配線＠１の表面に電子部品チップ５を搭載し、電子部品
チップ５とプリント配線板１の表面の回路パターン４と
の間にワイヤーボンディング２０などを施して電子部品
チップ５と回路パターン４とを電気的に接続させること
によりておこなうことがでトる。ここにおいて、電子部
品チップ５は金属棒１７を介して放熱部６に接続されて
いるために、電子部品チップ５の発熱は良好に放熱部６
に伝達されることになり、放熱部６から良好に放熱する
ことがでとるものであり、電子部品チップ５が昇温する
ことを防止して電子部品チップ５の高密度化を可能にす
ることができるものである。Using the thus formed weeping as a chip carrier,
An electronic component chip 5 such as a semiconductor chip is mounted, and as shown in FIG. Mounting the electronic component chip 5 and performing wire bonding 20 or the like between the electronic component chip 5 and the circuit pattern 4 on the surface of the printed wiring board 1 to electrically connect the electronic component chip 5 and the circuit pattern 4. It is possible to do this by Here, since the electronic component chip 5 is connected to the heat radiating section 6 via the metal rod 17, the heat generated by the electronic component chip 5 can be efficiently transferred to the heat radiating section 6.
This is achieved by good heat dissipation from the heat dissipation section 6, which prevents the electronic component chip 5 from rising in temperature and enables higher density of the electronic component chip 5. It is something that can be done.

また、このように電子部品チップ５を実装したものをパ
フケーシングすることによって、ＩＣＣバラケージど電
子素子として仕上げるしのであるが、ＰＧＡ（ビン　グ
リッド　アレー）として仕上げる場合には端子ビン７を
電子部品チップ５と電気的に接続した状態で取り付ける
必妥がある。このととには第３図に示すように端子ビン
７の基部むプリント配線板１のスルーホール１８内に挿
入固定することによりて、電子部品チップ５に接続した
状態で端子ビン７を取り付けることが”ｃ’ｓる。In addition, by puff casing the electronic component chip 5 mounted in this way, it can be finished as an electronic element such as an ICC bulk cage, but when finished as a PGA (bin grid array), the terminal bin 7 can be used as an electronic component chip. It is necessary to install it while electrically connected to 5. In this case, as shown in FIG. 3, the terminal pin 7 is attached in a state connected to the electronic component chip 5 by inserting and fixing it into the through hole 18 of the printed wiring board 1 located at the base of the terminal pin 7. But "c's".

第４図（ａ）はＰＧＡをソケッ）１０に接続する例を示
し、第４図（ｂ）はＬ　ＣＣ（リードレス　チップキャ
リア）をソック）１０ｉご接続する例を示し、・、二も
のｃ、ｌ’＋る。このソツケト１（〕には上記ＰＧＡ：
、：取り付けらｉた；ツ子ビン７に対応する位置にて固
定孔８が設けられた固定ビン９が複数本設けられ、ご〆
こＰ　Ｇ　Ａの金属枠１７に対応する位置にて一名属板
１ｊが埋設されていて、この金属板１１には金属棒１′
ｉ′を嵌合するための通孔１５や凹所１６が設（つられ
ている、ＰＧｌλをソック）１０の上面に配置してＰＧ
Ａの端子ビン′７をンッケト１０の固定孔８内に挿入す
ると共にＰＧＡの金属棒１７をソツケト１０の金属板１
１に嵌合しｔこ際には電子部品チップ５が金属棒１７そ
介して金属板１１に接続されることになり、電子部品チ
ップ５の熱を良好］こ放散することができると共に、ま
たＰＧＡのＦ面より突出しｔこ金属棒１７がチップキャ
リアを基板２へ実装する際の位置決めにもなるものであ
る。Figure 4(a) shows an example of connecting a PGA to a socket) 10, and Figure 4(b) shows an example of connecting an LCC (leadless chip carrier) to a socket) 10i. , l'+ru. This socket 1 () has the above PGA:
A plurality of fixing bins 9 are provided with fixing holes 8 at positions corresponding to the two-piece bins 7, and one is fixed at a position corresponding to the metal frame 17 of the PG A. A metal plate 1j is buried, and a metal rod 1' is buried in this metal plate 11.
A through hole 15 and a recess 16 for fitting the PG i′ are arranged on the upper surface of the PGlλ (socket) 10.
Insert the terminal pin '7 of A into the fixing hole 8 of the socket 10, and insert the metal rod 17 of the PGA into the metal plate 1 of the socket 10.
In this case, the electronic component chip 5 is connected to the metal plate 11 via the metal rod 17, and the heat of the electronic component chip 5 can be dissipated well. The metal rod 17 protruding from the F side of the PGA also serves for positioning when mounting the chip carrier on the board 2.

［発明の効果１ 上述のよう４二本発明にあっ′Ｃは、プリント配線板に
金属棒保持用化を貫通し、金属棒保持用孔内に金属棒の
基部を挿入固定すると共に金属棒の端部をプリント配線
板の表面より突出させ、金属棒の固定位置にてプリント
配線板の表面に電子部品チップを実装すると共に＝＆属
棒の端部に放熱部を設けたので、電子部品チップの発熱
は熱伝導性に優れた金属棒を辿って放熱部から放熱さね
、ることになり、電子部品チップの発熱を抑制して信頼
性を向」ニすることがで終ると共に電子部品チップの高
密度化を可能にすることができるものである。[Effect of the Invention 1 As described above, the present invention has the following features: A metal rod holding hole is penetrated through the printed wiring board, the base of the metal rod is inserted and fixed into the metal rod holding hole, and the metal rod is fixedly inserted into the metal rod holding hole. The electronic component chip is mounted on the surface of the printed wiring board at the fixed position of the metal rod, with the end protruding from the surface of the printed wiring board, and a heat dissipation part is provided at the end of the metal rod. The heat generated by the electronic component chips follows the metal rod with excellent thermal conductivity and is dissipated from the heat dissipation section, which suppresses the heat generation of the electronic component chips and improves reliability. It is possible to achieve higher density.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の断面図、第２図（ａ）（ｂ
Ｈｅ）は本発明の一実施例における製造の各工程の断面
図、第３図は本発明の他の実施例の断面図、第４図（ａ
）（ｂ）は同上のさらに他の実施例のび解断面図である
。 １はプリント配ｍ板、２は基板、３はビン保持用孔、４
は回路パターン、５は電子部品チップ、６は放熱部、１
７は金属棒である。Figure 1 is a sectional view of one embodiment of the present invention, Figures 2 (a) and (b)
He) is a cross-sectional view of each manufacturing step in one embodiment of the present invention, FIG. 3 is a cross-sectional view of another embodiment of the present invention, and FIG.
)(b) is an exploded sectional view of still another embodiment of the same. 1 is a printed wiring board, 2 is a board, 3 is a hole for holding a bottle, 4 is
is a circuit pattern, 5 is an electronic component chip, 6 is a heat dissipation part, 1
7 is a metal rod.

Claims (1)

【特許請求の範囲】[Claims] （１）基板の表面に回路パターンを設けて形成されるプ
リント配線板に金属棒保持用孔を貫通し、金属棒保持用
孔内に金属棒の基部を挿入固定すると共に金属棒の端部
をプリント配線板の表面より突出させ、金属棒の固定位
置にてプリント配線板の表面に電子部品チップを実装す
ると共に突出された金属棒の端部に放熱部を設けて成る
ことを特徴とする電子素子用チップキャリア。(1) Penetrate a metal rod holding hole into a printed wiring board formed by providing a circuit pattern on the surface of the board, insert and fix the base of the metal rod into the metal rod holding hole, and secure the end of the metal rod. An electronic device characterized in that an electronic component chip is mounted on the surface of the printed wiring board by protruding from the surface of the printed wiring board at a fixed position of a metal rod, and a heat dissipation part is provided at the end of the protruding metal rod. Chip carrier for elements.
JP17882085A 1985-08-14 1985-08-14 Chip carrier for electronic element Pending JPS6239032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17882085A JPS6239032A (en) 1985-08-14 1985-08-14 Chip carrier for electronic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17882085A JPS6239032A (en) 1985-08-14 1985-08-14 Chip carrier for electronic element

Publications (1)

Publication Number Publication Date
JPS6239032A true JPS6239032A (en) 1987-02-20

Family

ID=16055231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17882085A Pending JPS6239032A (en) 1985-08-14 1985-08-14 Chip carrier for electronic element

Country Status (1)

Country Link
JP (1) JPS6239032A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145337U (en) * 1986-03-07 1987-09-12
EP0522563A3 (en) * 1991-07-12 1994-06-08 Sumitomo Electric Industries Semiconductor chip module and method of manufacturing the same
EP0523387A3 (en) * 1991-06-18 1994-07-27 Sumitomo Electric Industries Semiconductor chip module and method for manufacturing the same
US6281571B1 (en) * 1999-03-26 2001-08-28 Fujitsu Limited Semiconductor device having an external connection electrode extending through a through hole formed in a substrate
US6737740B2 (en) * 2001-02-08 2004-05-18 Micron Technology, Inc. High performance silicon contact for flip chip
JP2011124386A (en) * 2009-12-10 2011-06-23 Ibiden Co Ltd Circuit board, high heat radiation connector, method for manufacturing the same, and circuit module with connector

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145337U (en) * 1986-03-07 1987-09-12
EP0523387A3 (en) * 1991-06-18 1994-07-27 Sumitomo Electric Industries Semiconductor chip module and method for manufacturing the same
EP0522563A3 (en) * 1991-07-12 1994-06-08 Sumitomo Electric Industries Semiconductor chip module and method of manufacturing the same
US5525548A (en) * 1991-07-12 1996-06-11 Sumitomo Electric Industries, Ltd. Process of fixing a heat sink to a semiconductor chip and package cap
US6281571B1 (en) * 1999-03-26 2001-08-28 Fujitsu Limited Semiconductor device having an external connection electrode extending through a through hole formed in a substrate
US6737740B2 (en) * 2001-02-08 2004-05-18 Micron Technology, Inc. High performance silicon contact for flip chip
US6812137B2 (en) 2001-02-08 2004-11-02 Micron Technology, Inc. Method of forming coaxial integrated circuitry interconnect lines
US6828656B2 (en) 2001-02-08 2004-12-07 Micron Technology, Inc. High performance silicon contact for flip chip and a system using same
JP2011124386A (en) * 2009-12-10 2011-06-23 Ibiden Co Ltd Circuit board, high heat radiation connector, method for manufacturing the same, and circuit module with connector

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