JPH04184951A - Semiconductor element mounting method - Google Patents

Semiconductor element mounting method

Info

Publication number
JPH04184951A
JPH04184951A JP2312666A JP31266690A JPH04184951A JP H04184951 A JPH04184951 A JP H04184951A JP 2312666 A JP2312666 A JP 2312666A JP 31266690 A JP31266690 A JP 31266690A JP H04184951 A JPH04184951 A JP H04184951A
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
electrodes
wiring board
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2312666A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Atsushi Miki
淳 三木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2312666A priority Critical patent/JPH04184951A/en
Priority to EP91119669A priority patent/EP0490125B1/en
Priority to DE69117891T priority patent/DE69117891T2/en
Priority to CA002055845A priority patent/CA2055845A1/en
Priority to US07/794,869 priority patent/US5244142A/en
Priority to AU87998/91A priority patent/AU640537B2/en
Priority to KR1019910020651A priority patent/KR960000696B1/en
Publication of JPH04184951A publication Critical patent/JPH04184951A/en
Priority to US08/012,369 priority patent/US5348214A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE:To lower the thermal resistance simultaneously eliminating the alignment step with high precision by a method wherein the heat dissipation fins are bonded onto the fear surface of semiconductor element using the solder at lower melting point than that of solder bumps furthermore, the electrodes of a wiring substrate are formed in recessed form. CONSTITUTION:The rear surface on the opposite side of the surface of a semiconductor element whereon bump electrodes are formed is aligned with a heat sink 1 to be bonded thereto using the solder 6 at the melting point lower than that of solder bumps 4. Next, when the electrodes of semiconductor elements 2 and a wiring substrate 5 are mutually aligned with one another and tack-fixed to be heated, the low melting point solder 6 is melted down before the solder bumps 4 are melted down. At this time, the solder bumps 4 are forced to be shifted to the centers of the recessed electrodes 7 so that the element 2 may be shifted to the correct position as if sliding over the surface of the heat sink 1. Through these procedures, the alignment of the element 2 with the wiring substrate 5 can be facilitated thereby enabling the thermal resistance to be lowered.

Description

【発明の詳細な説明】 〈産業上の利用分野〉　　。[Detailed description of the invention] <Industrial application field>.

本発明は、複数の半導体素子を配線基板に実装する半導
体素子実装方法に関する。The present invention relates to a semiconductor element mounting method for mounting a plurality of semiconductor elements on a wiring board.

〈従来の技術〉 複数の半導体素子を配線基板上へフェースダウンボンデ
ィングする場合には、従来、半田バンプの形成されたバ
ンプ電極を有する複数の半導体素子と配線基板とを相互
に電極を位置合わせして押し付けて仮固定し、その後加
熱して前記半田バンプを溶融することにより前記複数の
半導体素子を前記配線基板に実装するようにしている。<Prior Art> When performing face-down bonding of multiple semiconductor elements onto a wiring board, conventionally, the multiple semiconductor elements having bump electrodes on which solder bumps are formed and the wiring board are aligned with each other. The plurality of semiconductor elements are mounted on the wiring board by temporarily fixing the semiconductor elements by pressing and then heating to melt the solder bumps.

このように実装された半導体素子に発生した熱の放熱経
路は、バンプ電極を経由して配線基板に逃げるしかなく
、熱抵抗が非常に大きかった。The heat generated in the semiconductor element mounted in this manner has no choice but to escape to the wiring board via the bump electrodes, resulting in extremely high thermal resistance.

このことは、特に、半導体素子の消費電力が大きい場合
に問題となっていた。This has been a problem, particularly when the power consumption of the semiconductor element is large.

そこで、従来では、半導体素子の放熱経路としてヒート
シンクを設ける方法が一般に採用されている（二瓶公志
、早用征男、宮代文夫編“半導体装技術ハンドブック′
株式会社サイエンスフォーラム（１９８６））。Therefore, in the past, a method of providing a heat sink as a heat dissipation path for semiconductor elements was generally adopted (Koshi Nihei, Yukio Hayayo, Fumio Miyashiro, eds. "Semiconductor Device Technology Handbook").
Science Forum Co., Ltd. (1986)).

〈発明が解決しようとする課題〉 しかし、上記方法は複数の半導体素子を配線基板上へフ
ェースダウンポンディングした後にヒートシンクを半導
体素子に接着させる為、半導体素子の傾き等によりヒー
トシンクと半導体素子とが接触不良を起こしやすい問題
点があった。<Problems to be Solved by the Invention> However, in the above method, a plurality of semiconductor elements are bonded face-down onto a wiring board and then the heat sink is bonded to the semiconductor element, so the heat sink and the semiconductor element may become disconnected due to the inclination of the semiconductor element or the like. There was a problem that it was easy to cause poor contact.

また、複数の半導体素子を配線基板に対して高精度に位
置決めする必要があり、この為、実装時間が長時間とな
る問題があった。Furthermore, it is necessary to position a plurality of semiconductor elements with high precision with respect to the wiring board, which poses a problem of requiring a long mounting time.

本発明は、上記従来技術に鑑みて成されたものであり、
配線基板にフェースダウンポンディングにより実装され
る複数の半導体素子と放熱フィンとを確実に接触させ、
その熱抵抗を減少させると共に高精度な位置決め技術の
不要な半導体素子実装方法を提供することを目的とする
。The present invention has been made in view of the above-mentioned prior art,
Multiple semiconductor elements mounted on the wiring board by face-down bonding are brought into secure contact with the heat dissipation fins,
It is an object of the present invention to provide a semiconductor element mounting method that reduces the thermal resistance and does not require highly accurate positioning technology.

く課題を解決するための手段〉 斯かる目的を達成する本発明の構成は凸段して形成した
バンプ電極を有する複数の半導体素子と配線基板を相互
に電極を位置合わせして押し付け、加熱することにより
前記複数の半導体素子を前記基板に実装する方法におい
て、予め前記複数の半導体素子の前記バンプ電極を形成
した表面と反対側の裏面に放熱フィンを位置決めして接
着すると共に前記半導体素子と前記放熱フィンとの接着
に使用される半田として前記バンプ電極のバンプよりも
融点の低い低融点半田を使用し、更に前記配線基板の電
極は凹状に加工されることを特徴とする。Means for Solving the Problems> The structure of the present invention to achieve the above object is to press a plurality of semiconductor elements and a wiring board having bump electrodes formed in a convex manner to each other with the electrodes aligned, and heat them. In the method of mounting the plurality of semiconductor elements on the substrate, a radiation fin is positioned and bonded in advance to the back surface of the plurality of semiconductor elements opposite to the surface on which the bump electrodes are formed, and the semiconductor elements and the semiconductor elements are mounted on the substrate. The present invention is characterized in that a low melting point solder having a melting point lower than that of the bump of the bump electrode is used as the solder used for adhesion to the heat radiation fin, and the electrode of the wiring board is processed into a concave shape.

〈作用〉 複数の半導体素子を配線基板に対して押し付ける際、半
導体素子の配線基板に対する位置決め精度が不十分であ
ると、半導体素子に凸段したバンプ電極と、配線基板の
凹状電極とは、完全に嵌合しないが、その後、加熱され
ると、半田バンプが溶融する前に、低融点半田が溶融す
るので、バンプ電極を凹状電極の中心に移動させようと
する力により、半導体素子がヒートシンク上を滑るよう
に正確な位置に移動する。<Function> When multiple semiconductor elements are pressed against the wiring board, if the positioning accuracy of the semiconductor elements with respect to the wiring board is insufficient, the bump electrodes on the semiconductor elements and the concave electrodes on the wiring board may not be completely aligned. However, when heated, the low melting point solder melts before the solder bump melts, so the force trying to move the bump electrode to the center of the concave electrode causes the semiconductor element to move onto the heat sink. gliding to the correct position.

〈実施例〉 以下、本発明について、図面に示す実施例を参照して詳
細に説明する。<Examples> The present invention will be described in detail below with reference to examples shown in the drawings.

先ず、第１図に示すように、放熱フィンとして使用され
るヒートシンク１の下面にレジストパターン３を形成す
る。First, as shown in FIG. 1, a resist pattern 3 is formed on the lower surface of a heat sink 1 used as a heat radiation fin.

レジストパターン３は複数の半導体素子２の位置合わせ
用であり、例えば、フォトリソグラフィーにより形成す
る。The resist pattern 3 is used for positioning the plurality of semiconductor elements 2, and is formed by, for example, photolithography.

このため、レジストパターン３の開口部は、半導体素子
２の外形と等しく、複数の半導体素子２をフェースダウ
ンポンディングする位置と対応している。Therefore, the opening of the resist pattern 3 is equal to the outer shape of the semiconductor element 2 and corresponds to the position where the plurality of semiconductor elements 2 are face-down bonded.

一方、各半導体素子２の表面には、半田バンプ４の凸段
して形成された複数のバンプ電極が配置されている。On the other hand, on the surface of each semiconductor element 2, a plurality of bump electrodes of solder bumps 4 formed in convex steps are arranged.

次に、第１図に示すように、半導体素子２のバンプ電極
の形成された表面と反対側の裏面をヒートシンクｌに位
置決めして接着する。Next, as shown in FIG. 1, the back surface of the semiconductor element 2 opposite to the surface on which the bump electrodes are formed is positioned and bonded to the heat sink l.

接着は複数の半導体素子２について、半田バンプ４より
も融点の低い低融点半田６を使用する。For bonding, a low melting point solder 6 having a melting point lower than that of the solder bumps 4 is used for the plurality of semiconductor elements 2.

また、半導体素子２の位置決め精度は大まかなもので良
く、例えば、バンプ径８０μｍ、配線基板の電極径１０
０μｍの場合、従来では、±ＩＯμｍであったのに対し
、本実施例の場合では、±５０μｍで良い。Further, the positioning accuracy of the semiconductor element 2 may be rough, for example, the bump diameter is 80 μm, the electrode diameter of the wiring board is 10 μm, etc.
In the case of 0 μm, conventionally it was ±IO μm, but in the case of this embodiment, it may be ±50 μm.

引き続き、第２図に示すように配線基板５上に複数の半
導体素子２をフェースダウンポンディングする。Subsequently, as shown in FIG. 2, a plurality of semiconductor elements 2 are face-down bonded onto the wiring board 5.

即ち、半導体素子２と配線基板５とを相互に電極を位置
合わせして押し付けて仮固定し、その後、加熱して前記
半田バンプ４を溶融することにより半導体素子２を配線
基板５に実装する。That is, the semiconductor element 2 and the wiring board 5 are temporarily fixed by aligning the electrodes and pressing against each other, and then the semiconductor element 2 is mounted on the wiring board 5 by heating and melting the solder bumps 4.

この時、半導体素子２が配線基板５に対して正確に位置
決めされていなくても、セルフアライメントにより自動
的に正確な位置に移動して実装される。At this time, even if the semiconductor element 2 is not accurately positioned with respect to the wiring board 5, it is automatically moved to an accurate position by self-alignment and mounted.

即ち、配線基板５には複数の凹状電極７が設けられてお
り、これらの凹状電極７はバンプ電極の半田バンプ４に
それぞれ対応しているため、それらが完璧に位置決めさ
れていないと、両者は完全に嵌合できない。That is, the wiring board 5 is provided with a plurality of concave electrodes 7, and these concave electrodes 7 correspond to the solder bumps 4 of the bump electrodes, so if they are not perfectly positioned, the two will be damaged. It cannot be mated completely.

ここで、両者の位置決め精度が±５０μｍ程度であると
、第３図に示すように半田バンプ４は凹状電極７に完全
に嵌合しないが、その先端部が嵌合した状態で半導体素
子２は配線基板５に仮固定され、この状態では半田バン
プをこの凹状の電極中心に移動させる力が作用する。Here, if the positioning accuracy of both is about ±50 μm, the solder bump 4 will not completely fit into the concave electrode 7 as shown in FIG. It is temporarily fixed to the wiring board 5, and in this state, a force acts to move the solder bump to the center of the concave electrode.

その後、加熱されると、半田バンプ４が溶融する前に、
低融点半田６が溶融するので、半田バンプ４に働（凹状
電極７の中心に移動させようとする力により、半導体素
子２はヒートシンク１上を滑るようにして正確な位置に
移動する。Then, when heated, before the solder bumps 4 melt,
As the low melting point solder 6 melts, the semiconductor element 2 slides on the heat sink 1 and moves to an accurate position due to the force acting on the solder bump 4 (to move it to the center of the concave electrode 7).

この後、加熱を続けると半田バンプ４が溶融し、凹状電
極７とバンプ電極が接合された状態となる。Thereafter, if heating is continued, the solder bumps 4 will melt, and the concave electrode 7 and the bump electrode will be in a bonded state.

その後、加熱を停止すると、先ず半田バンプが凝固し、
次いで低融点半田６が凝固する。After that, when heating is stopped, the solder bumps first solidify.
Next, the low melting point solder 6 solidifies.

このように、複数の半導体素子２を配線基板５にフェー
スダウンボンディングする前に、予めヒートシンク１と
半導体素子２とを接着するので、半導体素子２とヒート
シンク１との接触が確実となり、両者の間の熱抵抗を低
減できる。In this way, since the heat sink 1 and the semiconductor element 2 are bonded in advance before face-down bonding the plurality of semiconductor elements 2 to the wiring board 5, the contact between the semiconductor element 2 and the heat sink 1 is ensured, and the gap between the two is ensured. can reduce the thermal resistance of

また、セルフアライメントにより半導体素子は配線基板
に対し自動的に正確な位置に移動するので、高精度な位
置決め技術が不要となる。Further, since the semiconductor element is automatically moved to an accurate position with respect to the wiring board by self-alignment, highly accurate positioning technology is not required.

これにより、実装時間が短縮され、信頼性が向上する。This reduces implementation time and improves reliability.

尚、上記実施例ではヒートシンク上にレジストパターン
を形成して半導体素子を位置決めしていたが、半導体素
子は高精度の位置決めが不要であるので、レジストパタ
ーンを省略してもよい。In the above embodiment, a resist pattern was formed on the heat sink to position the semiconductor element, but since the semiconductor element does not require highly accurate positioning, the resist pattern may be omitted.

また、上記実施例では、半田バンプ４が使用されたが、
これに代えて、Ａｕ、ＡｕＳｎ、Ｉｎバンプ等を使用す
ることができる。Further, in the above embodiment, solder bumps 4 were used, but
Instead of this, Au, AuSn, In bumps, etc. can be used.

〈発明の効果〉 以上、実施例に基づいて具体的に説明したように、本発
明は、半導体素子がヒートシンク上で配線基板に対して
所謂セルフアライメントにより正確な位置に自動的に移
動するので、半導体素子と配線基板との位置決めが容易
となり、実装時間の短縮となる。また、ヒートシンクと
半導体素子との接触が確実となるので、両者間の熱抵抗
が低減し、信頼性が向上する。<Effects of the Invention> As described above in detail based on the embodiments, the present invention has the advantage that the semiconductor element is automatically moved to an accurate position on the heat sink with respect to the wiring board by so-called self-alignment. Positioning of the semiconductor element and the wiring board becomes easy, and the mounting time is shortened. Furthermore, since contact between the heat sink and the semiconductor element is ensured, thermal resistance between the two is reduced and reliability is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第３図は本発明の一実施例に係る半導体素子実
装方法に関°し、第１図は複数の半導体素子をヒートシ
ンクに接着する様子を示す説明図、第２図は複数の半導
体素子を配線基板にフェースダウンボンディングする様
子を示す説明図、第３図は半導体素子のセルフアライメ
ントを示す拡大図である。 図面中、 ｌはヒートシンク、 ２は半導体素子、 ３はレジストパターン、 ４は半田バンプ、 ５は配線基板、 ６は低触点半田、 ７は凹状電極である。1 to 3 relate to a semiconductor device mounting method according to an embodiment of the present invention, FIG. 1 is an explanatory diagram showing how a plurality of semiconductor devices are bonded to a heat sink, and FIG. FIG. 3 is an explanatory view showing face-down bonding of a semiconductor element to a wiring board, and FIG. 3 is an enlarged view showing self-alignment of the semiconductor element. In the drawings, l is a heat sink, 2 is a semiconductor element, 3 is a resist pattern, 4 is a solder bump, 5 is a wiring board, 6 is a low contact solder, and 7 is a concave electrode.

Claims (1)

【特許請求の範囲】[Claims] 凸設して形成したバンプ電極を有する複数の半導体素子
と配線基板を相互に電極を位置合わせして押し付け、加
熱することにより前記複数の半導体素子を前記基板に実
装する方法において、予め前記複数の半導体素子の前記
バンプ電極を形成した表面と反対側の裏面に放熱フィン
を位置決めして接着すると共に前記半導体素子と前記放
熱フィンとの接着に使用される半田として前記バンプ電
極のバンプよりも融点の低い低融点半田を使用し、更に
前記配線基板の電極は凹状に加工されることを特徴とす
る半導体素子実装方法。In the method of mounting the plurality of semiconductor elements on the substrate by aligning the electrodes and pressing the plurality of semiconductor elements having bump electrodes formed in a convex manner and heating the wiring board, the plurality of semiconductor elements are mounted on the wiring board in advance. A heat dissipation fin is positioned and bonded to the back surface of the semiconductor element opposite to the surface on which the bump electrode is formed, and a solder having a melting point lower than that of the bump of the bump electrode is used to bond the semiconductor element and the heat dissipation fin. A semiconductor device mounting method characterized in that a low melting point solder is used and further the electrodes of the wiring board are processed into a concave shape.
JP2312666A 1990-11-20 1990-11-20 Semiconductor element mounting method Pending JPH04184951A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2312666A JPH04184951A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method
EP91119669A EP0490125B1 (en) 1990-11-20 1991-11-18 Method of mounting semiconductor elements
DE69117891T DE69117891T2 (en) 1990-11-20 1991-11-18 Method of assembling semiconductor elements
CA002055845A CA2055845A1 (en) 1990-11-20 1991-11-19 Method of mounting semiconductor elements
US07/794,869 US5244142A (en) 1990-11-20 1991-11-19 Method of mounting semiconductor elements
AU87998/91A AU640537B2 (en) 1990-11-20 1991-11-19 Method of mounting semiconductor elements
KR1019910020651A KR960000696B1 (en) 1990-11-20 1991-11-20 Method of mounting semiconductor elements
US08/012,369 US5348214A (en) 1990-11-20 1993-02-02 Method of mounting semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2312666A JPH04184951A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method

Publications (1)

Publication Number Publication Date
JPH04184951A true JPH04184951A (en) 1992-07-01

Family

ID=18031968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2312666A Pending JPH04184951A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JPH04184951A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729052A (en) * 1996-06-20 1998-03-17 International Business Machines Corporation Integrated ULSI heatsink
JP2007273628A (en) * 2006-03-30 2007-10-18 Fujitsu Ltd Manufacturing method for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729052A (en) * 1996-06-20 1998-03-17 International Business Machines Corporation Integrated ULSI heatsink
JP2007273628A (en) * 2006-03-30 2007-10-18 Fujitsu Ltd Manufacturing method for semiconductor device

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