JP2005340738A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
JP2005340738A
JP2005340738A JP2004161209A JP2004161209A JP2005340738A JP 2005340738 A JP2005340738 A JP 2005340738A JP 2004161209 A JP2004161209 A JP 2004161209A JP 2004161209 A JP2004161209 A JP 2004161209A JP 2005340738 A JP2005340738 A JP 2005340738A
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semiconductor element
fitting
wiring board
sealing resin
semiconductor device
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Sukenori Makari
祐紀 真狩
Nozomi Shimoishizaka
望 下石坂
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004161209A priority Critical patent/JP2005340738A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enable mounting of a semiconductor element on a wiring circuit board at a high positional accuracy by positioning the semiconductor element at a fitting recess and a fitting projection thereof in a self alignment manner to suppress a positional displacement between the semiconductor element and the wiring circuit board. <P>SOLUTION: Sealing resin 16 is coated on a mount region of a semiconductor element 10 on a wiring circuit board 13 having the fitting projection 15 and a bump 14 ((a) in the drawing). The semiconductor element 10 for formation of an electrode 11 and the fitting recess 12 thereon is positioned to be opposed to the wiring circuit board 13 for formation of the bump 14 and the fitting projection 15 ((b) in the drawing). The semiconductor element 10 is mounted on the wiring circuit board 13 ((c) in the drawing). Such a pressure that the element 10 pushes the board 13 and the sealing resin 16 covering the electrode 11 squeezes out, is applied to the semiconductor element 10. Due to fitting of the projection 15 in the recess 12, the element is guided to a most stable position and a relative position thereof with the board is restricted upon heated and joined thereto, thus establishing connection between the electrode 11 and the bump 14 ((d) in the drawing). The semiconductor element 10 can be mounted on the wiring circuit board 13 with a high accuracy exceeding the positional accuracy of a bonding device. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、配線基板上に半導体素子をフリップチップ実装した構造を有する半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device having a structure in which a semiconductor element is flip-chip mounted on a wiring board, and a manufacturing method thereof.

近年、ＬＳＩなどの半導体製品の高速化、低価格化、軽量化、薄型化及び小型化等の実現のため、ＣＳＰ（Chip Scale Package）やＴＣＰ（Tape Carrier Package）などのベアチップ実装に見られるマイクロバンプ接合に対する要求が高まっている。半導体素子と配線基板との接合はバンプを介して行われる。   In recent years, in order to realize high speed, low price, light weight, thinning and downsizing of semiconductor products such as LSIs, micros found in bare chip mounting such as CSP (Chip Scale Package) and TCP (Tape Carrier Package). The demand for bump bonding is increasing. The semiconductor element and the wiring board are joined through bumps.

図５は、従来の半導体装置を示す断面図である。図５において、１は半導体素子、２は半導体素子１上の電極、３は半導体素子１上に形成されたチップ保護膜、４は配線基板、５は配線基板４上に形成されたバンプである。配線基板４は銅などの金属箔を用いた金属配線（図示せず）と半導体素子１との接続を形成するバンプ５とで構成されている。半導体素子１の周囲は半導体素子１と配線基板４との接着強度確保のために封止樹脂６で覆われている。   FIG. 5 is a cross-sectional view showing a conventional semiconductor device. In FIG. 5, 1 is a semiconductor element, 2 is an electrode on the semiconductor element 1, 3 is a chip protection film formed on the semiconductor element 1, 4 is a wiring board, and 5 is a bump formed on the wiring board 4. . The wiring board 4 is composed of metal wiring (not shown) using a metal foil such as copper and bumps 5 that form connections between the semiconductor elements 1. The periphery of the semiconductor element 1 is covered with a sealing resin 6 in order to ensure the adhesive strength between the semiconductor element 1 and the wiring substrate 4.

次に、従来の半導体装置の製造方法について説明する。図６（ａ），（ｂ），（ｃ）は、従来の半導体装置の製造方法を示した断面図である。図６において、１は半導体素子、２は電極、３はチップ保護膜、４は配線基板、５はバンプ、６は封止樹脂、７は実装時に半導体素子１と配線基板４との位置合わせを画像認識により行うためのＴＶカメラである。図６（ａ）に示すように、ＴＶカメラ７の画像認識により半導体素子１と配線基板４の位置合わせを行う。次に、図６（ｂ）に示すように、配線基板４を保持し、半導体素子１の裏面から押圧する。図６（ｃ）に示すように、半導体素子１上の電極２と配線基板４上のバンプ５の接合形成が行われる。   Next, a conventional method for manufacturing a semiconductor device will be described. 6A, 6B, and 6C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device. In FIG. 6, 1 is a semiconductor element, 2 is an electrode, 3 is a chip protection film, 4 is a wiring board, 5 is a bump, 6 is a sealing resin, and 7 is an alignment between the semiconductor element 1 and the wiring board 4 during mounting. This is a TV camera for performing image recognition. As shown in FIG. 6A, the semiconductor element 1 and the wiring board 4 are aligned by the image recognition of the TV camera 7. Next, as shown in FIG. 6B, the wiring board 4 is held and pressed from the back surface of the semiconductor element 1. As shown in FIG. 6C, the electrodes 2 on the semiconductor element 1 and the bumps 5 on the wiring substrate 4 are bonded.

この接合形成には圧接、熱圧着による共晶成長、超音波による酸化膜の除去及び表層原子間結合などの方式を用いる。半導体装置の封止樹脂６は実装前に配線基板上に塗布される場合と、実装後にチップ側面から注入される場合とがある。封止樹脂６に熱硬化性樹脂を用いることで接合形成時もしくは接合形成後の加熱硬化により半導体装置の封止を行う。   For this bonding formation, methods such as pressure welding, eutectic growth by thermocompression bonding, removal of an oxide film by ultrasonic waves, and surface layer interatomic bonding are used. There are a case where the sealing resin 6 of the semiconductor device is applied onto the wiring board before mounting and a case where it is injected from the side surface of the chip after mounting. By using a thermosetting resin for the sealing resin 6, the semiconductor device is sealed at the time of bonding formation or by heat curing after bonding formation.

また、特許文献１に記載される半導体装置の製造方法として、複数の電極を有する配線基板上に、複数の電極を覆う樹脂にてなる接着剤を配設し、複数の電極と相対する複数の突起電極を有する半導体素子と配線基板とを接着剤が所望の粘度とし加熱状態にて圧接することにより、複数の突起電極で接着剤の層を突き破り複数の電極と複数の突起電極とをそれぞれ接触させ、その後に複数の電極と複数の突起電極との接触箇所に超音波振動を印加し、接触箇所に固相拡散にてなる接合部を形成して、半導体素子と配線基板とを接合し、接着剤を硬化させることが記載されている。
特許第３３０８８５５号公報 Further, as a method for manufacturing a semiconductor device described in Patent Document 1, an adhesive made of a resin covering a plurality of electrodes is disposed on a wiring board having a plurality of electrodes, and a plurality of electrodes facing the plurality of electrodes are arranged. By contacting the semiconductor element having a protruding electrode and the wiring board in a heated state with the adhesive having a desired viscosity, the plurality of protruding electrodes pierce the adhesive layer, and the plurality of electrodes and the plurality of protruding electrodes are brought into contact with each other. Then, applying ultrasonic vibration to the contact location between the plurality of electrodes and the plurality of protruding electrodes, forming a joint portion formed by solid phase diffusion at the contact location, and joining the semiconductor element and the wiring board, It is described to cure the adhesive.
Japanese Patent No. 3308855

しかしながら、このような構成の半導体装置とその製造方法には、以下に説明する課題がある。この課題について、図７を用いて説明する。図７（ａ），（ｂ）において、１は半導体素子、２は電極、３はチップ保護膜、４は配線基板、５はバンプ、６は封止樹脂である。   However, the semiconductor device having such a configuration and the manufacturing method thereof have the following problems. This problem will be described with reference to FIG. 7A and 7B, 1 is a semiconductor element, 2 is an electrode, 3 is a chip protection film, 4 is a wiring board, 5 is a bump, and 6 is a sealing resin.

半導体装置を形成するため、配線基板４上に半導体素子１を実装する際には高い位置合わせ精度が要求される。現在使用されているボンディング装置の位置合わせ精度は±５μｍ程度のため、図７（ａ）に示すように、位置ずれによりバンプ５が電極２周囲のチップ保護膜３と接触しチップ保護膜３にダメージを与える。また、バンプ５と電極２の接触面積が不充分となり接続信頼性が低下するなど半導体装置の不良発生の原因となる。さらに、バンプ５と電極２の位置合わせにはＴＶカメラによる画像認識を用いるため、精密な位置合わせを要求するほどコスト，工程，組立時間などが増加して、生産性が低下するという課題があった。   In order to form a semiconductor device, a high alignment accuracy is required when the semiconductor element 1 is mounted on the wiring board 4. Since the alignment accuracy of the bonding apparatus currently used is about ± 5 μm, as shown in FIG. 7A, the bump 5 comes into contact with the chip protective film 3 around the electrode 2 due to the displacement, and the chip protective film 3 is formed. Damage is done. In addition, the contact area between the bump 5 and the electrode 2 becomes insufficient, which causes a failure of the semiconductor device such as a decrease in connection reliability. Furthermore, since the image recognition by the TV camera is used for the alignment of the bump 5 and the electrode 2, there is a problem that the cost, the process, the assembly time, etc. increase as the precise alignment is required, and the productivity decreases. It was.

また、電極２とバンプ５の接合形成、封止樹脂硬化プロセスにおける加熱時には、図７（ｂ）に示すように、半導体素子１と配線基板４の線膨張係数の差により電極２とバンプ５との相対位置のずれが発生する。これにより電極２とバンプ５との接触面積が不充分となり接続信頼性が低下するなど半導体装置の不良発生の原因となるという課題があった。   In addition, when heating in the bonding formation of the electrode 2 and the bump 5 and the sealing resin curing process, as shown in FIG. 7B, the difference between the linear expansion coefficients of the semiconductor element 1 and the wiring substrate 4 causes the electrode 2 and the bump 5 to be The relative position shift occurs. As a result, the contact area between the electrode 2 and the bump 5 becomes insufficient, and there is a problem of causing a defect in the semiconductor device such as a decrease in connection reliability.

本発明は、前記従来技術の問題を解決することに指向するものであり、嵌合用凹部を有する半導体素子と嵌合用凸部を有する配線基板からなり、嵌合用凹部と嵌合用凸部の嵌合による自己整合的な位置合わせを行って、さらに、嵌合された前記嵌合用凹部と前記嵌合用凸部の保持力により前記半導体素子と前記配線基板の間で加熱接合時に発生する位置ずれを抑制して、半導体素子と配線基板が高い位置精度を持って実装された半導体装置及びその製造方法を提供することを目的とする。   The present invention is directed to solving the problems of the prior art, and includes a semiconductor element having a fitting concave portion and a wiring board having a fitting convex portion, and the fitting of the fitting concave portion and the fitting convex portion. In addition, the misalignment that occurs during the heat bonding between the semiconductor element and the wiring board is suppressed by the holding force of the mating concave portion and the mating convex portion. Then, it aims at providing the semiconductor device with which the semiconductor element and the wiring board were mounted with high positional accuracy, and its manufacturing method.

この目的を達成するために、本発明に係る請求項１に記載される半導体装置は、半導体素子と、半導体素子の表面に形成された複数の電極と、半導体素子の表面に形成された嵌合用凹部と、半導体素子の表面に形成された保護樹脂と、配線基板と、配線基板の表面に形成された複数のバンプと、配線基板の表面に形成された嵌合用凸部と、半導体素子と配線基板とを接着する硬化収縮性を有する封止樹脂とを備え、半導体素子の表面の嵌合用凹部と配線基板の表面の嵌合用凸部が相対して嵌合されることで半導体素子と配線基板の相対位置を規制し、封止樹脂の硬化収縮性により複数の電極と複数のバンプの相対位置を保持した構成によって、嵌合された嵌合用凹部と嵌合用凸部は封止樹脂の硬化収縮力により最安定位置で保持され、半導体素子と配線基板との位置が規制され、各部材の線膨張係数の差により発生する位置ずれを抑制できる。   In order to achieve this object, a semiconductor device according to claim 1 of the present invention includes a semiconductor element, a plurality of electrodes formed on the surface of the semiconductor element, and a fitting element formed on the surface of the semiconductor element. A recess, a protective resin formed on the surface of the semiconductor element, a wiring board, a plurality of bumps formed on the surface of the wiring board, a protrusion for fitting formed on the surface of the wiring board, a semiconductor element and a wiring A sealing resin having a curing shrinkage that adheres to the substrate, and the semiconductor device and the wiring substrate are configured by fitting the concave portion for fitting on the surface of the semiconductor element and the convex portion for fitting on the surface of the wiring substrate relative to each other. The fitting recesses and fitting protrusions are cured and shrunk by the sealing resin by a configuration in which the relative positions of the plurality of electrodes and the plurality of bumps are held by the curing shrinkage of the sealing resin. Held in the most stable position by force, semiconductor Children and position of the wiring board is regulated, it is possible to suppress the positional displacement caused by the difference in linear expansion coefficient of each member.

また、請求項２，３に記載される半導体装置は、請求項１の半導体装置において。嵌合用凹部と嵌合用凸部の一方または双方の側面が、斜面または曲面形状を有すること、さらに、封止樹脂が熱硬化性を有し、封止樹脂が硬化時の温度から常温に冷却される際の温度変化による熱収縮により半導体素子と配線基板とを保持する構成によって、嵌合用凹部の底部の幅と嵌合用凸部先端の幅を同程度としても嵌合が容易にでき、実装後の半導体素子と配線基板の相対位置の規制がより強固となり、嵌合による位置ずれ抑制ができ、半導体装置と配線基板の実装時の加熱温度と室温との温度差に起因する封止樹脂の熱収縮により嵌合用凹部と嵌合用凸部がより強固に保持されて位置ずれのより高い抑制ができる。   The semiconductor device according to claim 2 is the semiconductor device according to claim 1. One or both side surfaces of the fitting concave portion and the fitting convex portion have an inclined surface or a curved surface, and the sealing resin has thermosetting properties, and the sealing resin is cooled from the curing temperature to room temperature. The structure that holds the semiconductor element and the wiring board by thermal contraction due to temperature changes during fitting allows easy fitting even when the width of the bottom of the fitting recess is the same as the width of the tip of the fitting protrusion. The regulation of the relative position between the semiconductor element and the wiring board becomes stronger, the position shift due to the fitting can be suppressed, and the heat of the sealing resin caused by the temperature difference between the heating temperature and the room temperature when the semiconductor device and the wiring board are mounted. Due to the contraction, the fitting concave portion and the fitting convex portion are more firmly held, and a higher displacement can be suppressed.

また、請求項４に記載される半導体装置の製造方法は、複数の電極と保護樹脂を備えた半導体素子の表面に嵌合用凹部を形成する工程と、配線基板の表面に複数のバンプを形成する工程と、配線基板の表面に嵌合用凸部を形成する工程と、配線基板の表面に硬化収縮性を有する未硬化の封止樹脂を形成する工程と、配線基板の表面に半導体素子の表面を相対して搭載する工程と、電極とバンプとを接触させると同時に、嵌合用凹部と嵌合用凸部とを相対して嵌合圧接する工程と、未硬化の封止樹脂を硬化させる工程とによって、配線基板上に半導体素子の実装を行うと同時に嵌合用凹部と嵌合用凸部が自己整合的に最安定位置に嵌合され、特別な位置合わせ、嵌合肯定が不要となり生産性を向上、及び半導体素子と配線基板との位置合わせ精度を向上できる。   According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a recess for fitting on a surface of a semiconductor element having a plurality of electrodes and a protective resin; and forming a plurality of bumps on the surface of the wiring board. A step of forming a protrusion for fitting on the surface of the wiring substrate, a step of forming an uncured sealing resin having curing shrinkage on the surface of the wiring substrate, and a surface of the semiconductor element on the surface of the wiring substrate. A step of mounting the electrodes, a step of contacting the electrodes and the bumps at the same time, a step of pressing the fitting concave portions and the fitting convex portions relative to each other, and a step of curing the uncured sealing resin. When mounting the semiconductor element on the wiring board, the concave part for fitting and the convex part for fitting are fitted to the most stable position in a self-aligning manner, and special alignment and fitting affirmation are unnecessary, improving productivity. And alignment accuracy between the semiconductor element and the wiring board. It can be improved.

また、請求項５〜７に記載される半導体装置の製造方法は、請求項４の半導体装置の製造方法において、嵌合用凹部及び嵌合用凸部を形成する工程により、嵌合用凹部及び嵌合用凸部の斜面または曲面形状が形成された側面を接触させながら半導体素子と配線基板とを圧接して、嵌合用凹部と嵌合用凸部との側面をすべりながら最安定位置に自己整合的に嵌合されること、さらに、嵌合用凹部を形成する工程による嵌合用凹部の側面に形成する斜面または曲面形状の形成を、半導体素子表面の保護樹脂の形成と同時に行うこと、また、嵌合用凸部を形成する工程により嵌合用凸部の側面に形成する斜面または曲面形状の形成を、配線基板上のバンプ形成と同時に電解めっきの等方成長を用いて行うことによって、半導体素子と配線基板の実装の際に嵌合用凹部と嵌合用凸部の嵌合が側面をすべりながら行われるため、嵌合がより容易となり、ボンディング装置の位置合わせに要求される精度を低くでき、さらに、熱硬化性樹脂の硬化収縮により半導体素子上の曲面形状を有する嵌合用凹部を容易に作製できるとともに硬化性樹脂は半導体素子の保護樹脂と同時に形成でき、また、等方的めっき成長により配線基板上の曲面形状を有する嵌合用凸部を容易に作製できるとともにバンプと嵌合用凸部と同時に形成して工程を短縮でき、装置コスト、組立時間などを低減することができる。   According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fourth aspect of the present invention, wherein the step of forming the concave portion for fitting and the convex portion for fitting includes the step of forming the concave portion for fitting and the convex portion for fitting. The semiconductor element and the printed circuit board are pressed against each other while the side surface with the slope or curved surface is in contact with each other, and the side surfaces of the mating concave portion and mating convex portion are slid to fit in the most stable position in a self-aligning manner. And forming the slope or curved surface formed on the side surface of the fitting recess by the step of forming the fitting recess simultaneously with the formation of the protective resin on the surface of the semiconductor element. Mounting the semiconductor element and the wiring board by forming the slope or curved surface to be formed on the side surface of the projection for fitting in the forming process using the isotropic growth of electrolytic plating simultaneously with the bump formation on the wiring board In this case, the fitting recess and the fitting protrusion are fitted while sliding on the side surface, so that the fitting becomes easier, the accuracy required for the alignment of the bonding apparatus can be reduced, and the thermosetting resin The concave portion for fitting having a curved shape on the semiconductor element can be easily produced by curing shrinkage, and the curable resin can be formed simultaneously with the protective resin of the semiconductor element, and has a curved shape on the wiring board by isotropic plating growth. The fitting convex portion can be easily manufactured and formed simultaneously with the bump and the fitting convex portion, so that the process can be shortened, and the apparatus cost, assembly time, and the like can be reduced.

以上説明したように、本発明によれば、自己整合的な位置合わせにより高い実装精度を有し、また、半導体素子を配線基板上に加熱接合する際に線膨張係数の差により発生する位置ずれを効果的に抑制できる半導体装置及びその製造方法を提供できるという効果を奏する。   As described above, according to the present invention, there is a high mounting accuracy due to self-alignment alignment, and a positional shift caused by a difference in linear expansion coefficient when a semiconductor element is heated and bonded on a wiring board. It is possible to provide a semiconductor device and a method for manufacturing the same that can effectively suppress the above.

以下、図面を参照して本発明における実施の形態を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図１は本発明の実施の形態１における半導体装置を示す断面図である。図１において、１０は半導体素子、１１は半導体素子１０上に形成された電極、１２は半導体素子１０上の電極１１と半導体素子１０との間に形成された嵌合用凹部である。半導体素子１０上に電極１１の存在しない適当な領域が存在すればその領域に嵌合用凹部１２を形成してもよい。半導体素子１０表面には保護樹脂（図示せず）が形成されている。   FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a semiconductor element, 11 denotes an electrode formed on the semiconductor element 10, and 12 denotes a fitting recess formed between the electrode 11 on the semiconductor element 10 and the semiconductor element 10. If there is an appropriate region where the electrode 11 does not exist on the semiconductor element 10, the fitting recess 12 may be formed in that region. A protective resin (not shown) is formed on the surface of the semiconductor element 10.

また、１３は配線基板で、例えばアルミナ（酸化アルミニウム）、ガラスセラミックス（結晶化ガラス）、ポリイミド（耐熱性高分子）などで形成される。１４は配線基板１３上に形成されたバンプであり、例えばボールボンダ、めっきなどにより形成される。必要であれば２種以上の金属をめっきして積層構造としてもよい。１５は配線基板１３上に形成された嵌合用凸部であり、半導体素子１０上の嵌合用凹部１２と相対した位置に形成される。嵌合用凸部１５と嵌合用凹部１２は最安定位置に嵌合されておりバンプ１４と電極１１の相対位置を固定する役割を果たす。１６は実装された半導体素子１０と配線基板１３を覆う封止樹脂であり、例えば熱硬化型のエポキシ樹脂などが用いられる。封止樹脂１６は硬化収縮性を有し、最安定位置に嵌合された嵌合用凹部１２と嵌合用凸部１５を収縮力により保持している。   Reference numeral 13 denotes a wiring board, which is formed of, for example, alumina (aluminum oxide), glass ceramics (crystallized glass), polyimide (heat-resistant polymer), or the like. Reference numeral 14 denotes a bump formed on the wiring board 13 and is formed by, for example, a ball bonder or plating. If necessary, two or more kinds of metals may be plated to form a laminated structure. Reference numeral 15 denotes a fitting convex portion formed on the wiring substrate 13, which is formed at a position facing the fitting concave portion 12 on the semiconductor element 10. The fitting convex portion 15 and the fitting concave portion 12 are fitted in the most stable position and play a role of fixing the relative positions of the bumps 14 and the electrodes 11. Reference numeral 16 denotes a sealing resin that covers the mounted semiconductor element 10 and the wiring board 13, and for example, a thermosetting epoxy resin or the like is used. The sealing resin 16 has cure shrinkage, and holds the fitting concave portion 12 and the fitting convex portion 15 fitted in the most stable position by the shrinkage force.

次に、前記のような構造を有する半導体装置の製造方法について説明する。図２（ａ）〜（ｄ）は前述した実施の形態１における半導体装置の製造方法を示す断面図である。図２（ａ）〜（ｄ）において、１０は半導体素子、１１は半導体素子１０上に形成された電極、１２は半導体素子１０上の電極１１と半導体素子１０との間に形成された嵌合用凹部である。１３は配線基板、１４は配線基板１３上に形成されたバンプ、１５は配線基板１３上に形成された嵌合用凸部であり、半導体素子１０上の嵌合用凹部１２と相対した位置に形成されている。   Next, a method for manufacturing a semiconductor device having the above structure will be described. 2A to 2D are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment described above. 2A to 2D, 10 is a semiconductor element, 11 is an electrode formed on the semiconductor element 10, and 12 is a fitting formed between the electrode 11 on the semiconductor element 10 and the semiconductor element 10. It is a recess. 13 is a wiring board, 14 is a bump formed on the wiring board 13, and 15 is a fitting convex part formed on the wiring board 13, which is formed at a position facing the fitting concave part 12 on the semiconductor element 10. ing.

まず、図２（ａ）に示すように、嵌合用凸部１５及びバンプ１４を有する配線基板１３上の半導体素子１０実装領域に封止樹脂１６を塗布する。封止樹脂１６を適当な粘度にし、良好な塗布形状を得るために必要ならば配線基板１３もしくは封止樹脂１６に適当な温度を加えてもよい。例えば配線基板１３を８０℃、封止樹脂を３０℃に加熱した後、ポリイミドからなる配線基板１３上に熱硬化性のエポキシ樹脂からなる封止樹脂１６を塗布する。   First, as shown in FIG. 2A, a sealing resin 16 is applied to the mounting region of the semiconductor element 10 on the wiring substrate 13 having the fitting convex portions 15 and the bumps 14. If necessary, an appropriate temperature may be applied to the wiring board 13 or the sealing resin 16 in order to make the sealing resin 16 have an appropriate viscosity and obtain a good coating shape. For example, after the wiring board 13 is heated to 80 ° C. and the sealing resin is heated to 30 ° C., the sealing resin 16 made of a thermosetting epoxy resin is applied on the wiring board 13 made of polyimide.

図２（ｂ）に示すように、表面に電極１１及び嵌合用凹部１２が形成された半導体素子１０とバンプ１４及び嵌合用凸部１５が形成された配線基板１３を相対させて位置合わせを行う。位置合わせ時には装置の位置合わせ精度に起因する位置ずれがあり、現行のボンディング装置では±５μｍ程度の誤差が存在する。   As shown in FIG. 2B, the semiconductor element 10 having the electrode 11 and the fitting concave portion 12 formed on the surface thereof is aligned with the wiring substrate 13 having the bump 14 and the fitting convex portion 15 formed thereon. . At the time of alignment, there is a displacement due to the alignment accuracy of the apparatus, and an error of about ± 5 μm exists in the current bonding apparatus.

図２（ｃ）に示すように、半導体素子１０を配線基板１３上に実装する。実装時に封止樹脂１６の粘度を下げる必要がある場合には配線基板を加熱してもよい。また、半導体素子１０についても必要ならば適当な温度に加熱する。例えば半導体素子１０を２３０℃、配線基板１３を１００℃に加熱し、半導体素子１０を配線基板１３に押し当てる。半導体素子１０に加える圧力は、バンプ１４に要求する変形量や、半導体素子１０上の電極１１を覆う封止樹脂１６を押し退けるために必要な圧力に応じて適宜設定すればよい、例えば、１バンプあたり４０ｇの圧力を加える。   As shown in FIG. 2C, the semiconductor element 10 is mounted on the wiring board 13. If it is necessary to lower the viscosity of the sealing resin 16 during mounting, the wiring board may be heated. The semiconductor element 10 is also heated to an appropriate temperature if necessary. For example, the semiconductor element 10 is heated to 230 ° C. and the wiring board 13 is heated to 100 ° C., and the semiconductor element 10 is pressed against the wiring board 13. The pressure applied to the semiconductor element 10 may be appropriately set according to the amount of deformation required for the bump 14 and the pressure necessary to push away the sealing resin 16 covering the electrode 11 on the semiconductor element 10. Apply 40 g of pressure per round.

また、実装時には図２（ｂ）に示すように、位置合わせ時に発生した位置ずれが存在するが、配線基板１３上の嵌合用凸部１５及び半導体素子１０上の嵌合用凹部１２が嵌合により最安定位置へ誘導され、加熱接合時に半導体素子１０と配線基板１３の相対位置が規制される。このためボンディング装置の限界以上の高い位置精度で半導体素子１０を配線基板１３上に実装できる。また、嵌合された嵌合用凸部と嵌合用凹部は最安定位置で強固に保持され、半導体素子１０と配線基板１３を加熱実装する際に半導体素子１０と配線基板１３の線膨張係数の差により発生する位置ずれを抑制する。   In addition, as shown in FIG. 2B, there is a positional shift that occurs during alignment, but the fitting convex portion 15 on the wiring board 13 and the fitting concave portion 12 on the semiconductor element 10 are fitted. It is guided to the most stable position, and the relative position between the semiconductor element 10 and the wiring board 13 is regulated at the time of heat bonding. For this reason, the semiconductor element 10 can be mounted on the wiring board 13 with high positional accuracy exceeding the limit of the bonding apparatus. In addition, the fitting convex portion and the fitting concave portion that are fitted are firmly held at the most stable position, and the difference between the linear expansion coefficients of the semiconductor element 10 and the wiring board 13 when the semiconductor element 10 and the wiring board 13 are heated and mounted. Suppresses the positional deviation caused by.

図２（ｄ）に示すように、半導体素子１０上の電極１１と配線基板１３上のバンプ１４との接続を形成する。封止樹脂１６に熱硬化性樹脂を用いる場合には、電極１１とバンプ１４の接続形成と同時に封止樹脂１６の加熱硬化を行う。電極１１とバンプ１４の接合には圧接、熱圧着による共晶成長、超音波振動の印加などの方法を用いる。例えば半導体素子１０を２３０℃、配線基板１３を１００℃に保持し、２５ｍｓｅｃ程度の超音波振動を配線基板１３に印加することで固相拡散により電極１１とバンプ１４の接続を形成すると同時に熱硬化性のエポキシ樹脂を硬化させる。   As shown in FIG. 2D, the connection between the electrode 11 on the semiconductor element 10 and the bump 14 on the wiring substrate 13 is formed. When a thermosetting resin is used for the sealing resin 16, the sealing resin 16 is heated and cured simultaneously with the formation of the connection between the electrode 11 and the bump 14. For joining the electrode 11 and the bump 14, methods such as pressure welding, eutectic growth by thermocompression bonding, and application of ultrasonic vibration are used. For example, the semiconductor element 10 is maintained at 230 ° C., the wiring substrate 13 is maintained at 100 ° C., and ultrasonic vibration of about 25 msec is applied to the wiring substrate 13 to form the connection between the electrodes 11 and the bumps 14 by solid phase diffusion and simultaneously thermosetting. Harden epoxy resin.

このように本実施の形態１の半導体装置とその製造方法を用いれば、ボンディング装置の位置精度を越える高い精度での半導体素子１０の配線基板１３への実装が可能となる。また嵌合された嵌合用凹部１２と嵌合用凸部１５により半導体素子１０と配線基板１３の相対位置が固定され、加熱接合時に半導体素子１０と配線基板１３との線膨張係数の違いによりバンプ１４と電極１１の間に発生する位置ずれを抑制しながら接続形成を行うことが可能である。   As described above, if the semiconductor device and the manufacturing method thereof according to the first embodiment are used, the semiconductor element 10 can be mounted on the wiring substrate 13 with high accuracy exceeding the positional accuracy of the bonding device. Further, the relative position between the semiconductor element 10 and the wiring board 13 is fixed by the fitting concave part 12 and the fitting convex part 15, and the bumps 14 are caused by the difference in the linear expansion coefficient between the semiconductor element 10 and the wiring board 13 at the time of heat bonding. It is possible to form the connection while suppressing the positional deviation that occurs between the electrode 11 and the electrode 11.

次に、本発明の実施の形態１における半導体装置を形成する半導体素子の製造方法について説明する。図３は本実施の形態１の半導体素子上の嵌合用凹部の製造方法を示す断面図である。図３において、１０は半導体素子、１１は半導体素子１０上に形成された電極、１２は半導体素子１０上の電極１１と半導体素子１０との間に形成された嵌合用凹部１２である。１８は半導体素子１０の表面を覆う保護樹脂であり、例えばポリイミドなどで形成される。１７は嵌合用凹部１２の材料となる熱硬化性樹脂であり、保護樹脂１８と同じ材料を用いる。   Next, a method for manufacturing a semiconductor element forming the semiconductor device according to the first embodiment of the present invention will be described. FIG. 3 is a cross-sectional view showing a method for manufacturing the recess for fitting on the semiconductor element of the first embodiment. In FIG. 3, 10 is a semiconductor element, 11 is an electrode formed on the semiconductor element 10, and 12 is a fitting recess 12 formed between the electrode 11 on the semiconductor element 10 and the semiconductor element 10. Reference numeral 18 denotes a protective resin that covers the surface of the semiconductor element 10 and is formed of, for example, polyimide. Reference numeral 17 denotes a thermosetting resin which is a material of the fitting recess 12, and the same material as the protective resin 18 is used.

図３（ａ）に示すように、半導体素子１０上の保護樹脂１８と嵌合用凹部１２を形成する領域に熱硬化性樹脂１７を塗布する。次に、図３（ｂ）に示すように、半導体素子１０の加熱を行い、熱硬化性樹脂１７を硬化させる。熱硬化性樹脂１７の硬化の際に発生する硬化収縮力により、保護樹脂１８と嵌合用凹部１２は曲面形状となる。   As shown in FIG. 3A, a thermosetting resin 17 is applied to a region on the semiconductor element 10 where the protective resin 18 and the fitting recess 12 are formed. Next, as shown in FIG. 3B, the semiconductor element 10 is heated to cure the thermosetting resin 17. The protective resin 18 and the fitting recess 12 have a curved shape due to the curing shrinkage generated when the thermosetting resin 17 is cured.

このように、保護樹脂１８の形状にあらかじめ嵌合用凹部１２のパターンを加えることで、工数を増やすことなく容易に嵌合用凹部１２を形成することができる。また、熱硬化性樹脂１７の硬化収縮力により嵌合用凹部１２の曲面形状を容易に作製できる。嵌合用凹部１２に曲面形状を付与することで、嵌合用凹部１２への嵌合用凸部１５の嵌合が容易に起こると同時に半導体素子１０と配線基板１３の位置ずれに対し嵌合用凸部１５を誘導する範囲が広く取れるため、位置合わせを補正できる範囲が大きくなる。   Thus, by adding the pattern of the recess 12 for fitting to the shape of the protective resin 18 in advance, the recess 12 for fitting can be easily formed without increasing the number of steps. Further, the curved shape of the fitting recess 12 can be easily produced by the curing shrinkage force of the thermosetting resin 17. By providing the fitting concave portion 12 with a curved surface, the fitting convex portion 15 can be easily fitted into the fitting concave portion 12, and at the same time, the fitting convex portion 15 against the misalignment between the semiconductor element 10 and the wiring substrate 13. Since the range in which the position is guided is wide, the range in which the alignment can be corrected becomes large.

次に、本発明の実施の形態１における半導体装置を形成する配線基板の製造方法について説明する。図４は本実施の形態１の配線基板の作製方法を示す斜視図（ａ）〜（ｃ）及びその断面図（ｄ）〜（ｆ）である。図４（ａ）〜（ｆ）において、１３は配線基板、１４は配線基板１３上に形成された金属配線１９の所定の位置に形成されたバンプ、１５は配線基板１３上に形成された金属配線１９ａの所定の位置に形成された嵌合用凸部、２０はめっき用マスクパターン２０ａを形成するためのフォトレジストである。   Next, a method for manufacturing a wiring board for forming the semiconductor device according to the first embodiment of the present invention will be described. 4A and 4B are perspective views (a) to (c) and cross-sectional views (d) to (f) showing a method for manufacturing the wiring board of the first embodiment. 4A to 4F, 13 is a wiring board, 14 is a bump formed at a predetermined position of a metal wiring 19 formed on the wiring board 13, and 15 is a metal formed on the wiring board 13. A fitting convex portion 20 formed at a predetermined position of the wiring 19a is a photoresist for forming a plating mask pattern 20a.

まず、図４（ａ），（ｄ）に示すように、配線基板１３上には電極と接合用のバンプ１４のための金属配線１９と嵌合用凸部１５作製のための金属配線１９ａが形成されている。金属配線１９，１９ａの形成された配線基板１３上にフォトレジスト２０を塗布する。   First, as shown in FIGS. 4A and 4D, a metal wiring 19 for forming an electrode and a bonding bump 14 and a metal wiring 19a for forming a fitting projection 15 are formed on the wiring board 13. Has been. A photoresist 20 is applied on the wiring substrate 13 on which the metal wirings 19 and 19a are formed.

図４（ｂ），（ｅ）に示すように、フォトレジスト２０の露光、現像により配線基板１３上のバンプ１４、嵌合用凸部１５を形成する領域を開口しためっき用マスクパターン２０ａを作製する。めっき用マスクパターン２０ａは複数の導体配線にまたがった開口部を有している。   As shown in FIGS. 4B and 4E, a plating mask pattern 20a having an opening in the region for forming the bumps 14 and the fitting convex portions 15 on the wiring substrate 13 is produced by exposing and developing the photoresist 20. . The plating mask pattern 20a has an opening extending over a plurality of conductor wirings.

図４（ｃ），（ｆ）に示すように、等方性の電解めっきを行い金属配線１９及び１９ａ上に曲面形状を有するバンプ１４及び嵌合用凸部１５を作製する。めっき用マスクパターン２０ａが複数の配線にまたがっているため、隣接配線間でのバンプ１４の相対位置は極めて高い精度を有する。また、等方性のめっき成長を用いることで、バンプ１４と嵌合用凸部１５を等しい高さで作製することが可能となる。   As shown in FIGS. 4C and 4F, isotropic electrolytic plating is performed to produce bumps 14 having a curved shape and fitting convex portions 15 on the metal wirings 19 and 19a. Since the plating mask pattern 20a extends over a plurality of wirings, the relative positions of the bumps 14 between adjacent wirings have extremely high accuracy. Further, by using isotropic plating growth, the bumps 14 and the fitting convex portions 15 can be produced at the same height.

以上のように、形成した半導体素子１０と配線基板１３により加熱接合時にバンプ１４と電極１１の間に発生する位置ずれを抑制しながら接続形成を行うことができる。   As described above, the formed semiconductor element 10 and the wiring substrate 13 can be connected while suppressing a positional shift that occurs between the bump 14 and the electrode 11 during heat bonding.

本発明に係る半導体装置及びその製造方法は、自己整合的な位置合わせにより高い実装精度を有し、また、半導体素子を配線基板上に加熱接合する際に線膨張係数の差により発生する位置ずれを効果的に抑制でき、配線基板上に半導体素子をフリップチップ実装した構造を有する半導体装置及びその製造方法に有用である。   The semiconductor device and the manufacturing method thereof according to the present invention have high mounting accuracy due to self-alignment alignment, and misalignment caused by a difference in linear expansion coefficient when the semiconductor element is heated and bonded on the wiring board. It is useful for a semiconductor device having a structure in which a semiconductor element is flip-chip mounted on a wiring board and a method for manufacturing the same.

本発明の実施の形態１における半導体装置を示す断面及び部分拡大図Sectional and partially enlarged view showing the semiconductor device according to the first embodiment of the present invention. 本発明の実施の形態１における半導体装置の製造方法を示す断面図（ａ）〜（ｄ）Sectional drawing (a)-(d) which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention 本発明の実施の形態１における半導体素子の製造方法を示す断面図（ａ），（ｂ）Sectional drawing (a) which shows the manufacturing method of the semiconductor element in Embodiment 1 of this invention, (b) 本実施の形態１の配線基板の作製方法を示す斜視図（ａ）〜（ｃ）及びその断面図（ｄ）〜（ｆ）Perspective views (a) to (c) and cross-sectional views (d) to (f) showing a method for manufacturing the wiring board according to the first embodiment. 従来の半導体装置の構造を示す断面図Sectional view showing the structure of a conventional semiconductor device 従来の半導体装置の製造方法を示す断面図（ａ）〜（ｃ）Sectional drawing (a)-(c) which shows the manufacturing method of the conventional semiconductor device 従来の半導体装置の製造方法における位置合わせのずれ、線膨張係数によるずれを示す図The figure which shows the shift | offset | difference of the alignment in the manufacturing method of the conventional semiconductor device, and the shift | offset | difference by a linear expansion coefficient

符号の説明Explanation of symbols

１，１０ 半導体素子
２，１１ 電極
３ チップ保護膜
４，１３ 配線基板
５，１４ バンプ
６，１６ 封止樹脂
７ ＴＶカメラ
１２ 嵌合用凹部
１５ 嵌合用凸部
１７ 熱硬化性樹脂
１８ 保護樹脂
１９，１９ａ 金属配線
２０ フォトレジスト
２０ａ めっき用マスクパターン DESCRIPTION OF SYMBOLS 1,10 Semiconductor element 2,11 Electrode 3 Chip protective film 4,13 Wiring board 5,14 Bump 6,16 Sealing resin 7 TV camera 12 Fitting recessed part 15 Fitting convex part 17 Thermosetting resin 18 Protective resin 19, 19a Metal wiring 20 Photoresist 20a Plating mask pattern

Claims (7)

半導体素子と、前記半導体素子の表面に形成された複数の電極と、前記半導体素子の表面に形成された嵌合用凹部と、前記半導体素子の表面に形成された保護樹脂と、配線基板と、前記配線基板の表面に形成された複数のバンプと、前記配線基板の表面に形成された嵌合用凸部と、前記半導体素子と前記配線基板とを接着する硬化収縮性を有する封止樹脂とを備え、
前記半導体素子の表面の前記嵌合用凹部と前記配線基板の表面の前記嵌合用凸部が相対して嵌合されることで前記半導体素子と前記配線基板の相対位置を規制し、前記封止樹脂の硬化収縮性により前記複数の電極と前記複数のバンプの相対位置を保持したことを特徴とする半導体装置。 A semiconductor element; a plurality of electrodes formed on the surface of the semiconductor element; a recess for fitting formed on the surface of the semiconductor element; a protective resin formed on the surface of the semiconductor element; a wiring board; A plurality of bumps formed on the surface of the wiring substrate; a fitting convex formed on the surface of the wiring substrate; and a sealing resin having a curing shrinkage that bonds the semiconductor element and the wiring substrate. ,
The fitting recess on the surface of the semiconductor element and the fitting protrusion on the surface of the wiring board are fitted to each other so as to regulate the relative position between the semiconductor element and the wiring board, and the sealing resin A semiconductor device characterized in that the relative positions of the plurality of electrodes and the plurality of bumps are held by the curing shrinkage. 前記嵌合用凹部と前記嵌合用凸部の一方または双方の側面が、斜面または曲面形状を有することを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein one or both side surfaces of the fitting concave portion and the fitting convex portion have an inclined surface or a curved shape. 前記封止樹脂が熱硬化性を有し、前記封止樹脂が硬化時の温度から常温に冷却される際の温度変化による熱収縮により半導体素子と配線基板とを保持することを特徴とする請求項１または２記載の半導体装置。   The sealing resin has a thermosetting property, and the semiconductor element and the wiring board are held by heat shrinkage due to a temperature change when the sealing resin is cooled from a curing temperature to room temperature. Item 3. The semiconductor device according to Item 1 or 2. 複数の電極と保護樹脂を備えた半導体素子の表面に嵌合用凹部を形成する工程と、配線基板の表面に複数のバンプを形成する工程と、配線基板の表面に嵌合用凸部を形成する工程と、前記配線基板の表面に硬化収縮性を有する未硬化の封止樹脂を形成する工程と、前記配線基板の表面に前記半導体素子の表面を相対して搭載する工程と、前記電極と前記バンプとを接触させると同時に、前記嵌合用凹部と前記嵌合用凸部とを相対して嵌合圧接する工程と、前記未硬化の封止樹脂を硬化させる工程とからなることを特徴とする半導体装置の製造方法。   A step of forming a concave portion for fitting on a surface of a semiconductor element having a plurality of electrodes and a protective resin, a step of forming a plurality of bumps on the surface of the wiring substrate, and a step of forming a convex portion for fitting on the surface of the wiring substrate A step of forming an uncured sealing resin having curing shrinkage on the surface of the wiring substrate, a step of mounting the surface of the semiconductor element relative to the surface of the wiring substrate, the electrode and the bump And a step of pressing the fitting recess and the fitting protrusion relative to each other and a step of curing the uncured sealing resin. Manufacturing method. 前記嵌合用凹部及び前記嵌合用凸部を形成する工程により、前記嵌合用凹部及び前記嵌合用凸部の斜面または曲面形状が形成された側面を接触させながら前記半導体素子と前記配線基板とを圧接して、前記嵌合用凹部と前記嵌合用凸部との側面をすべりながら最安定位置に自己整合的に嵌合されることを特徴とする請求項４記載の半導体装置の製造方法。   In the step of forming the fitting recess and the fitting protrusion, the semiconductor element and the wiring board are pressed against each other while contacting the side surface on which the slope or curved surface of the fitting recess and the fitting protrusion is formed. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the fitting recesses and the fitting protrusions are fitted in a self-aligning manner at the most stable position while sliding side surfaces thereof. 前記嵌合用凹部を形成する工程による前記嵌合用凹部の側面に形成する斜面または曲面形状の形成を、半導体素子表面の保護樹脂の形成と同時に行うことを特徴とする請求項４または５記載の半導体装置の製造方法。   6. The semiconductor according to claim 4, wherein the formation of the slope or curved surface formed on the side surface of the fitting recess by the step of forming the fitting recess is performed simultaneously with the formation of the protective resin on the surface of the semiconductor element. Device manufacturing method. 前記嵌合用凸部を形成する工程により前記嵌合用凸部の側面に形成する斜面または曲面形状の形成を、配線基板上のバンプ形成と同時に電解めっきの等方成長を用いて行うことを特徴とする請求項４または５記載の半導体装置の製造方法。   The formation of the slope or curved surface formed on the side surface of the fitting convex portion by the step of forming the fitting convex portion is performed using isotropic growth of electrolytic plating simultaneously with the bump formation on the wiring board. A method for manufacturing a semiconductor device according to claim 4 or 5.
JP2004161209A 2004-05-31 2004-05-31 Semiconductor device and method for manufacturing the same Pending JP2005340738A (en)

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WO2014136241A1 (en) * 2013-03-07 2014-09-12 東北マイクロテック株式会社 Laminate and method of producing same
KR20150124651A (en) * 2014-04-29 2015-11-06 엘에스산전 주식회사 Assembling tool for power semiconductor module
JP2017126645A (en) * 2016-01-13 2017-07-20 セイコーインスツル株式会社 Electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014136241A1 (en) * 2013-03-07 2014-09-12 東北マイクロテック株式会社 Laminate and method of producing same
US9219047B2 (en) 2013-03-07 2015-12-22 Tohoku-Microtec Co., Ltd Stacked device and method of manufacturing the same
JPWO2014136241A1 (en) * 2013-03-07 2017-02-09 東北マイクロテック株式会社 Laminated body and method for producing the same
KR20150124651A (en) * 2014-04-29 2015-11-06 엘에스산전 주식회사 Assembling tool for power semiconductor module
KR101589371B1 (en) 2014-04-29 2016-01-27 엘에스산전 주식회사 Assembling tool for power semiconductor module
JP2017126645A (en) * 2016-01-13 2017-07-20 セイコーインスツル株式会社 Electronic component

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