JP2000357714A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2000357714A JP2000357714A JP16954099A JP16954099A JP2000357714A JP 2000357714 A JP2000357714 A JP 2000357714A JP 16954099 A JP16954099 A JP 16954099A JP 16954099 A JP16954099 A JP 16954099A JP 2000357714 A JP2000357714 A JP 2000357714A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- package
- thermoplastic resin
- heating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体素子を基
板上に接合する半導体装置及びその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for bonding a semiconductor element on a substrate and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、高密度実装化に伴う半導体装置と
して、半導体チップと同等サイズのＬＳＩパッケージ、
即ち、ＣＳＰ(Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ)
、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）が注目
されている。従来、この種のＣＳＰとして、基板の配線
パッドに半導体チップのはんだバンプを位置決め・接合
した後、基板と半導体チップとの接合強度を向上させる
ために、半導体チップの周辺部から熱硬化性樹脂のアン
ダーフィル剤をはんだバンプ間に充填し、熱硬化させて
いるものが知られている。しかし、かかる熱硬化性樹脂
をはんだバンプ間に充填するには、毛細管現象によるた
め、熱硬化性樹脂を短時間にはんだバンプ間に充填する
ことは難しく、十分に充填するには相当の時間を要する
ため、生産性の点で問題があるほか、基板と半導体チッ
プとの接続強度にもばらつきを生じ信頼性の点でも問題
があった。2. Description of the Related Art Conventionally, as a semiconductor device accompanying high-density mounting, an LSI package having the same size as a semiconductor chip,
That is, CSP (Chip Scale Package)
, BGA (Ball Grid Array) has been attracting attention. Conventionally, as a CSP of this type, after positioning and joining a solder bump of a semiconductor chip to a wiring pad of a board, a thermosetting resin is formed from the periphery of the semiconductor chip in order to improve the bonding strength between the board and the semiconductor chip. It is known that an underfill agent is filled between solder bumps and thermally cured. However, it is difficult to fill the thermosetting resin between the solder bumps in a short time due to the capillary phenomenon in filling the thermosetting resin between the solder bumps. Therefore, there is a problem in terms of productivity, and there is also a problem in terms of reliability due to variations in connection strength between the substrate and the semiconductor chip.
【０００３】一方、従来の半導体チップとパッケージ基
台とをフリップチップ接続により接合してなるＣＳＰと
して、例えば特開平９−２１３７３５号公報には、半導
体チップ及びパッケージ基台の各表面にそれぞれ硬化剤
及び主剤を塗布し、半導体チップとパッケージ基台を位
置合わせ・フェイス・ダウン接合する際に、硬化剤と主
剤を混合して両者の間に接着層を充填することにより、
両者の隙間に樹脂を充填することを不要にするものが記
載されている。しかし、かかる場合、硬化剤と主剤とを
徐々に混合しながら半導体チップとパッケージ基台との
間に接着層を充填するために生産性の点で問題があるほ
か、硬化剤及び主剤の塗布工程とフェイス・ダウン接合
工程とが一連であるために工程に制約があり、作業性の
点でも問題があった。On the other hand, as a conventional CSP in which a semiconductor chip and a package base are joined by flip-chip connection, for example, Japanese Unexamined Patent Publication No. 9-21735 discloses a curing agent on each surface of the semiconductor chip and the package base. When applying the main component and aligning the semiconductor chip and the package base and performing face-down bonding, by mixing the curing agent and the main component and filling the adhesive layer between them,
It is described that there is no need to fill a resin between the gaps. However, in such a case, there is a problem in terms of productivity because the adhesive layer is filled between the semiconductor chip and the package base while gradually mixing the curing agent and the main agent, and the coating process of the curing agent and the main agent is also required. Since the series of steps and the face-down joining process are limited, the process is limited, and there is also a problem in workability.
【０００４】[0004]
【発明が解決しようとする課題】このように、従来の半
導体装置及びその製造方法は、熱硬化性樹脂をはんだバ
ンプ間に充填するのに相当の時間を要するため、生産性
の点で問題があるほか、基板と半導体チップとの接続強
度にもばらつきを生じ信頼性の点でも問題があった。ま
た、硬化剤と主剤とを徐々に混合しながら半導体チップ
とパッケージ基台との間に接着層を充填するために生産
性等の点でも問題があった。As described above, the conventional semiconductor device and the method for manufacturing the same require a considerable amount of time to fill the space between the solder bumps with the thermosetting resin. In addition, the connection strength between the substrate and the semiconductor chip also fluctuates, causing a problem in reliability. In addition, since the adhesive layer is filled between the semiconductor chip and the package base while gradually mixing the curing agent and the base material, there is a problem in productivity and the like.
【０００５】そこで、この発明はかかる問題点を解決す
るためになされたものであり、生産性・作業性が高く、
基板と半導体チップとの接着強度も良い新規な半導体装
置及びその製造方法を提供することを目的とする。Therefore, the present invention has been made to solve such a problem, and has high productivity and workability.
It is an object of the present invention to provide a novel semiconductor device having good adhesive strength between a substrate and a semiconductor chip and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】この発明の請求項１に係
る半導体装置は、複数の配線パッドが設けられた基板
と、この基板に対向配置されたパッケージ基板と、この
パッケージ基板上の上記基板側に互いに間隔を隔てて設
けられた複数のボールグリッドと、上記パッケージ基板
の上記基板側と反対側に設けられた半導体チップと、上
記基板と上記パッケージ基板との間に充填された接着樹
脂とを備え、この接着樹脂は、上記パッケージ基板上の
上記ボールグリッド上に塗布し、仮硬化時における加熱
により上記複数のボールグリッドの間隔に充填して仮硬
化状態とし、この仮硬化状態でそれぞれ上記基板の配線
パッドに接続するリフロー時の加熱により、上記仮硬化
状態を溶融して上記基板と上記パッケージ基板との間に
充填されるようにしたものである。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate provided with a plurality of wiring pads; a package substrate opposed to the substrate; and the substrate on the package substrate. A plurality of ball grids provided at intervals on the side, a semiconductor chip provided on the opposite side of the package substrate from the substrate side, and an adhesive resin filled between the substrate and the package substrate. The adhesive resin is applied on the ball grid on the package substrate, and is filled in the space between the plurality of ball grids by heating at the time of temporary curing to form a temporary cured state. By heating at the time of reflow connecting to the wiring pad of the substrate, the pre-cured state is melted and filled between the substrate and the package substrate. It is intended.
【０００７】この発明の請求項２に係る半導体装置は、
複数の配線パッドが設けられたパッケージ基台と、この
パッケージ基台上に配設された半導体チップと、この半
導体チップの上記パッケージ基台側に互いに間隔を隔て
て設けられた複数のバンプと、上記半導体素子と上記パ
ッケージ基台との間に充填された接着樹脂とを備え、上
記半導体チップ上の上記バンプ上に塗布し、仮硬化時に
おける加熱により上記バンプの間隔に充填して仮硬化状
態とし、この仮硬化状態で上記半導体チップの複数のバ
ンプをそれぞれ上記パッケージ基台上の配線パッドに接
合するフェイスダウンボンデイング時の加熱により、上
記仮硬化状態を溶融して上記パッケージ基台と上記半導
体チップとの間に充填されるようにしたものである。According to a second aspect of the present invention, there is provided a semiconductor device comprising:
A package base provided with a plurality of wiring pads, a semiconductor chip provided on the package base, and a plurality of bumps provided at intervals on the package base side of the semiconductor chip; An adhesive resin filled between the semiconductor element and the package base, applied to the bumps on the semiconductor chip, and filled in the gaps of the bumps by heating during temporary curing to be in a temporarily cured state; In the pre-cured state, the plurality of bumps of the semiconductor chip are respectively bonded to the wiring pads on the package base by heating during face-down bonding, whereby the pre-cured state is melted to melt the package base and the semiconductor. It is designed to be filled between the chip and the chip.
【０００８】この発明の請求項３に係る半導体装置は、
上記ボールグリッド又は上記バンプの上面が露出するよ
うに上記接着樹脂を上記パッケージ基板上又は上記半導
体素子上に塗布したことを特徴とする請求項１又は２に
記載のものである。According to a third aspect of the present invention, there is provided a semiconductor device comprising:
3. The method according to claim 1, wherein the adhesive resin is applied on the package substrate or the semiconductor element such that an upper surface of the ball grid or the bump is exposed.
【０００９】この発明の請求項４に係る半導体装置は、
上記接着樹脂が、一液性の熱可塑性樹脂であることを特
徴とする請求項１又は２に記載の半導体装置。According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
The semiconductor device according to claim 1, wherein the adhesive resin is a one-component thermoplastic resin.
【００１０】この発明の請求項５に係る半導体装置の製
造方法は、半導体素子に熱可塑性樹脂を塗布する塗布工
程と、上記熱可塑性樹脂を加熱して仮硬化状態にさせる
仮硬化工程と、この仮硬化工程の後に、上記半導体素子
の仮硬化状態の熱可塑性樹脂をそれぞれ基板上に位置決
めする位置決め工程と、この位置決め工程後の加熱によ
り、上記熱可塑性樹脂の仮硬化状態を溶融して上記半導
体素子と上記基板との間にそれぞれ熱可塑性樹脂を充填
する充填工程とを備えたものである。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of applying a thermoplastic resin to a semiconductor element; a step of heating the thermoplastic resin to a temporary cured state; After the pre-curing step, a positioning step of positioning the thermoplastic resin in the pre-cured state of the semiconductor element on the substrate, and heating after the positioning step, the pre-cured state of the thermoplastic resin is melted to melt the semiconductor. A filling step of filling a thermoplastic resin between the element and the substrate.
【００１１】この発明の請求項６に係る半導体装置の製
造方法は、上記充填工程における加熱が、リフロー時の
加熱であって、上記熱可塑性樹脂の溶融により上記半導
体素子の外周部分においてフィレットを形成するように
したことを特徴とする請求項５に記載のものである。According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the heating in the filling step is heating during reflow, and a fillet is formed at an outer peripheral portion of the semiconductor element by melting the thermoplastic resin. According to a fifth aspect of the present invention, there is provided:
【００１２】[0012]
【発明の実施の形態１】以下、この発明の実施の形態１
に係る半導体装置について説明する。図１（ａ）（ｂ）
（ｃ）は、この実施の形態１に係る半導体装置の製造方
法を説明するための製造フロー図である。図１（ａ）に
おいて、１はパッケージ基板で、その一主面には半導体
チップ２を設け、その他主面には複数のはんだバンプ３
が間隔を隔てて設けられている。４は熱可塑性樹脂で、
熱により溶ける熱可塑性の構造を採るエポキシ樹脂であ
り、複数のはんだバンプ３の中央部にノズル５によって
塗布する。この熱可塑性樹脂４の塗布量は、図１（ａ）
に示すように、はんだバンプ３の上面が出る程度に塗布
する。熱可塑性樹脂４をはんだバンプ３上に塗布した
後、加熱装置（図示せず）内で熱可塑性樹脂４を１００
℃前後の加熱により、この仮硬化時に熱可塑性樹脂４を
軟化して複数のはんだバンプ３の間隔に充填させる。こ
のように、熱可塑性樹脂４を仮硬化状態とさせるのは、
図１（ａ）に示すアンダーフィル工程は組み立て工程の
終盤であることが多いため、熱可塑性樹脂４の未硬化の
ままであると作業性が悪いためである。Embodiment 1 Hereinafter, Embodiment 1 of the present invention will be described.
Will be described. FIG. 1 (a) (b)
(C) is a manufacturing flowchart for explaining the method for manufacturing the semiconductor device according to the first embodiment. In FIG. 1A, reference numeral 1 denotes a package substrate having a semiconductor chip 2 provided on one main surface and a plurality of solder bumps 3 provided on the other main surface.
Are provided at intervals. 4 is a thermoplastic resin,
It is an epoxy resin having a thermoplastic structure that is melted by heat, and is applied to the center of a plurality of solder bumps 3 by a nozzle 5. The application amount of the thermoplastic resin 4 is as shown in FIG.
As shown in (1), the solder bump 3 is applied so that the upper surface of the solder bump 3 comes out. After applying the thermoplastic resin 4 on the solder bumps 3, the thermoplastic resin 4 is applied in a heating device (not shown) for 100 hours.
The thermoplastic resin 4 is softened at the time of the temporary curing by heating at about ℃, and is filled in the space between the plurality of solder bumps 3. As described above, the thermoplastic resin 4 is brought into the pre-cured state because:
This is because the underfill step shown in FIG. 1A is often at the end of the assembling step, and the workability is poor if the thermoplastic resin 4 remains uncured.
【００１３】図１（ｂ）において、６は基板で、その上
に複数の配線パッド７が設けられている。これらの配線
パッド７上にはそれぞれクリームはんだ８が設けられて
いる。基板６上の各配線パッド７及びクリームはんだ８
上に半導体チップ２の各はんだバンプ３が配置するよう
に位置決めをする。この位置決めは、半導体チップ２と
基板６のターゲットを認識して位置合わせをする。この
とき、熱可塑性樹脂４を仮硬化状態としているので、半
導体チップ２とパッケージ基板１とは接合され、その後
の製造工程で外れることはほとんどない。In FIG. 1B, reference numeral 6 denotes a substrate on which a plurality of wiring pads 7 are provided. A cream solder 8 is provided on each of these wiring pads 7. Each wiring pad 7 on substrate 6 and cream solder 8
Positioning is performed so that the solder bumps 3 of the semiconductor chip 2 are arranged thereon. This positioning is performed by recognizing the target of the semiconductor chip 2 and the target of the substrate 6. At this time, since the thermoplastic resin 4 is in a pre-cured state, the semiconductor chip 2 and the package substrate 1 are joined and hardly separated in the subsequent manufacturing process.
【００１４】図１（ｃ）において、半導体チップ２のは
んだバンプ３が基板６の配線パッド７にそれぞれ接続す
るリフロー時の熱により、上記仮硬化状態の熱可塑性樹
脂４を再度溶融させ、パッケージ基板１と基板６との間
に充填させる。このとき、溶融した熱可塑性樹脂４は、
半導体チップ２の外周部分でフィレットを形成してパッ
ケージ基板１と基板６との接着強度を確保される。In FIG. 1 (c), the heat during reflow in which the solder bumps 3 of the semiconductor chip 2 are connected to the wiring pads 7 of the substrate 6, respectively, melts the temporarily cured thermoplastic resin 4 again, and 1 and the substrate 6. At this time, the molten thermoplastic resin 4
A fillet is formed at the outer peripheral portion of the semiconductor chip 2 to secure the adhesive strength between the package substrate 1 and the substrate 6.
【００１５】ここに、図１（ａ）において、熱可塑性樹
脂４の塗布量が多すぎると、はんだバンプ３と基板６の
配線パッド７及びクリームはんだ８との間に熱可塑性樹
脂４が入り込んで、これらの間をはんだ接合できない場
合が起こりうる。一方、この塗布量が少なすぎると、パ
ッケージ基板１と基板６との間においてはんだバンプ３
間に十分に熱可塑性樹脂４を充填することができず、ま
た、半導体チップ２の外周部分でフィレットを形成しな
いため、十分な接合強度も得られない。このため、熱可
塑性樹脂４の塗布量は精密に制御する必要があるが、は
んだバンプ３の径及び配列ピッチによって最適な塗布量
は異なる。ここでは、図１(ａ)に示すように、はんだバ
ンプ３の上面がやや出る程度とする。Here, in FIG. 1A, if the applied amount of the thermoplastic resin 4 is too large, the thermoplastic resin 4 enters between the solder bumps 3 and the wiring pads 7 and the cream solder 8 of the substrate 6. In some cases, soldering cannot be performed between them. On the other hand, if the coating amount is too small, the solder bumps 3 between the package substrate 1 and the substrate 6
Since the thermoplastic resin 4 cannot be sufficiently filled in between, and no fillet is formed on the outer peripheral portion of the semiconductor chip 2, sufficient bonding strength cannot be obtained. For this reason, it is necessary to precisely control the amount of the thermoplastic resin 4 to be applied, but the optimum amount of the thermoplastic resin 4 varies depending on the diameter and the arrangement pitch of the solder bumps 3. Here, as shown in FIG. 1A, the upper surface of the solder bump 3 is slightly exposed.
【００１６】[0016]
【発明の実施の形態２】以下、この発明の実施の形態２
に係る半導体装置について説明する。図２（ａ）（ｂ）
（ｃ）は、この実施の形態２に係る半導体装置の製造方
法を説明するための製造フロー図である。図２（ａ）に
おいて、１０は半導体チップ（半導体素子）で、一主面
に複数の金バンプ１１を形成する。ノズル５によって金
バンプ１１の上面から熱可塑性樹脂１２を塗布する。こ
の塗布量は、実施の形態１の場合と同様である。また、
熱可塑性樹脂１２は、実施の形態１と同様なエポキシ樹
脂等である。次いで、半導体チップ１０上に熱可塑性樹
脂１２を充填した側を上向きにして、図示しない支持装
置及び搬送装置により、上記加熱装置に搬入して熱可塑
性樹脂１２を約１００℃の加熱により軟化させ、金バン
プ１１の間隔に充填させて仮硬化状態とする。Embodiment 2 Hereinafter, Embodiment 2 of the present invention will be described.
Will be described. FIGS. 2A and 2B
(C) is a manufacturing flowchart for explaining the method for manufacturing the semiconductor device according to the second embodiment. In FIG. 2A, a semiconductor chip (semiconductor element) 10 has a plurality of gold bumps 11 formed on one main surface. The thermoplastic resin 12 is applied from the upper surface of the gold bump 11 by the nozzle 5. This application amount is the same as in the first embodiment. Also,
The thermoplastic resin 12 is an epoxy resin or the like as in the first embodiment. Next, the semiconductor chip 10 is filled with the thermoplastic resin 12 with the side facing upward, and is loaded into the heating device by a support device and a transfer device (not shown) to soften the thermoplastic resin 12 by heating at about 100 ° C. The space between the gold bumps 11 is filled to form a temporary hardened state.
【００１７】図２（ｂ）において、半導体チップ１０の
仮硬化状態とした熱可塑性樹脂１２を下向きにして、パ
ッケージ基台１３上に形成された配線パッド１４側に配
置し、半導体チップ１０の金バンプ１１がパッケージ基
台１３の配線パッド１４上になるように位置決めする。
この位置決め工程は、実施の形態１の場合と同様であ
る。In FIG. 2B, the thermoplastic resin 12 in the pre-cured state of the semiconductor chip 10 is placed face down on the side of the wiring pad 14 formed on the package base 13, and the gold of the semiconductor chip 10 is The bump 11 is positioned so as to be on the wiring pad 14 of the package base 13.
This positioning step is the same as in the first embodiment.
【００１８】図２（ｃ）において、半導体チップ１０の
金バンプ１１をパッケージ基台１３の配線パッド１４に
接続するフェイスダウンボンデイング時の加圧及び加熱
（約２００℃で、約１５秒間）により、仮硬化された熱
可塑性樹脂１２を溶融し、半導体チップ１０とパッケー
ジ基台１３との間に充填する。熱可塑性樹脂１２は、半
導体チップ１０の外周部分でフィレットを形成してこれ
らの接合強度を確保している。In FIG. 2C, pressure and heating (about 200 ° C. for about 15 seconds) during face-down bonding for connecting the gold bumps 11 of the semiconductor chip 10 to the wiring pads 14 of the package base 13 are performed. The temporarily cured thermoplastic resin 12 is melted and filled between the semiconductor chip 10 and the package base 13. The thermoplastic resin 12 forms a fillet at the outer peripheral portion of the semiconductor chip 10 to secure the bonding strength between them.
【００１９】[0019]
【発明の実施の形態３】以下、この発明の実施の形態３
に係る半導体装置の製造方法について図３を用いて説明
する。図３（ａ）（ｂ）（ｃ）は半導体装置の製造フロ
ー図である。図３（ａ）において、１５は受動体素子等
の半導体素子で、その一主面に熱可塑性樹脂１６をノズ
ル５によって塗布する。この塗布された熱可塑性樹脂１
６を加熱により仮硬化させる。この仮硬化させる条件
は、実施の形態１及び２の場合と同様である。Embodiment 3 Hereinafter, Embodiment 3 of the present invention will be described.
The method for manufacturing a semiconductor device according to the above will be described with reference to FIG. FIGS. 3A, 3B, and 3C are manufacturing flowcharts of the semiconductor device. In FIG. 3A, reference numeral 15 denotes a semiconductor element such as a passive element, and a thermoplastic resin 16 is applied to one main surface of the semiconductor element by the nozzle 5. This applied thermoplastic resin 1
6 is temporarily cured by heating. The conditions for the temporary curing are the same as those in the first and second embodiments.
【００２０】図３（ｂ）において、半導体素子１５の熱
可塑性樹脂１６を下向きにして基板１７上に配置・位置
決めする。このとき、かかる半導体素子１５を基板１７
上に複数個配置・位置決めする。このように熱可塑性樹
脂１６を仮硬化させるのは、熱可塑性樹脂１６が未硬化
のままであると、実装工程において複数の半導体素子１
５及び実装部品等を取り扱うので、作業性が極めて悪い
ためである。In FIG. 3B, the thermoplastic resin 16 of the semiconductor element 15 is arranged and positioned on the substrate 17 with the thermoplastic resin 16 facing downward. At this time, the semiconductor element 15 is connected to the substrate 17.
Arrange and position multiple units on top. The reason why the thermoplastic resin 16 is temporarily cured in this way is that if the thermoplastic resin 16 remains uncured, a plurality of semiconductor elements 1 are mounted in the mounting process.
This is because workability is extremely poor because the device 5 and mounted components are handled.
【００２１】次いで、図３（ｃ）において、仮硬化させ
た熱可塑性樹脂１６をリフロー時の加熱により溶融させ
て、半導体素子１５と基板１７との間に充填させる。な
お、同様な方法によって一個の半導体素子１５を基板１
７上に接合させることも可能である。また、リフロー時
の加熱により溶融した熱可塑性樹脂１６は、半導体素子
１５の外周部分でフィレットを形成して接合強度が確保
される。Next, in FIG. 3C, the temporarily cured thermoplastic resin 16 is melted by heating during reflow, and is filled between the semiconductor element 15 and the substrate 17. Note that one semiconductor element 15 is connected to the substrate 1 by the same method.
7, it is also possible to join. Further, the thermoplastic resin 16 melted by the heating during the reflow forms a fillet at the outer peripheral portion of the semiconductor element 15 to secure the bonding strength.
【００２２】[0022]
【発明の効果】以上のようにこの発明によれば、半導体
チップに接着樹脂を塗布して仮硬化状態にさせて基板の
配線パッドに接合するため作業性が向上するほか、リフ
ロー時の加熱により仮硬化状態を溶融状態として半導体
チップと基板との間に接着樹脂を充填するため、従来の
実装組み立て時におけるアンダーフィル工程が不要とな
り、しかも両者間の接合強度も確保できるという効果を
奏する。As described above, according to the present invention, the workability is improved because the adhesive resin is applied to the semiconductor chip so that the semiconductor chip is temporarily cured and joined to the wiring pad of the substrate, and the semiconductor chip is heated by reflow. Since the adhesive resin is filled between the semiconductor chip and the substrate in the temporarily cured state in a molten state, an underfill step in the conventional mounting and assembling is not required, and the joint strength between the two can be secured.
【図１】 この発明に係る半導体装置の製造フロー図で
ある。FIG. 1 is a manufacturing flowchart of a semiconductor device according to the present invention.
【図２】 この発明に係る半導体装置の製造フロー図で
ある。FIG. 2 is a manufacturing flowchart of the semiconductor device according to the present invention.
【図３】 この発明に係る半導体装置の製造フロー図で
ある。FIG. 3 is a manufacturing flowchart of the semiconductor device according to the present invention.
１…パッケージ基板、２、１０…半導体チップ、３…は
んだバンプ、４、１２、１６…熱可塑性樹脂、６…基
板、７、１４…配線パッド、１１…金バンプ、１３…パ
ッケージ基台、１５…半導体素子、１７…基板DESCRIPTION OF SYMBOLS 1 ... Package board, 2, 10 ... Semiconductor chip, 3 ... Solder bump, 4, 12, 16 ... Thermoplastic resin, 6 ... Substrate, 7, 14 ... Wiring pad, 11 ... Gold bump, 13 ... Package base, 15 ... semiconductor element, 17 ... substrate
Claims (6)
この基板に対向配置されたパッケージ基板と、このパッ
ケージ基板上の上記基板側に互いに間隔を隔てて設けら
れた複数のボールグリッドと、上記パッケージ基板の上
記基板側と反対側に設けられた半導体チップと、上記基
板と上記パッケージ基板との間に充填された接着樹脂と
を備え、この接着樹脂は、上記パッケージ基板上の上記
ボールグリッド上に塗布し、仮硬化時における加熱によ
り上記複数のボールグリッドの間隔に充填して仮硬化状
態とし、この仮硬化状態でそれぞれ上記基板の配線パッ
ドに接続するリフロー時の加熱により、上記仮硬化状態
を溶融して上記基板と上記パッケージ基板との間に充填
されるようにしたことを特徴とする半導体装置。A substrate provided with a plurality of wiring pads;
A package substrate opposed to the substrate, a plurality of ball grids provided on the substrate side of the package substrate at a distance from each other, and a semiconductor chip provided on an opposite side of the package substrate to the substrate side And an adhesive resin filled between the substrate and the package substrate. The adhesive resin is applied on the ball grid on the package substrate, and the plurality of ball grids are heated by temporary curing. In the pre-cured state, the pre-cured state is melted, and the pre-cured state is melted by heating at the time of reflow to connect to the wiring pads of the substrate, and the space is filled between the substrate and the package substrate. A semiconductor device characterized in that:
ジ基台と、このパッケージ基台上に配設された半導体チ
ップと、この半導体チップの上記パッケージ基台側に互
いに間隔を隔てて設けられた複数のバンプと、上記半導
体素子と上記パッケージ基台との間に充填された接着樹
脂とを備え、上記半導体チップ上の上記バンプ上に塗布
し、仮硬化時における加熱により上記バンプの間隔に充
填して仮硬化状態とし、この仮硬化状態で上記半導体チ
ップの複数のバンプをそれぞれ上記パッケージ基台上の
配線パッドに接合するフェイスダウンボンデイング時の
加熱により、上記仮硬化状態を溶融して上記パッケージ
基台と上記半導体チップとの間に充填されるようにした
ことを特徴とする半導体装置。2. A package base on which a plurality of wiring pads are provided, a semiconductor chip disposed on the package base, and a semiconductor chip provided on the package base side of the semiconductor chip at a distance from each other. A plurality of bumps, an adhesive resin filled between the semiconductor element and the package base, applied to the bumps on the semiconductor chip, and filled in the gaps between the bumps by heating during temporary curing In the temporary hardened state, the plurality of bumps of the semiconductor chip are bonded to the wiring pads on the package base in a face-down bonding in the temporarily hardened state, thereby melting the temporary hardened state and heating the package. A semiconductor device characterized by being filled between a base and the semiconductor chip.
は上記バンプの上面が露出するように上記パッケージ基
板上又は上記半導体素子上に塗布したことを特徴とする
請求項１又は２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the adhesive resin is applied on the package substrate or the semiconductor element such that an upper surface of the ball grid or the bump is exposed. .
であることを特徴とする請求項１又は２に記載の半導体
装置。4. The semiconductor device according to claim 1, wherein the adhesive resin is a one-component thermoplastic resin.
布工程と、上記熱可塑性樹脂を加熱して仮硬化状態にさ
せる仮硬化工程と、この仮硬化工程の後に、上記半導体
素子の仮硬化状態の熱可塑性樹脂をそれぞれ基板上に位
置決めする位置決め工程と、この位置決め工程後の加熱
により、上記熱可塑性樹脂の仮硬化状態を溶融して上記
半導体素子と上記基板との間にそれぞれ熱可塑性樹脂を
充填する充填工程とを備えたことを特徴とする半導体素
子の製造方法。5. An application step of applying a thermoplastic resin to a semiconductor element, a temporary curing step of heating the thermoplastic resin to a temporary curing state, and, after the temporary curing step, a temporary curing state of the semiconductor element. A positioning step of positioning each of the thermoplastic resins on the substrate, and heating after the positioning step, melting the thermoplastic resin in a pre-cured state and placing the thermoplastic resin between the semiconductor element and the substrate, respectively. A method for manufacturing a semiconductor device, comprising: a filling step of filling.
時の加熱であって、上記熱可塑性樹脂の溶融により上記
半導体素子の外周部分においてフィレットを形成するよ
うにしたことを特徴とする請求項５に記載の半導体装置
の製造方法。6. The heating in the filling step is heating during reflow, and a fillet is formed in an outer peripheral portion of the semiconductor element by melting the thermoplastic resin. The manufacturing method of the semiconductor device described in the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16954099A JP3565092B2 (en) | 1999-06-16 | 1999-06-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16954099A JP3565092B2 (en) | 1999-06-16 | 1999-06-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000357714A true JP2000357714A (en) | 2000-12-26 |
| JP3565092B2 JP3565092B2 (en) | 2004-09-15 |
Family
ID=15888390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16954099A Expired - Fee Related JP3565092B2 (en) | 1999-06-16 | 1999-06-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3565092B2 (en) |
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|---|---|---|---|---|
| US6821878B2 (en) * | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
| JP2008091724A (en) * | 2006-10-03 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Component mounting machine and component mounting method |
| CN100428454C (en) * | 2005-07-04 | 2008-10-22 | 南茂科技股份有限公司 | Tape lower chip packaging structure and its producing method |
| WO2010002739A2 (en) * | 2008-06-30 | 2010-01-07 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| US7675172B2 (en) | 2007-06-29 | 2010-03-09 | Kabushiki Kaisha Toshiba | Printed circuit board, mounting method of electronic component, and electronic apparatus |
| JP2012089740A (en) * | 2010-10-21 | 2012-05-10 | Fujitsu Ltd | Manufacturing method and bonding method of semiconductor device |
| JP2012195372A (en) * | 2011-03-15 | 2012-10-11 | Sekisui Chem Co Ltd | Semiconductor chip package body manufacturing method, laminated sheet and semiconductor chip package body |
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1999
- 1999-06-16 JP JP16954099A patent/JP3565092B2/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6821878B2 (en) * | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
| CN100428454C (en) * | 2005-07-04 | 2008-10-22 | 南茂科技股份有限公司 | Tape lower chip packaging structure and its producing method |
| JP4728201B2 (en) * | 2006-10-03 | 2011-07-20 | パナソニック株式会社 | Component mounting machine and component mounting method |
| JP2008091724A (en) * | 2006-10-03 | 2008-04-17 | Matsushita Electric Ind Co Ltd | Component mounting machine and component mounting method |
| US7675172B2 (en) | 2007-06-29 | 2010-03-09 | Kabushiki Kaisha Toshiba | Printed circuit board, mounting method of electronic component, and electronic apparatus |
| WO2010002739A2 (en) * | 2008-06-30 | 2010-01-07 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| WO2010002739A3 (en) * | 2008-06-30 | 2010-03-25 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| US8258019B2 (en) | 2008-06-30 | 2012-09-04 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| US8847368B2 (en) | 2008-06-30 | 2014-09-30 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| US9397016B2 (en) | 2008-06-30 | 2016-07-19 | Intel Corporation | Flip chip assembly process for ultra thin substrate and package on package assembly |
| JP2012089740A (en) * | 2010-10-21 | 2012-05-10 | Fujitsu Ltd | Manufacturing method and bonding method of semiconductor device |
| JP2012195372A (en) * | 2011-03-15 | 2012-10-11 | Sekisui Chem Co Ltd | Semiconductor chip package body manufacturing method, laminated sheet and semiconductor chip package body |
| JP2014150115A (en) * | 2013-01-31 | 2014-08-21 | Panasonic Corp | Electronic component mounting method |
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