JPH0415965A - Method of forming electrodes in mesa type semiconductor device - Google Patents
Method of forming electrodes in mesa type semiconductor deviceInfo
- Publication number
- JPH0415965A JPH0415965A JP2119185A JP11918590A JPH0415965A JP H0415965 A JPH0415965 A JP H0415965A JP 2119185 A JP2119185 A JP 2119185A JP 11918590 A JP11918590 A JP 11918590A JP H0415965 A JPH0415965 A JP H0415965A
- Authority
- JP
- Japan
- Prior art keywords
- mesa
- layer
- electrode
- mask
- masks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005253 cladding Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、メサ型半導体素子における電極形成方法、特
に、メサ型の発光ダイオード等に好適な電極形成方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming an electrode in a mesa-type semiconductor device, and particularly to a method for forming an electrode suitable for a mesa-type light emitting diode and the like.
（従来の技術）
従来のメサ型半導体素子における電極形成方法をメサ型
発光ダイオードを例にとって説明する。(Prior Art) A method for forming electrodes in a conventional mesa-type semiconductor device will be described using a mesa-type light emitting diode as an example.
第４図は、メサ付近の断面図である。図中、３はｎ−Ｉ
ｎＰのクラッド層、４はＩｎＧａＡｓＰの活性層、５は
ｐ−１ｎＰのクラッド層、６はｐ−ＩｎＧａＡｓＰのキ
ャップ層、１１はＳｉＮｘの絶縁膜、８はｐ電極である
。ｐ電極をメサ上のキャップ層６にコンタクトさせるた
めに、メサの形成後に、ＳｉＮｘの絶縁膜１１を全面に
成膜した後、メサ上の絶縁膜にコンタクトホールを形成
してから電極を被着させている。FIG. 4 is a cross-sectional view of the vicinity of the mesa. In the figure, 3 is n-I
An nP cladding layer, 4 an InGaAsP active layer, 5 a p-1nP cladding layer, 6 a p-InGaAsP cap layer, 11 an SiNx insulating film, and 8 a p-electrode. In order to contact the p-electrode with the cap layer 6 on the mesa, after forming the mesa, an SiNx insulating film 11 is formed on the entire surface, a contact hole is formed in the insulating film on the mesa, and then the electrode is attached. I'm letting you do it.
しかしながら、コンタクトホールの形成は、ホトリソ法
が用いられるが、正確にマスク合わせを行なうことが困
難であり、レジストがメサのエツジで切れ易いという難
点があり、歩留まりを悪くする原因となっている。However, although photolithography is used to form the contact holes, it is difficult to perform accurate mask alignment, and the resist easily breaks at the edges of the mesa, which causes a decrease in yield.
（発明が解決しようとする課題）
本発明は、上述した事情に鑑みてなされたもので、電極
形成工程を容易にすることにより、大量生産に好適なメ
サ型半導体素子における電極形成方法を提供することを
目的とするものである。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and provides a method for forming electrodes in a mesa-type semiconductor element suitable for mass production by facilitating the electrode forming process. The purpose is to
（課題を解決するための手段）
本発明は、メサ型半導体素子における電極形成方法にお
いて、メサ形成のためのマスクを形成し、メサを形成し
た後、電極部となる部分以外のマスクを除去し、ついで
、残されたマスクを用いて高抵抗層を形成した後、マス
クを除去して電極層を被着することを特徴とするもので
ある。(Means for Solving the Problems) The present invention provides a method for forming an electrode in a mesa-type semiconductor device, in which a mask for forming a mesa is formed, and after forming the mesa, the mask other than the portion that will become the electrode portion is removed. Then, after forming a high resistance layer using the remaining mask, the mask is removed and an electrode layer is deposited.
（作 用）
本発明は、メサ型半導体素子における電極形成方法にお
いて、メサ形成のためのマスクを形成し、メサを形成し
た後、電極部となる部分以外のマスクを除去する。マス
クの除去は、その周囲にメサ形成をした溝が存在してい
るから、メサ部におけるマスクを残すことは容易である
。ついで、残されたマスクを用いて高抵抗層を形成する
が、マスク上には高抵抗層が形成されないマスク材料を
選定しておけば、高抵抗層の形成後に、マスクを除去す
れば、コンタクトホールを容易に形成することができる
。(Function) According to the present invention, in a method for forming an electrode in a mesa-type semiconductor element, a mask for forming a mesa is formed, and after the mesa is formed, the mask other than the portion that will become the electrode portion is removed. When removing the mask, it is easy to leave the mask in the mesa portion because there is a groove in which a mesa is formed around the mask. Next, a high resistance layer is formed using the remaining mask, but if a mask material is selected that will not form a high resistance layer on the mask, the contact can be made by removing the mask after forming the high resistance layer. Holes can be easily formed.
したがって、電極をメサの上いっばいに形成することが
可能である。Therefore, it is possible to form the electrodes all over the mesa.
（実施例）
第１図は、本発明をメサ型発光ダイオードに適用した一
実施例の斜視図、第２図は、第１図のメサ部を通る面で
垂直に切った断面図である。図中、１はｎ電極、２はｎ
−ＩｎＰの基板、３はｎ−ＩｎＰのクラッド層、４はＩ
ｎＧａＡｓＰの活性層、５はｐ−ＩｎＰのクラッド層、
６はｐ−ＩｎＧａＡｓＰのキャップ層、７はＦｅドープ
の工ｎＰの高抵抗層、８はｐ電極、９はＳ Ｉ Ｎ ２
の光取り出し窓である。(Embodiment) FIG. 1 is a perspective view of an embodiment in which the present invention is applied to a mesa-type light emitting diode, and FIG. 2 is a sectional view taken perpendicularly to a plane passing through the mesa portion of FIG. 1. In the figure, 1 is an n-electrode, 2 is an n-electrode,
-InP substrate, 3 is n-InP cladding layer, 4 is I
nGaAsP active layer, 5 p-InP cladding layer,
6 is a p-InGaAsP cap layer, 7 is an Fe-doped nP high-resistance layer, 8 is a p-electrode, and 9 is a SIN2
It is a light extraction window.
第１図の発光ダイオードの製造方法の実施例を第３図に
より説明する。同図（Ａ）は、ｎ−ＩｎＰの基板２の上
に、ｎ−ＩｎＰのクラッド層３、ＩｎＧａＡｓＰの活性
層４、ｐ−ＩｎＰのクラッド層５、ｐ−ＩｎＧａＡｓＰ
のキャップ層６を液相成長によりエピタキシャル結晶成
長したものである。その上に、同図（Ｂ）に示すように
、スパッタリングとホトリソにより５ｉｎ２のメサエッ
チングマスク１２を形成する。ついで、同図（Ｃ）に示
すように、エツチング液により溝を形成してメサを形成
する。メサ形成後、通常はエツチングマスクを除去する
が、本発明では、同図（Ｄ）に示すように、メサ部の頂
部のマスクを残すようホトリソ工程で選択除去を行なう
。残すマスクの周囲は溝１０となって、ＳｉＯ２膜はな
いから、ホトリソ工程は容易である。An embodiment of the method for manufacturing the light emitting diode shown in FIG. 1 will be described with reference to FIG. The figure (A) shows an n-InP cladding layer 3, an InGaAsP active layer 4, a p-InP cladding layer 5, a p-InGaAsP
The cap layer 6 is epitaxially grown by liquid phase growth. Thereon, as shown in FIG. 2B, a 5 in 2 mesa etching mask 12 is formed by sputtering and photolithography. Next, as shown in FIG. 1C, grooves are formed using an etching solution to form mesas. After the mesa is formed, the etching mask is usually removed, but in the present invention, selective removal is performed in a photolithography process so as to leave the mask at the top of the mesa, as shown in FIG. The area around the remaining mask becomes a groove 10 and there is no SiO2 film, so the photolithography process is easy.
この実施例のように発光ダイオードの場合は、メサ部の
頂部のマスクは、そのすべてを残すようにするのがよい
が、半導体素子の形態によっては、その一部だけを残す
ようにパターン形成をしてもよい。In the case of a light-emitting diode as in this example, it is best to leave all of the mask on the top of the mesa part, but depending on the form of the semiconductor element, the pattern may be formed to leave only part of it. You may.
同図（Ｅ）は、高抵抗層の形成工程である。ＭＯＣＶＤ
によって、ＦｅドープのＩｎＰを全面に成長させる。し
かし、ＳｉＯ□膜の上には成長しない。この層は半絶縁
性である。つまり、同図（Ｂ）で説明したエツチングマ
スクは、高抵抗層が成長しない性質の膜を選択する。FIG. 3(E) shows the process of forming a high resistance layer. MOCVD
In this way, Fe-doped InP is grown over the entire surface. However, it does not grow on the SiO□ film. This layer is semi-insulating. In other words, the etching mask described with reference to FIG. 3B is selected from a film that does not allow the growth of a high-resistance layer.
高抵抗層を成長した後、フッ酸によりＳｉＯ□膜を除去
して、同図（Ｆ）に示すような、メサの頂部をコンタク
トホールとしたものが得られるから、これにｐ電極を、
裏面に、光取り出し窓を設けたｎ電極を形成する。After growing the high-resistance layer, the SiO□ film is removed using hydrofluoric acid to obtain a mesa with the top of the mesa as a contact hole, as shown in Figure (F).
An n-electrode provided with a light extraction window is formed on the back surface.
なお、各層における材料は、上記したものに限られるも
のではなく、光吸収領域層も、他の系の材料を用いるこ
とができる。メサ形成も、ｐ−ＩｎＰのクラッド層まで
とした準メサ構造でもよく、このようなものも、本発明
では、メサ型と呼んでいる。Note that the materials for each layer are not limited to those described above, and other types of materials can be used for the light absorption region layer as well. The mesa structure may also be a quasi-mesa structure including a p-InP cladding layer, and such a structure is also referred to as a mesa type in the present invention.
（発明の効果）
以上の説明から明らかなように、本発明によれば、コン
タクトホールの形成が容易であり、しかも正確にできる
ので、大量生産に適した、また、歩留まりのよい半導体
素子を製造できる効果がある。(Effects of the Invention) As is clear from the above description, according to the present invention, contact holes can be formed easily and accurately, so that semiconductor devices suitable for mass production and with a high yield can be manufactured. There is an effect that can be achieved.
これをメサ型の発光ダイオードに適用した場合は、メサ
型の頂部いっばいに広がるコンタクトホールを形成する
ことができる。When this is applied to a mesa-type light emitting diode, a contact hole can be formed that extends all the way to the top of the mesa-type.
第１図は、本発明の一実施例を説明するためのメサ型発
光ダイオードの斜視図、第２図は、第１図のメサ型発光
ダイオードの断面図、第３図は製造工程の説明図、第４
図は、従来の発光ダイオードの一例の斜視図である。
１・・・ｎ電極、２・・・ｎ−ＩｎＰ基板、３・・・ｎ
−ＩｎＰクラッド層、４−ＩｎＧａＡｓＰ活性層、５・
・−ｐ−ＩｎＰクラッド層、６−・−ｐ −Ｉ ｎ Ｇ
ａ Ａ ｓＰキャップ層、７・・・ＦｅドープのＩｎ
Ｐの高抵抗層、８・・・ｎ電極、９・・・光取り出し窓
。
特許出願人 株式会社島津製作所FIG. 1 is a perspective view of a mesa-type light emitting diode for explaining one embodiment of the present invention, FIG. 2 is a sectional view of the mesa-type light-emitting diode shown in FIG. 1, and FIG. 3 is an explanatory diagram of the manufacturing process. , 4th
The figure is a perspective view of an example of a conventional light emitting diode. 1...n electrode, 2...n-InP substrate, 3...n
-InP cladding layer, 4-InGaAsP active layer, 5.
・-p-InP cladding layer, 6-・-p-InG
a A sP cap layer, 7...Fe-doped In
P high resistance layer, 8...N electrode, 9...Light extraction window. Patent applicant: Shimadzu Corporation
Claims (1)
、電極部となる部分以外のマスクを除去し、ついで、残
されたマスクを用いて高抵抗層を形成した後、マスクを
除去して電極層を被着することを特徴とするメサ型半導
体素子における電極形成方法。After forming a mask for mesa formation and forming the mesa, remove the mask other than the part that will become the electrode part, then use the remaining mask to form a high resistance layer, and then remove the mask. A method for forming electrodes in a mesa-type semiconductor device, characterized by depositing an electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2119185A JPH0415965A (en) | 1990-05-09 | 1990-05-09 | Method of forming electrodes in mesa type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2119185A JPH0415965A (en) | 1990-05-09 | 1990-05-09 | Method of forming electrodes in mesa type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415965A true JPH0415965A (en) | 1992-01-21 |
Family
ID=14755017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2119185A Pending JPH0415965A (en) | 1990-05-09 | 1990-05-09 | Method of forming electrodes in mesa type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415965A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1592072A2 (en) * | 2004-04-30 | 2005-11-02 | Osram Opto Semiconductors GmbH | Optoelectronic semiconductor chip and method of fabricating the same |
-
1990
- 1990-05-09 JP JP2119185A patent/JPH0415965A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1592072A2 (en) * | 2004-04-30 | 2005-11-02 | Osram Opto Semiconductors GmbH | Optoelectronic semiconductor chip and method of fabricating the same |
| EP1592072A3 (en) * | 2004-04-30 | 2007-12-26 | Osram Opto Semiconductors GmbH | Optoelectronic semiconductor chip and method of fabricating the same |
| US7435999B2 (en) | 2004-04-30 | 2008-10-14 | Osram Opto Semiconductors Gmbh | Semiconductor chip for optoelectronics and method for the production thereof |
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