JPS62199021A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62199021A JPS62199021A JP4240286A JP4240286A JPS62199021A JP S62199021 A JPS62199021 A JP S62199021A JP 4240286 A JP4240286 A JP 4240286A JP 4240286 A JP4240286 A JP 4240286A JP S62199021 A JPS62199021 A JP S62199021A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- mask
- shielding film
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 238000005253 cladding Methods 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 6
- 239000007791 liquid phase Substances 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 H202 Chemical compound 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Weting (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
遮蔽膜Ａと遮蔽膜Ｂとの２層マスクによって、半導体基
板をメサ状にエツチングし、次いで、上層の遮蔽＊Ｂを
マスクにして遮蔽膜Ａの側方はみ出し部を除去する。そ
うすると、以降の処理工程で遮蔽膜Ａが剥がれたり、損
傷されたりすることがなくなる。[Detailed Description of the Invention] [Summary] A semiconductor substrate is etched into a mesa shape using a two-layer mask of a shielding film A and a shielding film B, and then, using the upper layer of the shielding *B as a mask, the sides of the shielding film A are etched. Remove the protruding part. This prevents the shielding film A from being peeled off or damaged in subsequent processing steps.
［産業上の利用分野］
本発明は半導体装置の製造方法に係り、特に、半導体発
光装置等のメサエッチングに関する。[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to mesa etching of a semiconductor light emitting device or the like.
半導体装置を製造する際、半導体基板をメサ状（台地状
）にエツチングするエツチング方法が使用されているが
、そのようにメサエッチングした場合には、通常、エツ
チング凹部を他の材料で埋める等の処置をして、表面を
平坦化する方法が採られる。When manufacturing semiconductor devices, an etching method is used in which the semiconductor substrate is etched into a mesa-like (plateau-like) shape.When such mesa etching is performed, the etching recesses are usually filled with other materials. Treatment is used to flatten the surface.
その場合、メサエッチングに用いたマスクは、そのまま
再びその次の工程に使用されることが多く、従って、そ
のマスクは十分に被覆性が維持されるように配慮しなけ
ればならない。In this case, the mask used for mesa etching is often used as is in the next step, and therefore care must be taken to ensure that the mask maintains sufficient coverage.
［従来の技術と発明が解決しようとする問題点］例えば
、ＩｎＧａＡｓ Ｐなどの半導体レーザは光通信用の光
源として利用されており、その半導体レーザ光源の素子
は閉じ込め層（埋め込みＭ）を設け、局部的な活性領域
からレーザ発振をおこなう構造が汎用されている。[Prior art and problems to be solved by the invention] For example, a semiconductor laser such as InGaAs P is used as a light source for optical communication, and the element of the semiconductor laser light source is provided with a confinement layer (embedded M). A structure in which laser oscillation is performed from a localized active region is widely used.
第２図は、その埋め込み層を設けたＩｎＧａＡｓ Ｐか
らなる半導体レーザ素子の断面概要を示しており、１は
ｎ−ＩｎＰ基板、２はｎ−ＩｎＰバッファ層、３はｎ
（ｐ） −ＩｎＧａＡｓ Ｐ活性層、４はｐ−ＩｎＰク
ラッド層、５はｐ −１ｎＧａＡｓ Ｐ電極層、６は絶
縁膜、７は生電極、８は一電極で、９が埋め込み層であ
る。FIG. 2 shows a cross-sectional outline of a semiconductor laser device made of InGaAsP with a buried layer provided therein. 1 is an n-InP substrate, 2 is an n-InP buffer layer, and 3 is an n-InP substrate.
(p) -InGaAs P active layer, 4 is a p-InP cladding layer, 5 is a p -1nGaAs P electrode layer, 6 is an insulating film, 7 is a raw electrode, 8 is one electrode, and 9 is a buried layer.
この埋め込み層９はｐ−ＩｎＰ層９１とｎ −ＩｎＰｎ
Ｐ２Ｏ５らなり、バッファ層２やクラッド層４に対し逆
接合して、電流を阻止しているが、この埋め込み層９の
形成が容易ではなく、第３図（Ｍｌ〜（Ｃ）にその形成
工程順断面図を示している。This buried layer 9 consists of a p-InP layer 91 and an n-InPn
The buried layer 9 is made of P2O5 and is reversely connected to the buffer layer 2 and cladding layer 4 to block current flow, but it is not easy to form this buried layer 9, and the formation process is shown in Fig. 3 (Ml to (C)). A forward sectional view is shown.
その形成方法は、まず、第３図ｆａ）に示すように、ｎ
−ＩｎＰ基板１上にｎ−１ｎＰバッファ層２．ｎ−Ｉｎ
ＧａＡｓ Ｐ活性層３．ｐ−ＩｎＰクラッド１ｉ４．
ｐ−ＩｎＧａＡｓ Ｐ電極層５を順次に液相成長法に
よってエピタキシャル成長した後、活性層を形成しよう
とする領域上に、酸化シリコン（Ｓｉｇｈ ）膜１０の
マスクを形成する。この５ｉ０２膜１０のマスクは、例
えば、５ｉ０２膜を被着し、その上にレジスト膜（図示
せず）のマスクを形成して、弗化物溶液で５ｔ０２膜１
０をエツチングして形成する。The formation method is as shown in Fig. 3fa).
- an n-1nP buffer layer 2 on an InP substrate 1; n-In
GaAs P active layer 3. p-InP cladding 1i4.
After the p-InGaAs P electrode layer 5 is sequentially epitaxially grown by liquid phase growth, a mask of a silicon oxide (Sigh) film 10 is formed on the region where the active layer is to be formed. The mask for this 5i02 film 10 can be made, for example, by depositing a 5i02 film, forming a mask of a resist film (not shown) on it, and applying a fluoride solution to the 5t02 film 10.
Formed by etching 0.
次いで、第３図（ｂ）に示すように、５ｉ０２膜１０を
マスクにして、基板の露出部をメサエッチングする。エ
ツチング液は臭化水素（ＨＢｒ）と過酸化水素（Ｈ２Ｏ
２）と水（Ｈ２０）との混合液である。Next, as shown in FIG. 3(b), the exposed portion of the substrate is mesa-etched using the 5i02 film 10 as a mask. The etching solution is hydrogen bromide (HBr) and hydrogen peroxide (H2O).
2) and water (H20).
この際、メサエッチングはエツチング厚さが厚い（例え
ば、厚さ２μｍ程度）ため、サイドエツチングが進行し
易（て、５ｉ０２膜１０マスクの下面もエツチングされ
、マスクが鍔状にはみだして突出する。At this time, since the mesa etching has a thick etching thickness (for example, about 2 μm), side etching tends to progress (as a result, the lower surface of the 5i02 film 10 mask is also etched, and the mask protrudes like a brim).
次いで、第３図（Ｃ）に示すように、５ｉ０２膜１０の
マスクをそのまま残存させ、それをマスクにして選択的
な液相成長法によって、エツチング凹部にｐ−ＩｎＰ層
９１とｎ−ＩｎＰｎＰ２Ｏ５エピタキシャル成長して平
坦化する。Next, as shown in FIG. 3(C), the mask of the 5i02 film 10 remains as it is, and a p-InP layer 91 and n-InPnP2O5 are epitaxially grown in the etching recess by selective liquid phase growth using it as a mask. and flatten it.
ところが、その際、液相成長の途中で、図示のように、
５ｉ０２膜１０のマスクが剥がれ落ちてなくなり、活性
領域上にもｐ −１ｎＰ層９１ ｖ ｎ −１ｎ Ｐ層
９２がエピタキシャル成長すると云う不具合が生じる。However, at that time, during the liquid phase growth, as shown in the figure,
A problem occurs in that the mask of the 5i02 film 10 peels off and disappears, and the p -1nP layer 91 v n -1n P layer 92 also grows epitaxially on the active region.
第３図（Ｃ１に示した例は、ｐ −ＩｎＰ層９１が選択
成長できて、次のｎ −ＩｎＰｎＰ２Ｏ５長時に５ｉ０
２膜ｌＯマスクが剥がれ落ちた例である。In the example shown in FIG. 3 (C1), the p -InP layer 91 can be selectively grown, and the next n -InPnP2O5 length is 5i0.
This is an example of a two-layer 1O mask peeling off.
しかし、このように５ｉ０２膜１０マスクが剥がれ落ち
ると選択的な液相成長がおこなわれず、ｎｐ逆接合が形
成されて、レーザ素子として役立たなくなる。また、マ
スク全部が剥がれなくて、一部が剥がれても、同様に素
子としての用をなさなくなる。However, if the 5i02 film 10 mask peels off in this way, selective liquid phase growth will not take place and an np reverse junction will be formed, making it useless as a laser device. Further, even if the entire mask is not peeled off, but only a part of the mask is peeled off, the device is no longer useful.
本発明は、このような問題点を解決して、歩留を向上す
るための半導体装置の製造方法を提案するものである。The present invention proposes a method of manufacturing a semiconductor device to solve these problems and improve yield.
［問題点を解決するための手段］
その目的は、遮蔽膜Ａと遮蔽膜Ｂとを積層した２層マス
クを用いて、半導体基板の所定領域をメサ状にエツチン
グし、次いで、上層の前記遮蔽膜Ｂをマスクにして、下
層の前記遮蔽膜Ａの側方露出部を除去するようにした工
程が含まれる半導体装置の製造方法によって達成される
。[Means for solving the problem] The purpose is to etch a predetermined area of a semiconductor substrate into a mesa shape using a two-layer mask in which a shielding film A and a shielding film B are stacked, and then to remove the upper layer of the shielding film. This is achieved by a method for manufacturing a semiconductor device that includes a step of removing the side exposed portions of the underlying shielding film A using film B as a mask.
例えば、上記の例では、レジスト膜と５ｉ０２膜とを積
層した２層マスクを用いて、ＩｎＰ基板の活性領域をメ
サ状にエツチングし、次いで、上層ののレジスト膜をマ
スクにして、下層の５ｉ０２膜の側方はみ出し露出部を
弗素系溶液でエツチング除去する。For example, in the above example, the active region of the InP substrate is etched into a mesa shape using a two-layer mask consisting of a resist film and a 5i02 film, and then, using the upper resist film as a mask, the lower 5i02 film is etched. The exposed side protruding portions of the membrane are removed by etching with a fluorine-based solution.
［作用］
即ち、本発明は、エツチング遮蔽膜ＡとＢとの２層マス
クによって、半導体基板をメサエッチングし、次いで、
上層の遮蔽膜Ｂをマスクにして遮蔽膜Ａの鍔状のはみ出
し部を除去する。[Operation] That is, in the present invention, a semiconductor substrate is mesa-etched using a two-layer mask of etching shielding films A and B, and then,
Using the upper layer shielding film B as a mask, the brim-shaped protruding portion of the shielding film A is removed.
そうすると、遮蔽膜Ａのマスクは鍔状のはみ出し部がな
くなるから、摩擦に強くなって、剥がれ難くなる。従っ
て、その遮蔽膜Ａのマスクを利用して、次工程を所期通
りに形成することができる。Then, the mask of the shielding film A will have no protruding part in the form of a brim, so it will be strong against friction and will not easily peel off. Therefore, using the mask of the shielding film A, the next step can be formed as expected.
［実施例コ 以下、図面を参照して実施例によって詳細に説明する。[Example code] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図（ａ）〜（ｄ）は、従来の第３図（ａｌ 〜（Ｃ
）に示す実施例に対応した、本発明にかかる形成工程順
断面図を示している。まず、同図（ａ）に示すように、
従来法と同じく、ｎ−ＩｎＰ基板１上にｎ −１ｎＰバ
ッファ層２． ｎ−ＩｎＧａＡｓＰ活性層３ （膜￥
：ｔｓｏｏ人）。Figures 1(a) to (d) are similar to conventional Figures 3(al to (C)
) shows sequential cross-sectional views of the forming steps according to the present invention, corresponding to the embodiment shown in FIG. First, as shown in Figure (a),
As in the conventional method, an n-1nP buffer layer 2. is formed on an n-InP substrate 1. n-InGaAsP active layer 3 (film
:tsoo person).
ｐ−ＩｎＰｎチク９フ４ （膜厚１ ／ｊ ｍ） ＋
ｐ −ＩｎＧａＡｓＰ電極層５ （膜厚３０００人）
を順次にエピタキシＪ）Ｌ／成長した後、５ｉ０２膜１
１（膜厚１０００〜２０００人）を被着し、更に、その
上にレジスト膜（膜Ｗ−１μｍ）１２のマスクを形成し
、次に、５ｉ０２膜１１を弗化物溶液でエツチングして
、活性層を形成しようとする領域上に、レジスト膜１２
と５ｉ０２膜１１との２層マスクを形成する。このマス
クは、例えば、幅３μｍ程度である。p-InPn pixel 9 4 (film thickness 1/j m) +
p-InGaAsP electrode layer 5 (thickness: 3000)
After sequential epitaxy J)L/growth, 5i02 film 1
1 (thickness: 1000 to 2000), a mask of resist film (film W - 1 μm) 12 is formed on it, and then the 5i02 film 11 is etched with a fluoride solution to form an activated etching film. A resist film 12 is placed on the area where the layer is to be formed.
A two-layer mask consisting of a 5i02 film 11 and a 5i02 film 11 is formed. This mask has a width of about 3 μm, for example.
次いで、第１図（ｂ）に示すように、レジスト膜１２を
除去することなく、そのまま２Ｎに積層したマスク１１
．１２を用いて、ＨＢｒとＨ２０２とＨ２Ｏとの混合溶
液で、露出部をメサエッチングする。その際、メサエッ
チングの厚さは１．４５μｍ以上になるから、サイドエ
ツチングが進行して、２層マスクは側方に長さ１μｍ程
度鍔状にはみだした形状になる。Next, as shown in FIG. 1(b), the mask 11 is laminated to 2N without removing the resist film 12.
．． 12, the exposed portion is mesa-etched with a mixed solution of HBr, H202, and H2O. At this time, since the thickness of the mesa etching is 1.45 μm or more, side etching progresses, and the two-layer mask protrudes laterally in a flange-like shape with a length of about 1 μm.
次いで、第１図（Ｃ）に示すように、レジスト膜１２を
そのままにして、弗化アンモン（ＮＨ４Ｆ）と弗酸（）
（Ｆ）との混合液でエツチングして、鍔状に突出した５
ｉ０２膜１１の部分を除去し、次に、レジスト膜１２を
有機溶剤で溶解除去する。そすうると、図示のように５
ｉ０２膜１１の鍔状突出部はなくなる。Next, as shown in FIG. 1(C), while leaving the resist film 12 as it is, ammonium fluoride (NH4F) and hydrofluoric acid () are added.
Etched with a mixture of (F) and protruding into a brim shape 5
A portion of the i02 film 11 is removed, and then the resist film 12 is dissolved and removed using an organic solvent. Then, as shown in the diagram, 5
The brim-like protrusion of the i02 film 11 disappears.
次いで、第１図（ｄｌに示すように、Ｓｔ○２膜１１全
１１マスクにして、選択的な液相成長法をおこない、凹
部にｐ−ＩｎＰ層９１とｎ−ＩｎＰＦｉ９２との埋め込
み層をエピタキシャル成長する。Next, as shown in FIG. 1 (dl), a selective liquid phase growth method is performed using a total mask of 11 for the St○2 film 11, and a buried layer of p-InP layer 91 and n-InPFi 92 is epitaxially grown in the recessed part. do.
上記が一実施例であるが、このような形成方法によれば
、５ｉ０２膜１１からなるマスクは鍔状のはみ出し部が
除去されており、接触しても剥がれ難くなるから、５ｉ
０２膜１１を利用して、良好な埋め込み層を形成するこ
とが容易になる。Although the above is an example, according to such a forming method, the flange-like protruding portion of the mask made of the 5i02 film 11 is removed, making it difficult to peel off even if it comes into contact with the mask.
By using the 02 film 11, it becomes easy to form a good buried layer.
［発明の効果］
以上の説明から明らかなように、本発明によれば、メサ
エッチング後の処理工程での問題点が解消されて、半導
体装置の歩留向上および高品質化に大きく寄与するもの
である。[Effects of the Invention] As is clear from the above description, according to the present invention, problems in the processing steps after mesa etching are solved, and this greatly contributes to improving the yield and quality of semiconductor devices. It is.
第１図（ａｌ〜（ｄ）は本発明にかかる形成工程順断面
図、第２図は埋め込み型ＩｎＧａＡｓ Ｐ半導体レーザ
の断面構造図、
第３図（ａｌ〜（Ｃ）は従来の形成工程順断面図である
。
図において、
１はｎ−１ｎＰ基板、 ２はｎ−ＩｎＰバッファ層
３はＩｎＧａＡｓ Ｐ活性層、 ４はｐ−ＩｎＰクラッ
ド層５はｐ −ＩｎＧａＡｓ Ｐ電極層、
６は絶縁膜、 ７．８は電極、９は埋め込み層
、
９１はｐ −１ｎＰ層、 ９２はｎ−１ｎＰ層、１
０、１１は５ｉ０２膜マスク、
１２はレジスト膜マスク
を示している。
オ響ト日ル；刀・ｉ・ｊ形へＴ＃グｔりｒ面図ｌ１１５
ｃＩ
第１ｖＭ
丁ｆｈンしり篤’ｉＪｙ＋５（ＬへＳＦ’半Ａ１り李し
−ザ謁ぜケ６け０ゴ第２図Figures 1 (al to d) are cross-sectional views in the order of the forming steps according to the present invention, Figure 2 is a cross-sectional structural diagram of a buried type InGaAs P semiconductor laser, and Figures 3 (al to (c) are the order of the conventional forming steps). 1 is a cross-sectional view. In the figure, 1 is an n-1nP substrate, 2 is an n-InP buffer layer 3 is an InGaAsP active layer, 4 is a p-InP cladding layer 5 is a p-InGaAsP electrode layer, 6 is an insulating film, 7.8 is an electrode, 9 is a buried layer, 91 is a p-1nP layer, 92 is an n-1nP layer, 1
0 and 11 are 5i02 film masks, and 12 is a resist film mask. Ohikoto day; Sword/I/J form T# Gut r side drawing l115
cI 1st vM Ding fhn Shiri Atsushi'iJy+5 (L to SF'Half A1 Ririshi-The audience 6 ke 0 Go Figure 2
Claims (2)
いて、半導体基板の所定領域をメサ状にエッチングし、
次いで、上層の前記遮蔽膜Ｂをマスクにして、下層の前
記遮蔽膜Ａの側方露出部を除去するようにした工程が含
まれてなることを特徴とする半導体装置の製造方法。(1) Using a two-layer mask in which shielding film A and shielding film B are laminated, a predetermined area of the semiconductor substrate is etched into a mesa shape,
A method for manufacturing a semiconductor device, comprising the step of: next, using the upper shielding film B as a mask, and removing a side exposed portion of the lower shielding film A.
スクを用いて、ＩｎＰ基板の活性領域をメサ状にエッチ
ングし、次いで、上層の前記レジスト膜をマスクにして
、下層の前記酸化シリコン膜の側方はみ出し露出部を弗
素系溶液でエッチング除去するようにした工程が含まれ
てなることを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(2) Using a two-layered mask consisting of a resist film and a silicon oxide film, the active region of the InP substrate is etched into a mesa shape, and then, using the upper resist film as a mask, the lower silicon oxide film is etched. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of etching away the exposed portions protruding from the sides with a fluorine-based solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240286A JPS62199021A (en) | 1986-02-26 | 1986-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240286A JPS62199021A (en) | 1986-02-26 | 1986-02-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199021A true JPS62199021A (en) | 1987-09-02 |
Family
ID=12635073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4240286A Pending JPS62199021A (en) | 1986-02-26 | 1986-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199021A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963507A (en) * | 1987-04-30 | 1990-10-16 | Siemens Aktiengesellschaft | Method and manufacturing a laser diode with buried active layer |
| JPH0425338U (en) * | 1990-06-22 | 1992-02-28 | ||
| JPH08316219A (en) * | 1995-05-19 | 1996-11-29 | Nec Corp | Manufacture of semiconductor device |
| US6678940B2 (en) * | 1998-10-08 | 2004-01-20 | Alps Electric Co., Ltd. | Method of making a thin-film magnetic head |
| KR100419286B1 (en) * | 2001-12-21 | 2004-02-18 | 엘지전자 주식회사 | Method for manufacturing semiconductor laser diode |
-
1986
- 1986-02-26 JP JP4240286A patent/JPS62199021A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963507A (en) * | 1987-04-30 | 1990-10-16 | Siemens Aktiengesellschaft | Method and manufacturing a laser diode with buried active layer |
| JPH0425338U (en) * | 1990-06-22 | 1992-02-28 | ||
| JPH08316219A (en) * | 1995-05-19 | 1996-11-29 | Nec Corp | Manufacture of semiconductor device |
| US6678940B2 (en) * | 1998-10-08 | 2004-01-20 | Alps Electric Co., Ltd. | Method of making a thin-film magnetic head |
| KR100419286B1 (en) * | 2001-12-21 | 2004-02-18 | 엘지전자 주식회사 | Method for manufacturing semiconductor laser diode |
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