JPH0415962A - Solar cell and manufacture thereof - Google Patents
Solar cell and manufacture thereofInfo
- Publication number
- JPH0415962A JPH0415962A JP2120790A JP12079090A JPH0415962A JP H0415962 A JPH0415962 A JP H0415962A JP 2120790 A JP2120790 A JP 2120790A JP 12079090 A JP12079090 A JP 12079090A JP H0415962 A JPH0415962 A JP H0415962A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- electrode
- light
- receiving surface
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000007639 printing Methods 0.000 abstract description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 3
- 239000002253 acid Substances 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical class O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract 1
- 229910019213 POCl3 Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035479 physiological effects, processes and functions Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
- H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
- H01L31/02245—Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
Landscapes
- Engineering & Computer Science (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Electromagnetism (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Sustainable Energy (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、半導体基板の形状及び受光面側電極の形成位
置に特徴を有する高効率で低価格の太陽電池及びその製
造方法に関するものである。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a highly efficient and low-cost solar cell characterized by the shape of a semiconductor substrate and the formation position of a light-receiving surface side electrode, and a method for manufacturing the same. .
〈従来の技術〉
太陽電池の高効率化を図るためには、表面反射率や表面
電極占有率の低減化が必要である。そこでこれまでに、
単結晶基板に対してはテクスチャ処理する方法等が、多
結晶基板に対してはンーザ光やダイサー等を用いて溝を
形成する方法等が用いられて表面面肘率が低減され、ま
た、スクリーン印刷技術の向上が図られて、表面電極占
有率が３〜４％にまで低減されている。<Prior Art> In order to improve the efficiency of solar cells, it is necessary to reduce the surface reflectance and surface electrode occupancy. So far,
For monocrystalline substrates, methods such as texturing are used, and for polycrystalline substrates, methods such as forming grooves using a laser beam or a dicer are used to reduce the surface elbow ratio. Improvements in printing technology have reduced the surface electrode occupancy to 3 to 4%.
一方、太陽電池は各セルが接続されて用いられるために
、接続の便利な裏面での接続法が工夫されている。例え
ば第４．５図に示すようなラップ・アラウンド法による
裏面での接続法がよく用いられる。第４図では、同図（
ａ）の太陽電池の構造図に示すように、受光面側のｎ＋
層５を素子端部より裏へ回し、該ｎ生理５に沿って受光
面側電極８を裏面まで回して形成した太陽電池を、同図
（ｂ）に示スように、リードフレーム４１により太陽電
池裏面の受光面側電極８と裏面電極７間で互いに接続し
ている。第５図では、リードフレーム４１によフ受光面
側電極８を裏面に形成したｎ”Ｍ５部で接続して受光面
側電極８を裏面に引回した太陽電池を、プリント基板５
１上に半田５２によシ太陽電池裏面の受光面側電極８と
裏面電極７を接続している。On the other hand, since solar cells are used by connecting each cell, a convenient connection method on the back side has been devised. For example, a wrap-around connection method on the back side as shown in FIG. 4.5 is often used. In Figure 4, the figure (
As shown in the structural diagram of the solar cell in a), n+ on the light-receiving surface side
A solar cell formed by turning the layer 5 from the element end to the back side and turning the light-receiving surface side electrode 8 to the back side along the n-type layer 5 is connected to the sun by a lead frame 41, as shown in FIG. The light-receiving side electrode 8 and the back electrode 7 on the back side of the battery are connected to each other. In FIG. 5, a solar cell in which the light-receiving surface side electrode 8 is connected to the lead frame 41 at the n''M5 portion formed on the back surface and the light-receiving surface side electrode 8 is routed on the back surface is connected to the printed circuit board 41.
1, the light-receiving surface side electrode 8 on the back surface of the solar cell and the back surface electrode 7 are connected by solder 52.
また、本出願人は表面電極占有率を低減しかつ裏面接続
の可能々太陽電池を提案している（特願昭６８−２０２
８７８）。これによれば例えば、第６図に示すような多
数の微小な貫通孔４を有するｐ型の多結晶シリコン基板
１と、該基板１の一方の面及び微小な貫通孔４の内壁に
形成されたｎ＋十層とよフなフ、該基板１の他方の面の
ｐ生理６の部分に裏面電極７を設け、該基板１の他方の
面の貫通孔４の端部のｎ生理５の部分に受光面側電極８
を設けた太陽電池である。尚、同図（ａ）は斜視図、（
ｂ）は貫通孔４周辺の拡大断面図であり、６１は反射防
止膜、６２はパッシベーション層である。In addition, the applicant has proposed a solar cell that reduces the surface electrode occupancy rate and allows connection on the back side (Patent Application No. 68-202
878). According to this, for example, a p-type polycrystalline silicon substrate 1 having a large number of minute through holes 4 as shown in FIG. A back electrode 7 is provided on the p-type 6 part of the other surface of the substrate 1, and a n-type 5 part is provided at the end of the through-hole 4 on the other surface of the substrate 1. The light-receiving surface side electrode 8
This is a solar cell equipped with Note that (a) is a perspective view, (
b) is an enlarged sectional view of the vicinity of the through hole 4, where 61 is an antireflection film and 62 is a passivation layer.
〈発明が解決しようとする課題〉
ヌクリーン印刷により達成される電極占有率は、３〜４
％まで低減されているものの、まだ低減化が十分ではな
（問題がある。これは、ヌクリーン印刷によらず、ホト
エツチング技術を用いれば解決できるが、太陽電池の低
価格化という観点から、その導入は困難であり、さらに
、上記表面反射率の低減のための溝加工を施した多結晶
基板では、表面の凹凸が５０〜１００μｍあり、精度良
ぐホトエツチングすることは不可能である。また、従来
のラップ・アラウンド法による裏面での配線方法では、
素子端部への電極形成が非常に困難であっタフ、リード
フレームをストレスフリーにするのに特殊な構造を用い
なければならなず、パッケージに組み込みにくい等の問
題がある。<Problem to be solved by the invention> The electrode occupancy rate achieved by Nuclean printing is 3 to 4
%, but the reduction is still not sufficient (there is a problem).This can be solved by using photoetching technology instead of Nuclean printing, but from the perspective of lowering the price of solar cells, it is difficult to introduce it. Furthermore, with the polycrystalline substrate that has been grooved to reduce the surface reflectance, the surface has irregularities of 50 to 100 μm, making it impossible to photoetch with high precision. In the backside wiring method using the wrap-around method,
There are problems such as it is extremely difficult and tough to form electrodes on the end of the element, a special structure must be used to make the lead frame stress-free, and it is difficult to incorporate it into a package.
これらに対し、先に提案した太陽電池では、型面占有率
が十分に低減され、かつ上記ラップ・アラウンド法にお
けるような問題もなく裏面接続が可能である。In contrast, in the solar cell proposed earlier, the mold surface occupancy rate is sufficiently reduced, and backside connection is possible without the problems encountered in the wrap-around method described above.
しかしながら、この太陽電池では、貫通孔端部に設けら
れた受光面側の電極と受光面とが離れているために、該
電極部での直列抵抗が大きくなりやすいという問題があ
Ｖ、改良の余地を残している。However, in this solar cell, since the electrode on the light-receiving surface side provided at the end of the through hole is separated from the light-receiving surface, there is a problem that the series resistance at the electrode portion tends to increase. leaving room.
そこで本発明は、スクリーン印刷によっても電極占有率
を十分に小さくすることができ、ラップ・アラウンド法
のような問題を生じることなく裏面接続が可能で、かつ
上記従来提案の発明による太陽電池よりも高い変換鮪率
を有する太陽電池を提供することを目的とする。また、
このような太陽電池を容易に作製するための製造方法を
提供することを目的とする。Therefore, the present invention can sufficiently reduce the electrode occupancy rate by screen printing, and can connect the back side without causing problems like the wrap-around method, and is better than the solar cells according to the previously proposed inventions. The purpose is to provide a solar cell with a high conversion rate. Also,
It is an object of the present invention to provide a manufacturing method for easily manufacturing such a solar cell.
く課題を解決するための手段〉
上記目的を達成するために、本発明は、半導体基板の受
光面に溝が形成され、上記受光面と反対側の裏面に上記
溝と重なるように凹部が形成され、該凹部と上記溝の重
なる位置に貫通孔が形成され、上記凹部開口部は貫通孔
の径より大きくなっており、上記裏面の上記凹部を含む
場所に上記貫通孔を介して半導体基板の受光面側に達す
る受光面側と電気的に接続された受光面側電極が形成さ
れ、上記裏面側の上記凹部を含まない場所に裏面電極が
形成されていることを特徴とする太陽電池を提供する。Means for Solving the Problems> In order to achieve the above object, the present invention provides a method in which a groove is formed on the light receiving surface of a semiconductor substrate, and a recess is formed on the back surface opposite to the light receiving surface so as to overlap with the groove. A through hole is formed at a position where the recess and the groove overlap, and the opening of the recess is larger than the diameter of the through hole, and the semiconductor substrate is passed through the through hole to a location including the recess on the back surface. Provided is a solar cell, characterized in that a light-receiving surface side electrode is formed that is electrically connected to the light-receiving surface side that reaches the light-receiving surface side, and a back electrode is formed on the back surface side at a location that does not include the recessed portion. do.
また、上記本発明による太陽電池を製造するための方法
として、半導体基板の受光面に第１の溝を、上記受光面
と反対側の裏面に第２の溝を、それぞれが互いに交差し
、かつ第１の溝と第２の溝の深さの和が上記半導体基板
の厚さ以上となるように形成することを特徴とする方法
ｔｉ供する。Further, as a method for manufacturing the solar cell according to the present invention, a first groove is formed on the light-receiving surface of the semiconductor substrate, and a second groove is formed on the back surface opposite to the light-receiving surface, the grooves intersecting each other, and A method ti is provided, characterized in that the first groove and the second groove are formed so that the sum of the depths is greater than or equal to the thickness of the semiconductor substrate.
この方法によれば本発明の太陽電池裏面の凹部が第２の
溝により形成され、貫通孔が第１と第２の溝の交差位置
に形成される。According to this method, the recess on the back surface of the solar cell of the present invention is formed by the second groove, and the through hole is formed at the intersection of the first and second grooves.
〈作 用〉
本発明の太陽電池において、受光面に形成された溝は多
重反射によυ表面反射率を低減するように作用する。ま
た、凹部は貫通孔の長さを短くし、さらに該貫通孔の径
よりもこの凹部の開口部が大きくなっているので、基板
の受光面側に達するように受光面側電属を形成する際に
、電極材が裏面から途切れることなく容易に受光面側に
達する。<Function> In the solar cell of the present invention, the grooves formed in the light-receiving surface act to reduce the υ surface reflectance due to multiple reflections. In addition, the recess shortens the length of the through hole, and since the opening of the recess is larger than the diameter of the through hole, the light receiving surface side metal is formed so as to reach the light receiving surface side of the substrate. In this case, the electrode material easily reaches the light-receiving surface side without being interrupted from the back surface.
したがって、上記貫通孔の長さは短い方が良く、上記凹
部は例えば断面がＶ字状のように開口部から貫通孔部に
かけて傾斜しているのが好ましい。Therefore, it is better for the length of the through hole to be short, and it is preferable that the recess has a V-shaped cross section and slopes from the opening to the through hole.
また、受光面側電極は、貫通孔の径とほぼ同じ大きさの
領域を受光面に対して占めるだけであるの占
で、電極嘉有率を小さくできる。さらに、受光面側電極
は受光面側にまで達しているので、該電極部での直列抵
抗は非常に小さくなる。また、受光面側電極と裏面電極
が共に裏面側に形成されているので、裏面接続が容易と
なる。Further, since the light-receiving surface side electrode only occupies an area on the light-receiving surface that is approximately the same size as the diameter of the through hole, the electrode coverage ratio can be reduced. Furthermore, since the light-receiving surface side electrode reaches the light-receiving surface side, the series resistance at the electrode portion becomes extremely small. Furthermore, since the light-receiving surface side electrode and the back surface electrode are both formed on the back surface side, back surface connection becomes easy.
本発明の製造方法では、第２の溝を形成することで、容
易に本発明太陽電池の凹部が形成される。In the manufacturing method of the present invention, the concave portion of the solar cell of the present invention can be easily formed by forming the second groove.
そして、第１の溝と第２の溝が平行ではなく交差するよ
うに形成されるので、溝の形成による半導体基板の強度
低下が最小限に抑えられ、上記交差する位置に貫通孔が
形成される。また、受光面側電極を第２の溝を含む場所
にヌトライプ状に形成することで、容易に平坦な電ｆｆ
ｉ’を形成することが可能となる。Since the first groove and the second groove are formed so as not to be parallel but to intersect with each other, a decrease in the strength of the semiconductor substrate due to the formation of the groove is minimized, and a through hole is formed at the above-mentioned intersecting position. Ru. In addition, by forming the light-receiving surface side electrode in a nutripe shape at a location including the second groove, it is possible to easily create a flat electrode.
It becomes possible to form i'.
〈実施例〉 以下実施例によｐ本発明を製造工程に従って説明する。<Example> The present invention will be explained below according to the manufacturing process using Examples.
まず、第１図の断面斜視図に示すように、多結晶シリコ
ン基板１の片面に第１の溝２をダイシング装置により７
Ｊｌ］工する。多結晶シリコン基板１は、ｐ型のキャス
ト基板であフ、１００μｍ角で２００μｍ厚の大きさで
ある。第１の溝２は溝の幅４０μｍ、溝の深さ７０μｍ
、ピッチ１２０μｍとした。溝の幅４０μｍ１溝の深さ
７０μｍの場合、ピッチを１２０μｍとすると度射率が
最適となるからである。尚、ダイシング装置の刃の形状
を変えることで、種々の断面形状の溝が形成でき、最適
な溝の構成も変わる。次に、第１の溝２を形成した面と
反対の面に第１の溝２と直交する方向に第２の溝３を同
様のダイシング装置により加工する。尚、第１と第２の
溝が直交しているので、２００μｍという従来の％以下
の薄型基板に対しても強度的な問題は生じない。溝の幅
は１００μｍ、溝の深さは１３０μｍとし、溝のピッチ
は３．７ｆｆとした。溝の幅等は後で説明する表面電極
形成のためのペーストの塗布の容易性及び表面電極の形
状、特に貫通孔の大きさと数を考慮して定めれば良い。First, as shown in the cross-sectional perspective view of FIG.
Jl] to work. The polycrystalline silicon substrate 1 is a p-type cast substrate, and is 100 μm square and 200 μm thick. The first groove 2 has a groove width of 40 μm and a groove depth of 70 μm.
, the pitch was 120 μm. This is because when the width of the groove is 40 μm and the depth of each groove is 70 μm, the emissivity is optimal when the pitch is 120 μm. Note that by changing the shape of the blade of the dicing device, grooves with various cross-sectional shapes can be formed, and the optimal groove configuration also changes. Next, a second groove 3 is formed on the surface opposite to the surface on which the first groove 2 is formed in a direction perpendicular to the first groove 2 using a similar dicing device. Incidentally, since the first and second grooves are orthogonal to each other, no strength problem arises even with a thin substrate of 200 μm, which is less than 10% of the conventional thickness. The width of the groove was 100 μm, the depth of the groove was 130 μm, and the pitch of the groove was 3.7ff. The width of the groove and the like may be determined by taking into consideration the ease of applying a paste for forming a surface electrode, which will be explained later, and the shape of the surface electrode, especially the size and number of through holes.
尚、以上の加工には、ダイシング装置を用いたが、レー
ザ加工装置等他の装置を用いても良い。Note that although a dicing device was used for the above processing, other devices such as a laser processing device may be used.
次に加工の終了した多結晶基板１の洗浄を行い、表面の
ダメージ層を除去するために、弗硝酸等で化学的なエツ
チング処理を施す。本実施例では、貫通孔４は、第２の
溝８を加工した時点で溝の交差位置に形成されるが、こ
のエツチング処理を利用し、第２の溝３等の深さを少し
浅くしておいて、この段階で貫通孔が形成されるように
しても良い。Next, the processed polycrystalline substrate 1 is cleaned and chemically etched using hydrofluoric acid or the like to remove the damaged layer on the surface. In this embodiment, the through hole 4 is formed at the intersection of the grooves when the second groove 8 is processed, but by using this etching process, the depth of the second groove 3 etc. is made slightly shallower. The through holes may be formed at this stage.
ただ、第２の溝３が形成された時点で貫通孔４が形成さ
れるようにする方が確実である。尚、このエツチング処
理によフ溝の形状、貫通孔４の大きさは変化し、エツチ
ング液、エツチング時間を調整することで、溝の形状、
貫通孔４の大きさを調節できる。本実施例ではほぼ１辺
が５０μｍの穴が形成されている。However, it is more reliable to form the through hole 4 at the time when the second groove 3 is formed. Note that the shape of the groove and the size of the through hole 4 change due to this etching process, and by adjusting the etching solution and etching time, the shape of the groove and the size of the through hole 4 can be changed.
The size of the through hole 4 can be adjusted. In this embodiment, a hole with approximately 50 μm on each side is formed.
次に、以上の加工により、第１の溝２と第２の溝３及び
貫通孔４の形成された多結晶シリコン基板１を用いて、
第２図に示す構造の太陽電池の作製を行う。同図（ａ）
は断面斜視図、同図（ｂ）はＡ −Ａ’断面図、同図（
ｃ）はＢ−Ｂ’断面図及び同図（ｄ）はＣＣ／断面図で
ある。Next, using the polycrystalline silicon substrate 1 in which the first groove 2, the second groove 3, and the through hole 4 were formed by the above processing,
A solar cell having the structure shown in FIG. 2 is manufactured. Figure (a)
is a cross-sectional perspective view, the same figure (b) is an A-A' cross-sectional view, the same figure (
c) is a BB' cross-sectional view, and (d) is a CC/cross-sectional view.
まず、ｐｏｃｇ３を用いた拡散工程によシ上記多結晶シ
リコン基板１の表面にｎ＋層５を形成してＰＮ接合を形
成し、続いて酸素雰囲気中で上記ｎ生理の形成された多
結晶シリコン基板１表面にパッシベーション層となる１
５０Ａの５ｉ０２酸化膜を形成し、さらにこの酸化膜の
上へ受光面側からＴｉＯ２から成る反射防止膜ｆｔ５０
０Ａ形成する。多結晶シリコン基板１には既に貫通孔４
等が形成されているので、この工程で貫通孔４、第二の
溝３内壁にもｎ生理５が形成される。尚、第２図では上
記酸化膜、ＴｉＯ２膜の記載を略している。First, an n+ layer 5 is formed on the surface of the polycrystalline silicon substrate 1 by a diffusion process using POCG3 to form a PN junction, and then the polycrystalline silicon substrate on which the n+ layer is formed in an oxygen atmosphere. 1 becomes a passivation layer on the surface
A 50A 5i02 oxide film is formed, and an anti-reflection film ft50 made of TiO2 is formed on this oxide film from the light-receiving surface side.
0A is formed. A through hole 4 is already formed in the polycrystalline silicon substrate 1.
etc. are formed, so the n-type 5 is also formed on the inner wall of the through hole 4 and the second groove 3 in this step. In addition, in FIG. 2, the description of the oxide film and TiO2 film is omitted.
次に、多結晶シリコン基板１の裏面に残っているｎ生理
５の接合を除去する。従来型素子の場合は、受光面を保
護し、裏面全体をエツチングすれば良いが、本実施例の
場合は第２の溝３部分にｎ＋層５が残るようにする。そ
こで、多結晶シリコン基板１の裏面に耐酸性のワンクス
をパターン印刷し、第２の溝と溝の間の２鱈幅の領域に
ついてエツチングを行い、この後ｎ生理除去部分にＡｌ
ベーストを印刷・焼成してｐ＋Ｍ６からなるＢＳＦ層並
びに裏面電極７の形成を同時に行う。Next, the n-type bond remaining on the back surface of the polycrystalline silicon substrate 1 is removed. In the case of a conventional element, it is sufficient to protect the light-receiving surface and etch the entire back surface, but in the case of this embodiment, the n+ layer 5 is left in the second groove 3 portion. Therefore, a pattern of acid-resistant Wanx was printed on the back surface of the polycrystalline silicon substrate 1, and etching was performed on the two-cod width region between the second grooves.
The base plate is printed and fired to form the BSF layer made of p+M6 and the back electrode 7 at the same time.
次に、第２の溝８内にＡｇを含むペーストを印刷によυ
充填し、焼成して受光面側電極８を形成する。ここで用
いるＡｇペーストはｎ生鉱散層に対して良好な電気的特
性を有しておフ、焼成によシ５ｉ０２膜、ＴｉＯ２膜を
貫通してｎ生鉱散層と電気的に接続されるものである。Next, a paste containing Ag is applied in the second groove 8 by printing.
The light-receiving surface side electrode 8 is formed by filling and firing. The Ag paste used here has good electrical properties with respect to the n-mineralized layer, and when fired, it penetrates through the 5i02 film and the TiO2 film and is electrically connected to the n-originated ore-dispersed layer. It is something that
本実施例では、３回の重ね印刷で充填が完了した。これ
は、Ａｇペーストの粘度、塗布条件等によシ変化し、ま
た、粘度調整により、貫通孔４からのＡｇペーストのだ
れの問題も発生しないことが判った。In this example, filling was completed by repeating printing three times. This varies depending on the viscosity of the Ag paste, coating conditions, etc., and it has been found that by adjusting the viscosity, the problem of Ag paste dripping from the through holes 4 does not occur.
以上によシ形成される受光面側電極８は、受光面側から
見た場合、−辺が約５０μｍ、ピッチ１２０μｍのドツ
ト電極となっておち、裏面側から見た場合、幅１００μ
ｍのグリッド電価となっている。また、受光面側表面の
ｎ生理５と第２の溝３内壁のｎ生理５とが貫通孔４を介
して連続しているので、受光面電極８の受光面側との電
気的接触状態に問題は生じない。When viewed from the light-receiving surface side, the light-receiving surface-side electrode 8 formed as described above is a dot electrode with a negative side of approximately 50 μm and a pitch of 120 μm, and when viewed from the back surface, it is a dot electrode with a width of 100 μm.
The grid electricity price is m. In addition, since the n-type 5 on the light-receiving surface side surface and the n-type 5 on the inner wall of the second groove 3 are continuous through the through hole 4, they are in electrical contact with the light-receiving surface side of the light-receiving surface electrode 8. No problems arise.
以上により作製された太陽電池の特性を測定した結果、
受光面側電極の太陽電池受光面に占める割合が従来の３
〜４％の約１／／１ｏと小さくなった事に伴い電流が増
加し、また、電極を埋込み構造とし、接触面積を大きく
したので曲線因子も０．７５以上と従来よフ高い値が得
られ、高効率の太陽電池となっていることがわかった。As a result of measuring the characteristics of the solar cell produced as above,
The ratio of the light-receiving surface side electrode to the solar cell light-receiving surface is 3
The current increases as the current decreases to approximately 1//1o, which is ~4%, and the electrode is embedded, increasing the contact area, resulting in a fill factor of 0.75 or higher, which is higher than before. It was found that the solar cell was highly efficient.
第３図に本実施例の太陽電池のモジュール化の例を示す
。パターン配線８１，８２．８８の形成された基板３０
上に、太陽電池Ａの裏面電極７がパターン配線３１に、
受光面側電極８がパターン配線３２に接続され、太陽電
池Ｂの裏面側電極７がパターン配線３３に、受光面側電
極８がパターン配線３３に接続されて、２個の太陽電池
が直列に接続されている。FIG. 3 shows an example of modularization of the solar cell of this embodiment. Substrate 30 on which pattern wiring 81, 82, 88 is formed
On the top, the back electrode 7 of the solar cell A is connected to the pattern wiring 31,
The light-receiving side electrode 8 is connected to the pattern wiring 32, the back side electrode 7 of the solar cell B is connected to the pattern wiring 33, the light-receiving side electrode 8 is connected to the pattern wiring 33, and the two solar cells are connected in series. has been done.
本実施例の太陽電池では、第２の溝３にＡｇペーストが
完全に充填されて受光面側電極が平坦に形成されている
ので、良好な電気的接触状態を保った配線、接続が容易
に行える。In the solar cell of this example, the second groove 3 is completely filled with Ag paste and the light-receiving surface side electrode is formed flat, making it easy to wire and connect while maintaining good electrical contact. I can do it.
以上示した実施例では、第２の溝３に受光面電極８を形
成するのに、印刷法を用いたが、これは蒸着法等音用い
る場合に比べて非常に低コヌトでの作製ができるからで
あフ、第２の溝が０字状の断面を有しており、かつ第１
と第２の溝がつながって貫通孔となっているために印刷
法による電極の形成を容易にしている。In the embodiment shown above, the printing method was used to form the light-receiving surface electrode 8 in the second groove 3, but this method can be manufactured at a much lower cost than when using the vapor deposition method. empty, the second groove has a zero-shaped cross section, and the first groove has a zero-shaped cross section;
Since the first groove and the second groove are connected to form a through hole, it is easy to form the electrode by a printing method.
尚、本実施例では裏面の凹部を溝で形成しているが、例
えばつりがね状断面を有する穴を多数形成することも可
能であり、また、印刷法によらず蒸着等によって電極を
形成することも可能である。In this example, the concave portion on the back surface is formed by a groove, but it is also possible to form a large number of holes having a bell-shaped cross section, for example, and the electrodes may be formed by vapor deposition or the like instead of the printing method. It is also possible to do so.
また、溝内部にはｎ生理を形成せずに受光面側電極を形
成することも可能である。Furthermore, it is also possible to form the light-receiving surface side electrode inside the groove without forming the n-type electrode.
〈発明の効果〉
本発明の太陽電池は、太陽電池の受光面積が増加して発
生電流が向上し、電極形成においてシャドウロスを問題
にすることなしに電極を設計できるので、大きな曲線因
子の値が実現され、受光面に形成されている溝によって
入射光の利用効率が高くなり、受光面側電極部の抵抗も
小さくなって、高効率となる。しかも、容易に作製でき
るので安価に製造することができる。<Effects of the Invention> The solar cell of the present invention increases the light-receiving area of the solar cell, improves the generated current, and allows electrodes to be designed without shadow loss being a problem in electrode formation, resulting in a large fill factor value. The grooves formed in the light-receiving surface increase the utilization efficiency of incident light, and the resistance of the electrode portion on the light-receiving surface side also decreases, resulting in high efficiency. Moreover, since it can be easily manufactured, it can be manufactured at low cost.
また、基板の裏面だけで電極形成を行っているので、モ
ジュール化する場合、直・並列回路をパターン化した基
板の上へ直接マウントするだけで配線が完了する。従っ
て、従来のモジュール化工程に比べて工程が簡略化され
、モジュールとした場合の低価格化も実現する。Furthermore, since electrodes are formed only on the back side of the substrate, when modularizing, wiring can be completed by simply mounting the series/parallel circuits directly onto the patterned substrate. Therefore, the process is simplified compared to the conventional modularization process, and the cost of the module is also reduced.
本発明の製造方法によれば、容易に本発明の太陽電池の
製造ができ、安価で高効率の太陽電池を供給することが
可能となる。According to the manufacturing method of the present invention, the solar cell of the present invention can be easily manufactured, and it becomes possible to supply a solar cell with low cost and high efficiency.
第１図は本発明の実施例の太陽電池作製に用いる多結晶
シリコン基板の断面斜視図、第２図は本実施例の太陽電
池の構造図、第３図は本実施例の裏面配線によるモジュ
ール化の例を示す図、第４゜５図は従来のラップ・アラ
ウンド法を示す図、第６図は本土願人が先に提案した太
陽電池の１例を示す図である。
■・・・多結晶シリコン基板 ２・・・第１の溝３・
・・第３の溝 ４・・・貫通孔 ５・・・ｎ十層６
・・・ｐ生理 ７・・・裏面電極 ８・・・受光面
側電極 ３０・・・基板 ８１．８２．８８・・・
パターン配線
代理人 弁理士 梅 １） 勝（他２名）（Ｃ）
８−８’前ｉ国
Ｃｄ’）Ｃ−Ｃ’噸ｌ凹
第４ｆｉFIG. 1 is a cross-sectional perspective view of a polycrystalline silicon substrate used for manufacturing a solar cell according to an example of the present invention, FIG. 2 is a structural diagram of a solar cell according to this example, and FIG. 3 is a module with backside wiring according to this example. Figures 4-5 are diagrams showing an example of the conventional wrap-around method, and Figure 6 is a diagram showing an example of a solar cell previously proposed by Mainland. ■... Polycrystalline silicon substrate 2... First groove 3.
...Third groove 4...Through hole 5...n ten layers 6
...P physiology 7...Back electrode 8...Light-receiving surface side electrode 30...Substrate 81.82.88...
Pattern wiring agent Patent attorney Ume 1) Katsu (2 others) (C) 8-8'Pre-i country Cd') C-C'噸l dent 4th fi
Claims (1)
反対側の裏面に上記溝と重なるように凹部が形成され、
該凹部と上記溝の重なる位置に貫通孔が形成され、上記
凹部開口部は貫通孔の径より大きくなっており、上記裏
面の上記凹部を含む場所に上記貫通孔を介して半導体基
板の受光面側に達する受光面側と電気的に接続された受
光面側電極が形成され、上記裏面側の上記凹部を含まな
い場所に裏面電極が形成されていることを特徴とする太
陽電池。 ２、半導体基板の受光面に第１の溝を、上記受光面と反
対側の裏面に第２の溝を、それぞれが互いに交差し、か
つ第１の溝と第２の溝の深さの和が上記半導体基板の厚
さ以上となるように形成することを特徴とする請求項１
記載の太陽電池の製造方法。[Claims] 1. A groove is formed on the light-receiving surface of the semiconductor substrate, and a recess is formed on the back surface opposite to the light-receiving surface so as to overlap with the groove,
A through hole is formed at a position where the recess and the groove overlap, the opening of the recess is larger than the diameter of the through hole, and the light-receiving surface of the semiconductor substrate is passed through the through hole to a location on the back surface that includes the recess. A solar cell characterized in that a light-receiving surface side electrode is formed that is electrically connected to the light-receiving surface side that reaches the side, and a back electrode is formed at a location on the back surface side that does not include the recessed portion. 2. A first groove on the light-receiving surface of the semiconductor substrate and a second groove on the back surface opposite to the light-receiving surface, each of which intersects each other, and the sum of the depths of the first groove and the second groove. Claim 1, wherein the semiconductor substrate is formed so that the thickness thereof is greater than or equal to the thickness of the semiconductor substrate.
The method for manufacturing the solar cell described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2120790A JPH0415962A (en) | 1990-05-09 | 1990-05-09 | Solar cell and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2120790A JPH0415962A (en) | 1990-05-09 | 1990-05-09 | Solar cell and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415962A true JPH0415962A (en) | 1992-01-21 |
Family
ID=14795065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2120790A Pending JPH0415962A (en) | 1990-05-09 | 1990-05-09 | Solar cell and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415962A (en) |
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| JP2002527910A (en) * | 1998-10-12 | 2002-08-27 | パシフィック ソーラー ピー ティ ワイ リミテッド | Melt-through contact formation method |
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| JP2005510885A (en) * | 2001-11-26 | 2005-04-21 | シェル・ゾラール・ゲーエムベーハー | Manufacture of solar cells with back contacts |
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