JPH04155929A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPH04155929A
JPH04155929A JP28155290A JP28155290A JPH04155929A JP H04155929 A JPH04155929 A JP H04155929A JP 28155290 A JP28155290 A JP 28155290A JP 28155290 A JP28155290 A JP 28155290A JP H04155929 A JPH04155929 A JP H04155929A
Authority
JP
Japan
Prior art keywords
wiring
film
aluminum
aluminum film
crystal grain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28155290A
Other languages
Japanese (ja)
Inventor
Kiyoko Washizu
鷲津 聖子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP28155290A priority Critical patent/JPH04155929A/en
Publication of JPH04155929A publication Critical patent/JPH04155929A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent stress migration and improve reliability by injecting, by the ion implantation method, a metal element having a large atomic weight into an aluminum film for wiring immediately after it is formed by the sputtering method to obtain an amorphous film by breaking the crystal grain boundary of the aluminum film for the wiring explained above. CONSTITUTION:An oxide film 4 is formed as an interlayer insulating film on a gate wiring 3 formed on a field oxide film 2. Next, the interlayer insulating film 4 on the source/drain region 5 of a semiconductor substrate 1 is etched, a contact hole is formed and an aluminum film 6 for wiring is formed by the sputtering method. The aluminum film just produced includes crystal grain boundary. Size of crystal grain depends on temperature of sputtering and becomes larger as the sputtering temperature rises. In order to break the crystal grain boundary, a metal element having the atom number of 20 or higher such as tungsten, molybdenum, paradium and titanium, etc., is implanted by the ion implantation method into the aluminum film 6 for wiring to obtain the amorphous of the aluminum for the wiring.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特にアルミニ
ウム配線の形成方法に関するものであ2〔従来の技術〕 現在、半導体装置の配線材料としては、主にアルミニウ
ムが用いられてお9、その形成にあたっては、第2図の
70−に示す様に、まず、半導体基板1上に厚いフィー
ルド酸化膜2を形成し、上記フィールド酸化膜2上に、
ゲート配線3を形成する(α)。次に、層間絶縁膜とし
て酸化膜4をOVD法等により形成しCb)、半導体基
板1のソース・ドレイン領域5上の上記層間絶縁膜4を
ζ  エツチングし、コンタクト穴を形成する(C)。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming aluminum wiring.2 [Prior Art] Currently, aluminum is used as a wiring material for semiconductor devices. , aluminum is mainly used 9. In its formation, a thick field oxide film 2 is first formed on the semiconductor substrate 1, as shown at 70- in FIG. ,
Gate wiring 3 is formed (α). Next, an oxide film 4 is formed as an interlayer insulating film by an OVD method (Cb), and the interlayer insulating film 4 on the source/drain region 5 of the semiconductor substrate 1 is etched to form a contact hole (C).

〕  更に、配線用のアルミニウム膜6をスパッタ法で
形成しくd)、フォトリング:7フイー法、及びエテ 
 ッチング法により上記配線用のアルミニウム膜6をパ
ターニングする(−)、製造方法であった。
] Furthermore, an aluminum film 6 for wiring is formed by a sputtering method.
The manufacturing method involved patterning (-) the aluminum film 6 for wiring using a etching method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、配線構造の微細化が進み、配線幅の細い
部分では、幅方向にせいぜ〜九−つの結晶粒しか存在し
ないバンブー構造になる。そうすると、隣りあった結晶
粒の結晶軸方向(tll)if近接していた場合、後の
工程で加えられる熱応力によりボイドが発生す漬が、そ
のボイドがスリット状になりストレスマイグレーション
に至る、という問題点を有していた。
However, as the wiring structure becomes finer, a bamboo structure is formed in which only nine crystal grains are present in the width direction in the narrow wiring width portion. Then, if adjacent crystal grains are close to each other in the crystal axis direction (tll), voids will be generated due to thermal stress applied in a later process, but the voids will become slit-shaped and lead to stress migration. It had some problems.

日経マイクロデバイス 1990年5月手崎他 ストレ
スマイグレーションによるA1の断線機構を定量的に解
析 〔課題を解決するための手段〕 本発明の半導体装置の製造方法は、半導体装置の配線構
造を形成するにあたり、スパッタ法により形成された直
後の配線用のアルミニウム膜に、原子量の大きいタング
ステン、モリブデン、パラジウム、チタン等の金属元素
を、イオン・インプラ法により注入し、上記配線用のア
ルミニウム膜の結晶粒界を破壊し、アモルファス化する
ことを特徴とする。
Nikkei Micro Devices, May 1990 Tezaki et al. Quantitative analysis of the disconnection mechanism of A1 due to stress migration [Means for solving the problem] The method for manufacturing a semiconductor device of the present invention includes the following steps in forming the wiring structure of a semiconductor device: Metal elements with large atomic weights such as tungsten, molybdenum, palladium, and titanium are implanted into the aluminum film for wiring immediately after it is formed by the sputtering method using the ion implantation method to form the crystal grain boundaries of the aluminum film for wiring. It is characterized by destruction and becoming amorphous.

〔実施例〕〔Example〕

第1図のフローは、本発明の実施例における断面図であ
る。1は半導体基板、2はフィールド酸化膜である。ま
ず、上記フィールド酸化膜2上に多結晶シリコン等によ
りゲート配線3を形成しくα)、上記ゲート配線3上に
、層間絶縁膜として酸化膜4をOVD法等により形成す
る(b)。
The flow shown in FIG. 1 is a sectional view of an embodiment of the present invention. 1 is a semiconductor substrate, and 2 is a field oxide film. First, a gate wiring 3 is formed of polycrystalline silicon or the like on the field oxide film 2 (a), and an oxide film 4 is formed as an interlayer insulating film on the gate wiring 3 by an OVD method or the like (b).

次に、半導体基板1のソース・ドレイン領域5上の上記
層間絶縁膜4をエツチングし、コンタクト穴を形成しく
C)、配線用のアルミニウム膜6をスパッタ法により形
成する(d)。スパッタ法により形成された直後のアル
ミニウム膜には、第1図(d)に示すとおり結晶粒界が
存在し、結晶粒の大きさはスパッタ時の温度に依存し、
高温でスパッタされる程大きくなる。この結晶粒界を破
壊するために、上記配線用のアルミニウム膜6に、タン
グステン、モリブデン、パラジウム、チタン等、原子番
号が20以上の金属元素をイオン・インプラ法により注
入し、配線用のアルミニウム膜をアモルファス化する(
1゜この時の条件はドーズ量にして1014〜1017
ケ/d、 加速電圧60KeV以上とするが、加速電圧
が高い程、結晶構造に対するダメージは大きく有効であ
る。
Next, the interlayer insulating film 4 on the source/drain region 5 of the semiconductor substrate 1 is etched to form a contact hole (c), and an aluminum film 6 for wiring is formed by sputtering (d). As shown in Figure 1(d), crystal grain boundaries exist in the aluminum film immediately after being formed by sputtering, and the size of the crystal grains depends on the temperature during sputtering.
The higher the temperature of sputtering, the larger it becomes. In order to destroy this crystal grain boundary, a metal element having an atomic number of 20 or more, such as tungsten, molybdenum, palladium, titanium, etc., is implanted into the aluminum film 6 for wiring using the ion implantation method. to amorphous (
1゜The conditions at this time are 1014 to 1017 in terms of dose.
The acceleration voltage is set to be 60 KeV or more, but the higher the acceleration voltage, the more effective the damage to the crystal structure is.

更に、アモルファス化した配線用アルミニウム族7を、
フォトリソグラフィー法及び、エツチング法によりバタ
ーニングする(1)。
Furthermore, amorphous aluminum group 7 for wiring,
Buttering is performed by photolithography and etching (1).

なお、第1図の実施例においては、配線材料としてアル
ミニウムを用いたが、純粋なアルミニウムに限らず、シ
リコン、鋼等の金属を含有しているアルミニウムを用い
ることも可能である。
Although aluminum is used as the wiring material in the embodiment shown in FIG. 1, it is not limited to pure aluminum, and aluminum containing metals such as silicon and steel can also be used.

〔発明の効果〕〔Effect of the invention〕

以上述べた様に、本発明によれば、スパッタ法により形
成された直後の配線用のアルミニウム膜に、原子量の大
きいタングステン、モリブデン、パラジウム、チタン等
の金属元素を、イオン・インプラ法により注入し、上記
配線用のアルミニウム膜の結晶粒界を破壊し、アモルフ
ァス化することにより、ストレスマイグレーシランを防
止し、信頼性を向上させることができた。
As described above, according to the present invention, a metal element having a large atomic weight such as tungsten, molybdenum, palladium, or titanium is implanted by the ion implantation method into an aluminum film for wiring immediately after it is formed by the sputtering method. By destroying the crystal grain boundaries of the aluminum film for wiring and making it amorphous, it was possible to prevent stress migration and improve reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(eL)〜(1)は本発明の一実施例の主要断面
図、第2図(α)〜(=)は従来例の主要断面図。 1・・・・・・・・・半導体基板 2・・・・・・・・・フィールド酸化膜3・・・・・・
・・・ゲート配線 4・・・・・・・・・層間絶縁膜 5・・・・・・・・・ソース・ドレイン領域6・・・・
・・・・・配線用のアルミニウム膜708.10006
.アエヤ7アス化した配線用のアルミニウム膜 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木喜ミ部(他1名)°紹1・」 、i21
FIGS. 1(eL) to (1) are main sectional views of an embodiment of the present invention, and FIGS. 2(α) to (=) are main sectional views of a conventional example. 1... Semiconductor substrate 2... Field oxide film 3...
...Gate wiring 4...Interlayer insulating film 5...Source/drain region 6...
...Aluminum film for wiring 708.10006
.. Aluminum film for wiring that has become 7-A

Claims (1)

【特許請求の範囲】[Claims]  半導体装置の配線構造を形成するにあたり、スパッタ
法により形成された直後の配線用のアルミニウム膜に、
タングステン、モリブデン、パラジウム、チタン等、原
子番号が20以上の金属元素をイオン・インプラ法によ
り注入し、上記配線用のアルミニウム膜の結晶粒界を破
壊し、アモルファス化することを特徴とする半導体装置
の製造方法。
When forming the wiring structure of a semiconductor device, an aluminum film for wiring is coated immediately after being formed by sputtering.
A semiconductor device characterized in that a metal element having an atomic number of 20 or more, such as tungsten, molybdenum, palladium, or titanium, is implanted by an ion implantation method to destroy the crystal grain boundaries of the aluminum film for wiring and make it amorphous. manufacturing method.
JP28155290A 1990-10-19 1990-10-19 Production of semiconductor device Pending JPH04155929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28155290A JPH04155929A (en) 1990-10-19 1990-10-19 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28155290A JPH04155929A (en) 1990-10-19 1990-10-19 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04155929A true JPH04155929A (en) 1992-05-28

Family

ID=17640776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28155290A Pending JPH04155929A (en) 1990-10-19 1990-10-19 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04155929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19527368A1 (en) * 1994-07-26 1996-02-08 Toshiba Kawasaki Kk Semiconductor device fabrication method
US20150279809A1 (en) * 2014-03-31 2015-10-01 Rama I. Hegde Structure for aluminum pad metal under ball bond

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19527368A1 (en) * 1994-07-26 1996-02-08 Toshiba Kawasaki Kk Semiconductor device fabrication method
DE19527368C2 (en) * 1994-07-26 2001-09-13 Toshiba Kawasaki Kk Manufacturing method of a semiconductor device with single crystal wiring layers
US20150279809A1 (en) * 2014-03-31 2015-10-01 Rama I. Hegde Structure for aluminum pad metal under ball bond
US9343422B2 (en) * 2014-03-31 2016-05-17 Freescale Semiconductor, Inc. Structure for aluminum pad metal under ball bond

Similar Documents

Publication Publication Date Title
JPH0456325A (en) Manufacture of semiconductor device
JPS5815250A (en) Manufacture of semiconductor device
JPH0611076B2 (en) Method for manufacturing semiconductor device
JPH04155929A (en) Production of semiconductor device
JPH06125057A (en) Semiconductor memory containing ferroelectric film
JPS59200418A (en) Manufacture of semiconductor device
JP2773146B2 (en) Method for manufacturing semiconductor device
JPS6292470A (en) Semiconductor device
JPH10125864A (en) Manufacture of semiconductor device
JP3196241B2 (en) Method for manufacturing semiconductor device
JPH01181469A (en) Semiconductor device and its manufacture
KR100186985B1 (en) Manufacture of semiconductor device
JPS62104138A (en) Semiconductor device
JPH09266192A (en) Manufacture of semiconductor device
JPH1074706A (en) Semiconductor device and its manufacture
JPS58155767A (en) Manufacture of metal oxide semiconductor type semiconductor device
JPH03187226A (en) Manufacture of semiconductor device
JPH07107926B2 (en) Method for manufacturing semiconductor capacitive element
JPH0389522A (en) Wiring conductor forming method for semiconductor device
JPS6347950A (en) Semiconductor device
JPH01122165A (en) Manufacture of semiconductor device
JPS61283153A (en) Semiconductor device
JPH03187244A (en) Semiconductor device and manufacture thereof
JPH0235769A (en) Semiconductor device
JPH02292866A (en) Manufacture of mis type semiconductor device