JPS6347950A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6347950A JPS6347950A JP19310686A JP19310686A JPS6347950A JP S6347950 A JPS6347950 A JP S6347950A JP 19310686 A JP19310686 A JP 19310686A JP 19310686 A JP19310686 A JP 19310686A JP S6347950 A JPS6347950 A JP S6347950A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- point metal
- silicide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 238000002844 melting Methods 0.000 claims abstract description 28
- 230000008018 melting Effects 0.000 claims abstract description 26
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 14
- 229920005591 polysilicon Polymers 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 description 9
- 239000003870 refractory metal Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
この発明は半導体装置に関し、特にポリサイド構造の電
極配線形成技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to semiconductor devices, and more particularly to a technique for forming electrode wiring having a polycide structure.
［従来の技術］
従来より、半導体装置の電極配線用として高融点金属シ
リサイドおよび高融点金属が用いられてきた。特に、Ｍ
Ｏ３型半導体デバイスにおいては、高融点金属シリサイ
ドまたは高融点金属とポリシリコンとの２層構造（ポリ
サイド構造）がゲート電極として用いられている。[Prior Art] Refractory metal silicides and refractory metals have conventionally been used for electrode wiring of semiconductor devices. In particular, M
In O3 type semiconductor devices, a two-layer structure (polycide structure) of refractory metal silicide or refractory metal and polysilicon is used as a gate electrode.
第２Ａ図および第２Ｂ図は、従来のポリサイド構造の電
極配線を有する半導体装置を示す断面図である。FIGS. 2A and 2B are cross-sectional views showing a semiconductor device having a conventional electrode wiring having a polycide structure.
第２Ａ図において、半導体基板１表面にポリシリコン膜
や酸化膜などの下地段差パターン２、および二酸化シリ
コン膜３が形成されており、下地段差パターン２と二酸
化シリコン膜３間に段差部が形成されている。下地段差
パターン２表面および二酸化シリコン膜３表面にポリシ
リコン膜４１が形成されている。このポリシリコン膜４
１は、高融点金属シリサイド膜または高融点金属膜との
２層構造（ポリサイド構造）として用いられるもので、
通常０．２〜０．３μｍの膜厚のものが用いられる。ま
た、このポリシリコン膜４１は配線抵抗を下げる目的で
燐（Ｐ）がドープされている。In FIG. 2A, a base step pattern 2 such as a polysilicon film or an oxide film, and a silicon dioxide film 3 are formed on the surface of a semiconductor substrate 1, and a step portion is formed between the base step pattern 2 and the silicon dioxide film 3. ing. A polysilicon film 41 is formed on the surface of the underlying step pattern 2 and the silicon dioxide film 3. This polysilicon film 4
1 is used as a two-layer structure (polycide structure) with a high melting point metal silicide film or a high melting point metal film,
Usually, a film thickness of 0.2 to 0.3 μm is used. Further, this polysilicon film 41 is doped with phosphorus (P) for the purpose of lowering wiring resistance.
ポリシリコン膜４１表面にスパッタリング法により電極
配線用の高融点金属シリサイド膜または高融点金属膜、
たとえばモリブデンシリサイド膜５０が形成されている
。素子の高速化に伴い配線の低抵抗化が要求され、配線
のシート抵抗を下げる目的で、このモリブデンシリサイ
ド膜５０の膜厚としては０．２μｍ以上の膜厚が＝般に
用いられている。そして、モリブデンシリサイド膜５０
をスパッタリング法で形成した場合、段差部において膜
の成長の仕方が異なることによりこのモリブデンシリサ
イド膜５０に不整合部７０が生じる。A high melting point metal silicide film or a high melting point metal film for electrode wiring is formed on the surface of the polysilicon film 41 by sputtering.
For example, a molybdenum silicide film 50 is formed. As the speed of devices increases, there is a demand for lower wiring resistance, and for the purpose of lowering the sheet resistance of wiring, the thickness of the molybdenum silicide film 50 is generally 0.2 μm or more. And molybdenum silicide film 50
When the molybdenum silicide film 50 is formed by sputtering, a mismatch portion 70 occurs in the molybdenum silicide film 50 due to the difference in the way the film grows at the stepped portion.
第２Ｂ図は、第２Ａ図のポリサイド構造の電極配線を熱
処理した後の状態を示したもので、この熱処理によりモ
リブデンシリサイド膜５０の結晶５１は熱処理後のモリ
ブデンシリサイド膜を示している。FIG. 2B shows the state after the electrode wiring having the polycide structure shown in FIG. 2A has been heat-treated. As a result of this heat treatment, the crystals 51 of the molybdenum silicide film 50 show the molybdenum silicide film after the heat treatment.
［発明が解決しようとする問題点コ
ところで、モリブデンシリサイド膜５０を厚く形成する
場合、電極配線形成後の熱処理により、第２Ｂ図に示す
ようにモリブデンシリサイド膜５１に断線８が生じるこ
とがある。その理由は、熱処理によるモリブデンシリサ
イド膜５０の結晶粒径の増大に伴ってこの膜の体積収縮
が起こりこの膜に強い内部応力が発生し、この内部応力
によって膜強度の弱い不整合部７０が断線８に至ると考
えられている。モリブデンシリサイド膜５１に断線８が
発生すれば、ポリサイド構造の電極配線の電気伝導が阻
害されて配線抵抗が上昇し、このため、半導体装置の製
造の歩留りや信頼性の低下が発生するなどの問題点があ
った。[Problems to be Solved by the Invention] By the way, when the molybdenum silicide film 50 is formed to be thick, a disconnection 8 may occur in the molybdenum silicide film 51 as shown in FIG. 2B due to heat treatment after forming the electrode wiring. The reason for this is that as the crystal grain size of the molybdenum silicide film 50 increases due to heat treatment, the volume of this film shrinks and a strong internal stress is generated in the film. It is thought that it will reach 8. If a disconnection 8 occurs in the molybdenum silicide film 51, the electrical conduction of the electrode wiring of the polycide structure is inhibited and the wiring resistance increases, resulting in problems such as a decrease in the yield and reliability of semiconductor device manufacturing. There was a point.
この発明は」１記のような問題点を解消するためになさ
れもので、ポリサイド構造の電極配線の熱処理時におい
て、高融点金属シリサイド膜または高融点金属膜の断線
を防いで配線抵抗の上昇を抑えることができる半導体装
置を得ることを目的とする。This invention was made in order to solve the problem mentioned in item 1 above, and it prevents the increase in wiring resistance by preventing disconnection of the high-melting point metal silicide film or the high-melting point metal film during heat treatment of electrode wiring having a polycide structure. The purpose is to obtain a semiconductor device that can suppress the noise.
［問題点を解決するための手段］
この発明に係る半導体装置は、段差部に形成される電極
配線用の高融点金属シリサイド膜または高融点金属膜の
膜厚を０．２μｍ以下にしたものである。[Means for Solving the Problems] A semiconductor device according to the present invention is such that the film thickness of the high melting point metal silicide film or the high melting point metal film for electrode wiring formed in the stepped portion is 0.2 μm or less. be.
［作用コ
この発明においては、高融点金属シリサイド膜または高
融点金属膜の膜厚を０．２μｍ以下にするので、電極配
線の熱処理時にこれらの膜に発生する内部応力が低下し
、このため、高融点金属シリサイド膜または高融点金属
膜の不整合部に断線が生じなくなる。[Function] In this invention, since the film thickness of the high melting point metal silicide film or the high melting point metal film is set to 0.2 μm or less, the internal stress generated in these films during heat treatment of the electrode wiring is reduced. No disconnection occurs in the mismatched portion of the high melting point metal silicide film or the high melting point metal film.
［実施例］ 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
なお、この実施例の説明において、従来の技術の説明と
重複する部分については適宜その説明を省略する。In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.
第１Ａ図〜第１Ｆ図は、この発明の実施例であるポリサ
イド構造の電極配線を宵する半導体装置の製造方法を説
明するための工程断面図である。FIGS. 1A to 1F are process cross-sectional views for explaining a method of manufacturing a semiconductor device using electrode wiring having a polycide structure, which is an embodiment of the present invention.
この製造方法について説明すると、まず、シリコン２！
！ｉ２１表面に下地段差パターン２および二酸化シリコ
ン膜３を形成する（第１Ａ図）。次に、下地段差パター
ン２表面および二酸化シリコン膜３表面に０．２〜０．
３μｍの膜厚のポリシリコン膜４０を形成する（第１Ｂ
図）。次に、配線抵抗を下げる目的でポリシリコン膜４
０に燐（Ｐ）をドープする。４１は燐がドープされたポ
リシリコン膜を示している（第１Ｃ図）。次に、ポリシ
リコン膜４１表面にスパッタリング法により膜厚が０．
２μｍ以下の高融点金属シリサイド膜または高融点金
属膜、たとえばモリブデンシリサイド膜５２を形成する
。このとき、段差部において膜の成長の仕方が異なるこ
とによりモリブデンシリサイド膜５２に不整合部７１が
生じる。次に、ポリサイド構造の電極配線を１０００℃
前後の温度て熱処理する。このとき、従来技術で述べた
ようにモリブデンシリサイド膜５２の結晶粒径は数１０
０Ａから数１０００Ａに増大する。５３は熱処理後のモ
リブデンシリサイド膜を示している。モリブデンシリサ
イド膜５２の結晶粒径の増大に伴ってこの膜の体積収縮
が起こりこの膜に内部応力が発生するが、この実施例で
は、モリブデンシリサイド膜５２の膜厚を０． ２μｍ
以下にしているため、この内部応力は小さくなり、不整
合部７１で断線が生じない（第１Ｅ図）。次に、モリブ
デンシリイド膜５３表面にＢＰＳＧからなるスムースコ
ート膜を形成し、この後、スムースコート膜をリフロー
する。６はリフロー後のスムースコート膜を示している
（第１Ｆ図）。To explain this manufacturing method, first, Silicon 2!
! A base step pattern 2 and a silicon dioxide film 3 are formed on the i21 surface (FIG. 1A). Next, the surface of the base step pattern 2 and the silicon dioxide film 3 are coated with 0.2-0.
A polysilicon film 40 with a thickness of 3 μm is formed (first B).
figure). Next, in order to lower the wiring resistance, a polysilicon film 4
0 is doped with phosphorus (P). Reference numeral 41 indicates a polysilicon film doped with phosphorus (FIG. 1C). Next, the surface of the polysilicon film 41 is coated with a sputtering method to reduce the film thickness to 0.
A refractory metal silicide film or a refractory metal film of 2 μm or less, for example, a molybdenum silicide film 52 is formed. At this time, a mismatched portion 71 is generated in the molybdenum silicide film 52 due to the difference in the way the film grows at the stepped portion. Next, the electrode wiring of the polycide structure was heated to 1000°C.
Heat treatment at different temperatures. At this time, as described in the prior art, the crystal grain size of the molybdenum silicide film 52 is several 10
It increases from 0A to several thousand A. 53 indicates a molybdenum silicide film after heat treatment. As the crystal grain size of the molybdenum silicide film 52 increases, the volume of this film shrinks and internal stress is generated in the film, but in this embodiment, the thickness of the molybdenum silicide film 52 is set to 0. 2μm
Since the internal stress is set as below, this internal stress is reduced and no wire breakage occurs at the mismatched portion 71 (FIG. 1E). Next, a smooth coat film made of BPSG is formed on the surface of the molybdenum silide film 53, and then the smooth coat film is reflowed. 6 shows the smooth coat film after reflow (Fig. 1F).
なお、上記実施例では、ポリシリコン膜とモリブデンシ
リサイド膜とからなるポリサイド構造の電極配線につい
て示したが、モリブデンシリサイド膜の代わりに、タン
グステンシリサイド膜、チタンシリサイド膜、タンタル
シリサイド膜などの高融点金属シリサイド膜を用いても
よく、また、モリブデン膜、タングステン膜、チタン膜
、タンタル膜などの高融点金属膜を用いてもよい。In addition, in the above embodiment, an electrode wiring having a polycide structure consisting of a polysilicon film and a molybdenum silicide film was shown, but instead of the molybdenum silicide film, a high melting point metal such as a tungsten silicide film, a titanium silicide film, a tantalum silicide film, etc. A silicide film may be used, or a high melting point metal film such as a molybdenum film, a tungsten film, a titanium film, or a tantalum film may be used.
［発明の効果コ
以上のようにこの発明によれば、段差部に形成される電
極配線用の高融点金属シリサイド膜または高融点金属膜
の膜厚を０． ２μｍ以下にしたので、ポリサイド構造
の電極配線の熱処理時において、高融点金属シリサイド
膜または高融点金属膜の断線を防いで配線抵抗の上昇を
抑えるこができる半導体装置を得ることができる。この
ため、半導体装置の製造の歩留りや信頓性が向上する。[Effects of the Invention] As described above, according to the present invention, the film thickness of the high melting point metal silicide film or the high melting point metal film for electrode wiring formed in the stepped portion is reduced to 0. Since the thickness is set to 2 μm or less, it is possible to obtain a semiconductor device in which disconnection of the high melting point metal silicide film or the high melting point metal film can be prevented and an increase in wiring resistance can be suppressed during heat treatment of the electrode wiring having a polycide structure. Therefore, the yield and reliability of manufacturing semiconductor devices are improved.
第１Ａ図〜第１Ｆ図は、この発明の実施例であるポリサ
イド構造の電極配線を何する半導体装置の製造方法を説
明するための工程断面図である。
第２Ａ図および第２Ｂ図は、従来のポリサイド構造の電
極配線を有する半導体装置を示す断面図である。
図において、１はシリコン基板、２は下地段差パターン
、３は二酸化シリコン膜、４０．４１はポリシリコン膜
、５０．５１，５２．５３はモリブデンシリサイド膜、
６はスムースコート膜、７０．７１は不整合部、８は断
線である。
なお、各図中同一符号は同一または相当部分を示す。FIGS. 1A to 1F are process cross-sectional views for explaining a method of manufacturing a semiconductor device for forming electrode wiring of a polycide structure according to an embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views showing a semiconductor device having a conventional electrode wiring having a polycide structure. In the figure, 1 is a silicon substrate, 2 is a base step pattern, 3 is a silicon dioxide film, 40.41 is a polysilicon film, 50.51, 52.53 are molybdenum silicide films,
6 is a smooth coat film, 70 and 71 are mismatched portions, and 8 is a disconnection. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (4)
サイド膜または高融点金属膜の膜厚を０．２μｍ以下に
したことを特徴とする半導体装置。(1) A semiconductor device characterized in that the film thickness of a high melting point metal silicide film or a high melting point metal film for electrode wiring formed in a stepped portion is 0.2 μm or less.
サイド膜、タングステンシリサイド膜、チタンシリサイ
ド膜およびタンタルシリサイド膜からなる群から選ばれ
た１つの膜である特許請求の範囲第１項記載の半導体装
置。(2) The semiconductor device according to claim 1, wherein the high melting point metal silicide film is one film selected from the group consisting of a molybdenum silicide film, a tungsten silicide film, a titanium silicide film, and a tantalum silicide film.
ン膜、チタン膜およびタンタル膜からなる群から選ばれ
た１つの膜である特許請求の範囲第１項記載の半導体装
置。(3) The semiconductor device according to claim 1, wherein the high melting point metal film is one film selected from the group consisting of a molybdenum film, a tungsten film, a titanium film, and a tantalum film.
は、スパッタリング法により形成される特許請求の範囲
第１項ないし第３項のいずれかに記載の半導体装置。(4) The semiconductor device according to any one of claims 1 to 3, wherein the high melting point metal silicide film or the high melting point metal film is formed by a sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19310686A JPS6347950A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19310686A JPS6347950A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6347950A true JPS6347950A (en) | 1988-02-29 |
Family
ID=16302342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19310686A Pending JPS6347950A (en) | 1986-08-18 | 1986-08-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6347950A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0479330A (en) * | 1990-07-23 | 1992-03-12 | Matsushita Electron Corp | Method of forming laminated wiring |
| KR100260524B1 (en) * | 1997-06-27 | 2000-08-01 | 김영환 | Method for forming a metal line in a semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS609160A (en) * | 1983-06-28 | 1985-01-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6057975A (en) * | 1983-09-09 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6184831A (en) * | 1984-10-02 | 1986-04-30 | Nec Corp | Manufacture of semiconductor device |
-
1986
- 1986-08-18 JP JP19310686A patent/JPS6347950A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS609160A (en) * | 1983-06-28 | 1985-01-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6057975A (en) * | 1983-09-09 | 1985-04-03 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS6184831A (en) * | 1984-10-02 | 1986-04-30 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0479330A (en) * | 1990-07-23 | 1992-03-12 | Matsushita Electron Corp | Method of forming laminated wiring |
| KR100260524B1 (en) * | 1997-06-27 | 2000-08-01 | 김영환 | Method for forming a metal line in a semiconductor device |
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