JPH04150034A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04150034A JPH04150034A JP27457190A JP27457190A JPH04150034A JP H04150034 A JPH04150034 A JP H04150034A JP 27457190 A JP27457190 A JP 27457190A JP 27457190 A JP27457190 A JP 27457190A JP H04150034 A JPH04150034 A JP H04150034A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist
- wiring
- forming
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000010410 layer Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims description 3
- 239000003870 refractory metal Substances 0.000 claims description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 23
- 239000010931 gold Substances 0.000 abstract description 23
- 229910052737 gold Inorganic materials 0.000 abstract description 23
- 229910052782 aluminium Inorganic materials 0.000 abstract description 14
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052697 platinum Inorganic materials 0.000 abstract description 13
- 229910052719 titanium Inorganic materials 0.000 abstract description 13
- 239000010936 titanium Substances 0.000 abstract description 13
- 150000004767 nitrides Chemical class 0.000 abstract description 12
- 238000005530 etching Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 238000007747 plating Methods 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910017974 NH40H Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に上層配線と
しての金配線の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gold wiring as an upper layer wiring.
従来、半導体基板上に上層配線として金配線を形成する
に際しては、下層のアルミニウム配線との密着用および
バリヤ用メタルとしての高融点金属をリフトオフプロセ
スで形成した後、フォトリソグラフィー工程を用いた選
択メツキ法により金配線を形成するという方法が用いら
れている。Conventionally, when forming gold wiring as an upper-layer wiring on a semiconductor substrate, a high-melting point metal is formed by a lift-off process for adhesion to the lower-layer aluminum wiring and as a barrier metal, and then selective plating is performed using a photolithography process. A method is used in which gold wiring is formed by a method.
また、金メツキ法とドライエツチング法とを用いて金配
線を形成する方法もある。以下この方法について第３図
を参照して説明する。There is also a method of forming gold wiring using a gold plating method and a dry etching method. This method will be explained below with reference to FIG.
まず、第３図（ａ）に示すように、シリコン基板１上に
形成されたシリコン酸化膜２上に下層配線としてアルミ
ニウム配線３を形成し、次で全面にプラズマＣＶＤ法に
よる窒化膜（以下ＣＶＤ窒化膜という）４を被着し、フ
ォトレジスト５をマスクとしてアルミニウム配線上にス
ルーホール６を形成する。次に第３図（ｂ）に示すよう
に、フ才１−レジスト５を除去後、チタン膜８と白金膜
９を全面に被着する。First, as shown in FIG. 3(a), an aluminum wiring 3 is formed as a lower layer wiring on a silicon oxide film 2 formed on a silicon substrate 1, and then a nitride film (hereinafter referred to as CVD) is formed on the entire surface by plasma CVD method. A nitride film 4 (referred to as nitride film) is deposited, and through holes 6 are formed on the aluminum wiring using a photoresist 5 as a mask. Next, as shown in FIG. 3(b), after removing the resist 5, a titanium film 8 and a platinum film 9 are deposited on the entire surface.
次に第３図（ｃ）に示すように、フォトレジスト１０を
パターニングし、スルーホール６上に開口部を形成し、
金メツキ層１１を形成する。次に、第３図（ｄ）に示す
ように、フオトレジス１〜１０を除去後、金メツキ層１
１をマスクにしてチタン膜８と白金膜９をドライエツチ
ング法によりエツチングし、金配線１１Ａの形成を完了
する。Next, as shown in FIG. 3(c), the photoresist 10 is patterned to form an opening above the through hole 6,
A gold plating layer 11 is formed. Next, as shown in FIG. 3(d), after removing the photoresists 1 to 10, the gold plating layer 1
1 as a mask, the titanium film 8 and the platinum film 9 are etched by dry etching to complete the formation of the gold wiring 11A.
上述したリフトオフプロセスと選択金メツキ法による方
法は、リフトオフ時にひげが発生しショート不良を起す
ため、微細金配線形成は困難である。The method using the lift-off process and selective gold plating method described above is difficult to form fine gold wiring because whiskers occur during lift-off and cause short-circuit defects.
また、金メツキ法とドライエツチング法とを用いた方法
は、アルミニウム配線と金配線の層宵絶縁膜であるＣＶ
Ｄ窒化膜の平坦性が悪いと、第３図（ｄ）に示したよう
に、ＣＶＤ窒化膜４の段差部においてチタン膜と白金膜
の残渣１３が発生するためショート不良を起し、半導体
装置の信頼性及び歩留りを低下させるという欠点がある
。また、層間絶縁膜の平坦化は複雑な工程が必要となり
実用的ではない。In addition, the method using the gold plating method and the dry etching method is a method that uses CV
If the flatness of the D nitride film is poor, as shown in FIG. 3(d), residues 13 of the titanium film and platinum film will be generated at the stepped portion of the CVD nitride film 4, resulting in short-circuit defects and damage to the semiconductor device. The disadvantage is that it reduces reliability and yield. Furthermore, planarization of the interlayer insulating film requires a complicated process and is not practical.
本発明の半導体装置の製造方法は、シリコン基板上に形
成された酸化膜上に下層配線を形成する工程と、前記下
層配線上に層間絶縁膜を形成したのちパターニングし前
記下層配線上に開口部を形成する工程と、開口部が形成
された前記層間絶縁膜上部にフォトレジスト膜を形成し
前記下層配線により形成された前記層間絶縁膜の段差部
を平坦化する工程と、前記下層配線上の前記フォトレジ
スト膜を開口し下層配線の表面を露出する工程と、露出
した前記下層配線の表面を含む全面に上層配線形成用の
高融点金属膜を形成する工程とを含んで構成される。A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a lower layer wiring on an oxide film formed on a silicon substrate, forming an interlayer insulating film on the lower layer wiring, and patterning it to form an opening on the lower layer wiring. forming a photoresist film on the interlayer insulating film in which the opening is formed and flattening the stepped portion of the interlayer insulating film formed by the lower wiring; The method includes a step of opening the photoresist film to expose the surface of the lower layer wiring, and a step of forming a refractory metal film for forming the upper layer wiring on the entire surface including the exposed surface of the lower layer wiring.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至（ｆ＞は本発明の第１の実施例を説明
するための半導体チップの断面図である。FIGS. 1A to 1F are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.
まず、第１図（ａ）に示すように、シリコン基板１上に
形成されたシリコン酸化膜２上に下層配線としてアルミ
ニウム配線３を形成し、次で全面にプラズマＣＶＤ法に
よりＣＶＤ窒化膜４を被着し、パターニングされたフォ
トレジスト５によりアルミニウム配線５上にスルーホー
ル６を開口する。First, as shown in FIG. 1(a), an aluminum wiring 3 is formed as a lower layer wiring on a silicon oxide film 2 formed on a silicon substrate 1, and then a CVD nitride film 4 is formed on the entire surface by plasma CVD. A through hole 6 is opened on the aluminum wiring 5 using the deposited and patterned photoresist 5.
次に第１図（ｂ）に示すように、フ才）〜レジスト５を
除去後、再びフォトレジスト７を形成し、アルミニウム
配線３上のＣＶＤ窒化膜４に形成された段差部を埋めて
平坦化したのちパターニングし、アルミニウム配線上に
スルーホール６より大きな開口部を形成し、約１５０″
Ｃでベークすることによりこの開口部をなだらかにする
。Next, as shown in FIG. 1(b), after removing the photoresist 5, a photoresist 7 is formed again to fill the stepped portion formed in the CVD nitride film 4 on the aluminum wiring 3 and flatten it. After patterning, an opening larger than the through hole 6 is formed on the aluminum wiring, with a diameter of approximately 150".
This opening is made smooth by baking at C.
次に第１図（ｃ）に示すように、露出されたアルミニウ
ム配線３の表面を含む全面に密着用膜としてのチタン膜
８とバリヤ用膜としての白金膜９をスパッタ法によりそ
れぞれ１０００への厚さに被着する。Next, as shown in FIG. 1(c), a titanium film 8 as an adhesion film and a platinum film 9 as a barrier film are coated on the entire surface including the exposed surface of the aluminum wiring 3 to a thickness of 1,000 yen each by sputtering. Deposit thickly.
次に、第１図（ｄ）に示すように、スルーホール６上に
開口部を有するフォトレジスト１０を形成したのち、金
メツキ法によりこの開口部内に金メツキ層１１を形成す
る。Next, as shown in FIG. 1(d), a photoresist 10 having an opening is formed over the through hole 6, and then a gold plating layer 11 is formed in the opening by a gold plating method.
次に第１図（ｅ）に示すように、フォトレジスト］０を
除去後マグネトロン型のりアクティブイオンエツチング
装置によって白金膜９とチタン膜８を、例えばＡｒ＋Ｃ
２ＣＡ２ Ｆ４ガスでエツチングする。この時、下地は
平坦化されているので、エツチング残渣は発生しない。Next, as shown in FIG. 1(e), after removing the photoresist 0, the platinum film 9 and the titanium film 8 are etched using a magnetron type active ion etching device, for example, Ar+C.
Etch with 2CA2 F4 gas. At this time, since the underlying layer is flattened, no etching residue is generated.
次に第１図（ｆ）に示すように、フォトレジスト７を除
去し、金配線１１Ａの形成を完了する。Next, as shown in FIG. 1(f), the photoresist 7 is removed to complete the formation of the gold wiring 11A.
このように第１の実施例によれば、ＣＶＤ窒化膜４の段
差部はフォトレジストアにより平坦化されているため、
白金膜及びチタン膜の残渣が発生することはなく、微細
な金配線を形成することができる。例えば、従来のリフ
トオフ法における限界配線ピッチが１５μｍであるのに
対し、本実施例の限界配線ピッチは５μｍである。As described above, according to the first embodiment, since the stepped portion of the CVD nitride film 4 is flattened by photoresist,
Residues of platinum and titanium films are not generated, and fine gold wiring can be formed. For example, while the limit wiring pitch in the conventional lift-off method is 15 μm, the limit wiring pitch in this embodiment is 5 μm.
第２図（ａ）乃至（ｈ）は本発明の第２の実施例を説明
するための半導体チップの断面図である。FIGS. 2(a) to 2(h) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.
まず第２図（ａ）に示すように、第１の実施例と同様に
してＣＶＤ窒化膜４にスルーホール６を形成し、フォト
レジスト５を除去後第２図（ｂ）に示すように、逆スパ
ツタでアルミニウム配線３の表面を清浄としたのち、ス
パッタ法でチタン膜１２を３０００Ａの厚さに被着する
。First, as shown in FIG. 2(a), a through hole 6 is formed in the CVD nitride film 4 in the same manner as in the first embodiment, and after removing the photoresist 5, as shown in FIG. 2(b), After cleaning the surface of the aluminum wiring 3 by reverse sputtering, a titanium film 12 is deposited to a thickness of 3000 Å by sputtering.
次に第２図（ｃ）に示すように、再びフォトレジスト７
を形成しＣＶＤ窒化膜４により形成された段差部を平坦
化したのち、スルーホール６上に開口部を形成し、１５
０″Ｃでベータしてこの開口部をなだらかにする。Next, as shown in FIG. 2(c), the photoresist 7 is applied again.
After forming and flattening the stepped portion formed by the CVD nitride film 4, an opening is formed above the through hole 6, and a step 15 is formed.
Beta at 0″C to smooth this opening.
次に、第２図（ｄ）に示すように、密着用膜としてのチ
タン膜８とバリヤ用膜としての白金膜９をそれぞれ１０
００への厚さ被着する。Next, as shown in FIG. 2(d), 100% of each of the titanium film 8 as an adhesion film and the platinum film 9 as a barrier film was applied.
Deposit thickness to 00.
次に第２図（ｅ）に示すように、スルーホール６−トに
開口部を有するフォトレジスト１０を形成したのち、こ
の開口部内に金メツキ層１１を形成する。Next, as shown in FIG. 2(e), a photoresist 10 having an opening in the through hole 6-t is formed, and then a gold plating layer 11 is formed in this opening.
次に、第２図（ｆ）に示すように、フォトレジスト１０
を除去後、マグネトロン型のりアクティブイオンエツチ
ング装置によって白金膜９を、例えばＡｒ＋Ｃ２Ｃ，Ｒ
２Ｆ４ガスでエツチングする。この時、下地は平坦化さ
れているので、エツチング残渣は生じない。Next, as shown in FIG. 2(f), a photoresist 10
After removing the platinum film 9, the platinum film 9 is etched using a magnetron type active ion etching device, for example, Ar+C2C,R
Etch with 2F4 gas. At this time, since the underlying layer is flattened, no etching residue is generated.
次に第２図（ｇ）に示すように、フォトレジスト７を除
去する。次いて、第２図（ｈ）に示すように、ウェット
エツチング法（Ｈ２０２＋ＮＨ４０Ｈ）によってチタン
膜１２をエツチングし、金配線１１Ａの形成を完了する
。Next, as shown in FIG. 2(g), the photoresist 7 is removed. Next, as shown in FIG. 2(h), the titanium film 12 is etched by a wet etching method (H202+NH40H) to complete the formation of the gold wiring 11A.
本第２の実施例では、逆スパツタ法でアルミニウム配線
表面を清浄にしているため、第１の実施例に比ベアルミ
ニウム配線３と金配線１１Ａとをより導電性よく接続で
きる利点がある。In the second embodiment, since the surface of the aluminum wiring is cleaned by the reverse sputtering method, there is an advantage over the first embodiment that the aluminum wiring 3 and the gold wiring 11A can be connected with better conductivity.
以上説明した様に本発明は、下層配線上部の層間絶縁膜
の段差部をフォトレジストにより埋めて平坦化を行なう
ことにより、段差部に上層配線形成用の高融点金属のエ
ツチング残渣か発生することがなくなるため、微細な金
配線を形成できると共に、半導体装置の信頼性及び歩留
りを向上させることができるという効果がある。As explained above, in the present invention, by filling the stepped portion of the interlayer insulating film above the lower layer wiring with a photoresist and flattening it, etching residue of the refractory metal for forming the upper layer wiring is generated in the stepped portion. This eliminates the possibility of forming fine gold interconnections, and has the effect that the reliability and yield of semiconductor devices can be improved.
第１図（ａ）乃至（ｆ）は本発明の第１の実施例を、第
２図（ａ）乃至（ｈ）は第２の実施例を、第３図（ａ）
乃至（ｄ）は従来例をそれぞれ説明するための半導体チ
ップの断面図である。
１・・・シリコン基板、２・・・シリコン酸化膜、３・
・アルミニウム配線、４・・・ＣＶＤ窒化膜、５，７１
０・・・フォトレジスト、６・・・スルーホール、８１
２・・・チタン膜、９・・・白金膜、１１・・・金メツ
キ層、ＩＩＡ・金配線、１３・・・チタン膜と白金膜の
残渣。FIGS. 1(a) to (f) show the first embodiment of the present invention, FIGS. 2(a) to (h) show the second embodiment, and FIG. 3(a) shows the second embodiment.
1 to 3(d) are cross-sectional views of semiconductor chips for explaining conventional examples, respectively. 1... Silicon substrate, 2... Silicon oxide film, 3.
・Aluminum wiring, 4...CVD nitride film, 5, 71
0... Photoresist, 6... Through hole, 81
2...Titanium film, 9...Platinum film, 11...Gold plating layer, IIA/gold wiring, 13...Residues of titanium film and platinum film.
Claims (1)
成する工程と、前記下層配線上に層間絶縁膜を形成した
のちパターニングし前記下層配線上に開口部を形成する
工程と、開口部が形成された前記層間絶縁膜上部にフォ
トレジスト膜を形成し前記下層配線により形成された前
記層間絶縁膜の段差部を平坦化する工程と、前記下層配
線上の前記フォトレジスト膜を開口し下層配線の表面を
露出する工程と、露出した前記下層配線の表面を含む全
面に上層配線形成用の高融点金属膜を形成する工程とを
含むことを特徴とする半導体装置の製造方法。a step of forming a lower layer wiring on an oxide film formed on a silicon substrate; a step of forming an interlayer insulating film on the lower layer wiring and then patterning it to form an opening on the lower layer wiring; and a step of forming an opening on the lower layer wiring. forming a photoresist film on top of the interlayer insulating film and flattening the stepped portion of the interlayer insulating film formed by the lower wiring; opening the photoresist film on the lower wiring; A method for manufacturing a semiconductor device, comprising: exposing a surface; and forming a refractory metal film for forming an upper layer wiring over the entire surface including the exposed surface of the lower layer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27457190A JP3033171B2 (en) | 1990-10-12 | 1990-10-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27457190A JP3033171B2 (en) | 1990-10-12 | 1990-10-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04150034A true JPH04150034A (en) | 1992-05-22 |
| JP3033171B2 JP3033171B2 (en) | 2000-04-17 |
Family
ID=17543597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27457190A Expired - Lifetime JP3033171B2 (en) | 1990-10-12 | 1990-10-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033171B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659201A (en) * | 1995-06-05 | 1997-08-19 | Advanced Micro Devices, Inc. | High conductivity interconnection line |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101693107B1 (en) | 2015-04-20 | 2017-01-17 | 이도영 | Moving apparatus of patient Exercise machine |
-
1990
- 1990-10-12 JP JP27457190A patent/JP3033171B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5659201A (en) * | 1995-06-05 | 1997-08-19 | Advanced Micro Devices, Inc. | High conductivity interconnection line |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3033171B2 (en) | 2000-04-17 |
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