JPH04102331A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04102331A JPH04102331A JP22029490A JP22029490A JPH04102331A JP H04102331 A JPH04102331 A JP H04102331A JP 22029490 A JP22029490 A JP 22029490A JP 22029490 A JP22029490 A JP 22029490A JP H04102331 A JPH04102331 A JP H04102331A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- hole
- insulating film
- wiring
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010410 layer Substances 0.000 claims abstract description 80
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 238000000992 sputter etching Methods 0.000 claims abstract description 21
- 239000011247 coating layer Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 31
- 239000011261 inert gas Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 30
- 239000000758 substrate Substances 0.000 abstract description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 14
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052731 fluorine Inorganic materials 0.000 abstract description 3
- 239000011737 fluorine Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 210000003029 clitoris Anatomy 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 208000020442 loss of weight Diseases 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置の製造方法、特に層間接続用のテーパ状スル
ーホールを具備した多層配線の形成方法の改良に関し、
不活性ガスのプラズマによるスパッタエツチングによっ
て層間接続用のスルーホールをテーパ状に加工する工程
を有する多層配線の形成方法において、スルーホール内
のコンタクト界面に堆積物が存在せず、スルーホールが
微細化された際にもコンタクト抵抗の低い良好な層間コ
ンタクトが得られる方法を提供することを目的とし、層
間接続部を有する多層配線を形成するに際して、下層絶
縁膜上に、絶縁膜及び配線金属に対してエツチングの選
択性が得られる被覆層を上面に有する下層配線を形成す
る工程と、該下層配線形成面を覆う眉間絶縁膜を形成す
る工程と、次いで、異方性ドライエツチング手段を用い
、該層間絶縁膜に、該下層配線上の被覆層をエツチング
停止層として、該被覆層の上面に達するスルーホールを
形成する工程と、次いて該層間絶縁膜の表面を不活性ガ
スのプラズマを用いてスパッタエツチングし、該スルー
ホールの側壁面を斜面状に形成する工程と、次いで該ス
ルーホール底部に表出する該被覆層を選択的にエツチン
グ除去して該スルーホールの底部に下層配線を直に表出
せしめる工程を含み構成される。[Detailed Description of the Invention] [Summary] Regarding an improvement in a method for manufacturing a semiconductor device, particularly in a method for forming multilayer interconnections having tapered through holes for interlayer connections, the method for forming interlayer connections by sputter etching using inert gas plasma. In a method for forming multilayer interconnection that includes the process of processing through holes into a tapered shape, there is no deposit at the contact interface in the through holes, and even when the through holes are miniaturized, there is a good interlayer interconnection with low contact resistance. In order to provide a method for obtaining contacts, when forming a multilayer interconnection having an interlayer connection part, a coating layer that provides etching selectivity with respect to the insulating film and wiring metal is placed on the lower insulating film on the upper surface. a step of forming a lower layer wiring on the lower layer wiring, a step of forming a glabellar insulating film covering the surface on which the lower layer wiring is formed, and then a coating layer on the lower layer wiring is formed on the interlayer insulating film using an anisotropic dry etching means. forming a through hole reaching the upper surface of the coating layer using the etching stop layer as an etching stop layer, and then sputter etching the surface of the interlayer insulating film using inert gas plasma to make the side wall surface of the through hole sloped. The method includes the step of forming a shape, and then selectively etching away the covering layer exposed at the bottom of the through hole to directly expose the lower layer wiring at the bottom of the through hole.
本発明は半導体装置の製造方法、特に層間接続用のテー
パ状スルーホールを具備した多層配線の形成方法の改良
に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming a multilayer wiring having tapered through holes for interlayer connections.
近年の半導体装置の高密度・高集積化に伴って、半導体
装置内部の各種パターンの微細化が進行しており、それ
に伴って多層配線構造における層間接続用のスルーホー
ルのコンタクト面積も、同様に微細化せざるを得なくな
ってきている。As semiconductor devices have become more dense and highly integrated in recent years, various patterns inside semiconductor devices have become smaller and smaller, and as a result, the contact area of through holes for interlayer connections in multilayer wiring structures has also become smaller. We have no choice but to miniaturize.
そのため、スルーホール上に形成される上層配線層のカ
バレッジ性を高めて配線金属のマイグレーション等に起
因する上層配線の断線を防止するためには、スルーホー
ルの上部開口部を斜面状に広げてアスペクト比を減少せ
しめたテーパ状のスルーホールを用いることが有効であ
る。Therefore, in order to improve the coverage of the upper wiring layer formed on the through hole and prevent disconnection of the upper wiring layer due to wiring metal migration, etc., the upper opening of the through hole is widened into a slope shape to increase the aspect ratio. It is effective to use a tapered through hole with a reduced ratio.
そこで、テーパ状スルーホールの形成手段として、基板
面にほぼ垂直な側壁面を有するスルーホール形成後、こ
のスルーホールの開口部を、不活性ガスのプラズマによ
るスパッタ性のエツチングにより面取りする方法か提案
されているが、この方法には、コンタクト面への再堆積
物の付着によるコンタクト特性劣化の問題かあり、改善
か望まれている。Therefore, we proposed a method of forming a tapered through hole by forming a through hole with a side wall surface almost perpendicular to the substrate surface and then chamfering the opening of the through hole by sputtering etching using inert gas plasma. However, this method has the problem of deterioration of contact characteristics due to redeposited matter adhering to the contact surface, and an improvement is desired.
テーパ状スルーホールは、従来、第２図（ａ）に示すよ
うに、先ず下層配線５３形成面上を覆う層間絶縁膜５４
に、図示しないレジスト膜をマスクにし反応性イオンエ
ツチングにより、基板面に対してほぼ垂直な側壁面を有
するスルーホール５５を形成する。（５１は半導体基板
、５２は下層絶縁膜）次いで、第２図（ｂ）に示すよう
に、不活性ガス例えばアルゴン（Ａｒ）のプラズマ中に
おいて、励起されたＡｒ粒子（Ａｒ“）によって層間絶
縁膜５４の表面をスパッタエツチングする。Conventionally, as shown in FIG. 2(a), a tapered through hole is formed by first forming an interlayer insulating film 54 covering a surface on which lower layer wiring 53 is formed.
Next, a through hole 55 having a side wall surface substantially perpendicular to the substrate surface is formed by reactive ion etching using a resist film (not shown) as a mask. (51 is a semiconductor substrate, 52 is a lower insulating film) Next, as shown in FIG. 2(b), in an inert gas, for example, argon (Ar) plasma, excited Ar particles (Ar") are used to insulate the interlayer. The surface of the film 54 is sputter etched.
このスパッタエツチングのエツチングレートは、基板面
に対し４５度方向のエツチング角度において最も大きな
値になり、９０度方向及び基板面に沿う方向では殆ど０
になる。The etching rate of this sputter etching has the largest value at an etching angle of 45 degrees with respect to the substrate surface, and is almost 0 in the direction of 90 degrees and along the substrate surface.
become.
そのため上記スパッタエツチングによって、第２図（Ｃ
）に示すように、スルーホール５５の開口部の角か４５
度の角度を持って優先的に削られ、この開口部にほぼ４
５度のテーパ部５６か形成される。そしてまた、上記ス
パッタエツチングにより削り取られた絶縁膜はスルーホ
ール５５の側壁の上記テーパ部５６の下部に斜面状に再
堆積するので（１５３は再堆積絶縁膜）、スルーホール
５５の側壁面が底部から開口部に向かって順次波かった
テーパ状スルーホール５５Ｔか形成される。Therefore, by the above sputter etching, as shown in Fig. 2 (C
), the corner of the opening of the through hole 55 or 45
This opening is preferentially cut at an angle of approximately 4 degrees.
A tapered portion 56 of 5 degrees is formed. Furthermore, the insulating film scraped off by the sputter etching is re-deposited on the lower part of the tapered part 56 on the side wall of the through-hole 55 in a slope shape (153 is a re-deposited insulating film), so that the side wall surface of the through-hole 55 is at the bottom. A tapered through-hole 55T is formed which is wavy in order from the opening toward the opening.
そして、従来のテーパ状スルーホール５５Ｔの形成工程
はここで終了しており、多層配線形成工程においては、
第２図（ｄ）に示すように、上記テーパ状スルーホール
５５Ｔ上に、直接上層配線５７が形成されていた。The conventional step of forming the tapered through hole 55T is completed here, and in the multilayer wiring forming step,
As shown in FIG. 2(d), an upper layer wiring 57 was formed directly on the tapered through hole 55T.
しかし上記従来の方法によると、第２図（Ｃ）に示され
るように、スパッタエツチングの際の再堆積絶縁膜１５
４の一部かスルーホール５５Ｔの底部に表出する下層配
線５３の表面にも部分的に薄く堆積するもの（１５４Ｐ
）があり、これが第２（ｄ）に示すように、このスルー
ホール５５Ｔ上に直ちに形成される上層配線５７と下層
配線５３との間に介在してそのコンタクト抵抗を増大さ
せ、配線の層間コンタクト不良の原因となることがあっ
た。However, according to the above conventional method, as shown in FIG. 2(C), the redeposited insulating film 15 during sputter etching
4 or on the surface of the lower layer wiring 53 exposed at the bottom of the through hole 55T (154P).
), which is interposed between the upper layer wiring 57 and the lower layer wiring 53 that are immediately formed on the through hole 55T, increasing the contact resistance, and causing an interlayer contact between the wirings, as shown in 2(d). This may cause defects.
そのため従来の方法では、良好な上層配線のカバレッジ
は得られても、上記コンタクト抵抗の増大を考慮してス
ルーホールの大きさの縮小が制限されるという問題があ
った。Therefore, in the conventional method, even if good coverage of the upper layer wiring can be obtained, there is a problem in that reduction in the size of the through hole is limited in consideration of the increase in contact resistance.
そこで本発明は、不活性ガスのプラズマによるスパッタ
エツチングによって層間接続用のスルーホールをテーパ
状に加工する工程を有する多層配線の形成方法において
、スルーホール内のコンタクト界面に堆積物が存在せず
、スルーホールが微細化された際にもコンタクト抵抗の
低い良好な層間コンタクトか得られる方法を提供するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention provides a method for forming a multilayer interconnection, which includes a step of forming a through hole for interlayer connection into a tapered shape by sputter etching using an inert gas plasma, in which no deposits are present at the contact interface within the through hole. It is an object of the present invention to provide a method by which good interlayer contact with low contact resistance can be obtained even when through holes are miniaturized.
上記課題は、層間接続部を有する多層配線を形成するに
際して、下層絶縁膜上に、絶縁膜及び配線金属に対して
エツチングの選択性か得られる被覆層を上面に有する下
層配線を形成する工程と、該下層配線形成面を覆う層間
絶縁膜を形成する工程と、次いで、異方性ドライエツチ
ング手段を用い、該層間絶縁膜に、該下層配線上の被覆
層をエツチング停止層として、該被覆層の上面に達する
スルーホールを形成する工程と、次いで、該層間絶縁膜
の表面を不活性ガスのプラズマを用いてスパッタエツチ
ングし、該スルーホールの側壁面を斜面状に形成する工
程と、次いで、該スルーホール底部に表出する該被覆層
を選択的にエツチング除去して該スルーホールの底部に
下層配線を直に表出せしめる工程を含む本発明による半
導体装置の製造方法によって解決される。The above problem is solved by the process of forming a lower layer wiring on the lower layer insulating film, which has a covering layer on the upper surface that provides etching selectivity with respect to the insulating film and the wiring metal, when forming a multilayer wiring having interlayer connections. , a step of forming an interlayer insulating film covering the lower wiring forming surface, and then etching the covering layer on the interlayer insulating film using an anisotropic dry etching means, using the covering layer on the lower wiring as an etching stop layer. a step of forming a through hole reaching the upper surface; a step of sputter etching the surface of the interlayer insulating film using inert gas plasma to form a side wall surface of the through hole in an inclined shape; This problem is solved by the method of manufacturing a semiconductor device according to the present invention, which includes a step of selectively etching away the covering layer exposed at the bottom of the through hole to directly expose the lower wiring at the bottom of the through hole.
即ち本発明においては、下層配線を上面に被覆層か積層
された構造にしておき、この被覆層を有する下層配線上
に層間絶縁膜を形成し、この層間絶縁膜に上記被覆層を
エツチング停止層とし、この被覆層面を表出する側壁面
のほぼ垂直なスルーホールを形成し、次いて不活性ガス
プラズマを用いるスパッタエツチングにより上記スルー
ホールの側壁をテーパ状に加工し、その後にスルーホー
ル底部に表出する被覆層を選択的にエツチング除去して
、底部に下層配線のコンタクト面を直に表出するテーパ
状スルーホールを形成する。That is, in the present invention, the lower wiring has a structure in which a covering layer is laminated on the upper surface, an interlayer insulating film is formed on the lower wiring having the covering layer, and the covering layer is applied to the interlayer insulating film as an etching stop layer. Then, a through hole with a nearly vertical side wall surface exposing the surface of this coating layer is formed, and then the side wall of the through hole is processed into a tapered shape by sputter etching using inert gas plasma. The exposed covering layer is selectively etched away to form a tapered through hole at the bottom directly exposing the contact surface of the underlying wiring.
このようにすると、スパッタエツチングに際してスルー
ホール底部下層配線のコンタクト面上に被着する一部の
再堆積絶縁膜は、下層配線上の被覆層上に被着しようと
することになり、この堆積絶縁膜は、上記スパッタエツ
チングによるスルーホールのテーパ加工終了後に選択的
にエツチング除去される被覆層と共にリフトオフされる
ので、テーパ状スルーホールの底部には清浄な下層配線
のコンタクト面が直に表出せしめられる。In this way, during sputter etching, part of the re-deposited insulating film deposited on the contact surface of the lower layer interconnect at the bottom of the through hole will tend to adhere to the covering layer on the lower layer interconnect, and this deposited insulating film will be removed. The film is lifted off together with the covering layer, which is selectively etched away after the taper processing of the through hole by sputter etching is completed, so that the contact surface of the clean underlying wiring is directly exposed at the bottom of the tapered through hole. It will be done.
従って、スルーホールか微細であっても良好なコンタク
ト特性を得ることが可能になる。Therefore, it is possible to obtain good contact characteristics even if the through hole is minute.
以下本発明の方法を、第１図（ａ）〜（ｇに示す工程断
面図を参照し、一実施例により具体的に説明する。The method of the present invention will be specifically explained below by way of an example with reference to process cross-sectional views shown in FIGS. 1(a) to 1(g).
第１図（ａ）参照
本発明の方法によりテーパ状スルーホールを有する多層
配線構造を形成するに際しては、通常通り、図示しない
半導体素子の形成された半導体基板１上の、図示しない
領域に半導体素子面に達するコンタクトホールか形成さ
れた下層絶縁膜２上に、先ず下層配線の材料である例え
ば厚さ７０００人程度０周知のＡｌ−３ｉ−Ｃｕ合金層
１０３を、通常通リスバッタ法等により形成し、次いで
このＡｌ−３ｉ−Ｃｕ合金層１０３上に、同じくスパッ
タ法等により、導電性の被覆層として厚さ７００人程０
の窒化チタン（ＴｉＮ ）被覆層４を被着する。Refer to FIG. 1(a) When forming a multilayer wiring structure having tapered through holes by the method of the present invention, as usual, semiconductor elements are placed in regions (not shown) on a semiconductor substrate 1 on which semiconductor elements (not shown) are formed. First, a well-known Al-3i-Cu alloy layer 103 with a thickness of about 7,000, which is a material for the lower wiring, is formed on the lower insulating film 2 in which a contact hole reaching the surface is formed, by the usual Lisbatter method or the like. Then, on this Al-3i-Cu alloy layer 103, a conductive coating layer with a thickness of about 700 mm is formed by sputtering or the like.
A titanium nitride (TiN 2 ) coating layer 4 is applied.
なお上記ＴｉＮは、配線材料である前記Ａｌ−３ｉ−Ｃ
ｕ合金及び後に形成される層間絶縁膜との間に充分なエ
ツチングの選択性が得られるように選ばれた材料である
。Note that the above-mentioned TiN is the same as the above-mentioned Al-3i-C which is a wiring material.
This material was selected to provide sufficient etching selectivity between the u alloy and the interlayer insulating film that will be formed later.
第１図（ｂ）参照
次いで、エツチング手段に塩素（Ｃ１）系のガスによる
反応性イオンエツチング（ＲＩＢ）を用いるフォトリソ
グラフィにより上記ＴｉＮ被覆層４及びＡｌ−５ｉ−Ｃ
ｕ合金層１０３を一部パターニングし、前記下層絶縁膜
２上に、前記Ａｌ−３ｉ−Ｃｕ合金層１０３からなり、
図示しない領域のコンタクトホールを介し半導体素子面
に接続され、且つ上面に前記ＴｉＮ被覆層４が積層され
てなる下層ＡＩ配線３を形成する。Referring to FIG. 1(b), the TiN coating layer 4 and the Al-5i-C are etched by photolithography using reactive ion etching (RIB) using a chlorine (C1) gas as an etching means.
Part of the u alloy layer 103 is patterned, and the Al-3i-Cu alloy layer 103 is formed on the lower insulating film 2,
A lower AI wiring 3 is formed which is connected to the semiconductor element surface through a contact hole in an area not shown and has the TiN covering layer 4 laminated on the upper surface.
第１図（Ｃ）参照
次いで、上記ＴｉＮ被覆層４を上面に有する上記下層Ａ
Ｉ配線３が形成されてなる被加工基板上に、通常通り周
知の平坦化技術を含む化学気相成長工程を経て、例えば
厚さ９０００人程度０ＳｉＯ□膜からなる表面が平滑化
された層間絶縁膜５を形成する。Refer to FIG. 1(C) Next, the lower layer A having the TiN coating layer 4 on the upper surface.
On the substrate to be processed on which the I wiring 3 is formed, an interlayer insulating material with a smooth surface made of, for example, a 0SiO□ film with a thickness of about 9,000 yen is formed through a chemical vapor deposition process including a well-known planarization technique as usual. A film 5 is formed.
第１図（ｄ）参照
次いで、従来通り通常のフォトプロセスにより層間絶縁
膜５上に形成した図示しないレジストマスクの開孔を介
し、エツチングガスに上記層間絶縁膜５とＴｉＮ被覆層
４との間でエツチングの選択性が得られる弗素系のガス
である例えば３弗化メタン（ＣＨＦ、）を用いるＲＩＢ
処理を行い、層間絶縁膜５に、下層ＡＩ配線３上のＴｉ
Ｎ被覆層４の上面を底部に表出し、且つほぼ垂直な側壁
面を有する径０．８μｍ程度のスルーホール６を形成す
る。Referring to FIG. 1(d), etching gas is applied between the interlayer insulating film 5 and the TiN coating layer 4 through an opening in a resist mask (not shown) formed on the interlayer insulating film 5 by a conventional photo process. RIB using a fluorine-based gas such as trifluoromethane (CHF) that provides etching selectivity in
After processing, the interlayer insulating film 5 is coated with Ti on the lower layer AI wiring 3.
A through hole 6 having a diameter of about 0.8 μm is formed, exposing the upper surface of the N coating layer 4 to the bottom and having a substantially vertical side wall surface.
第１図（ｅ）参照
次いで、上記被加工基板の層間絶縁膜５の表面を、通常
のりアクティブイオンエツチング装置等の平板電極型プ
ラズマエツチング装置内において、不活性ガス例えばＡ
ｒガスの、プラズマにより励起された荷電粒子（Ａｒ”
）によりスパッタエツチングする。このスパッタエツ
チングの条件は、例えば次の如くである。Referring to FIG. 1(e), the surface of the interlayer insulating film 5 of the substrate to be processed is etched with an inert gas such as A
Charged particles (Ar”) of r gas excited by the plasma
) sputter etching. The conditions for this sputter etching are, for example, as follows.
Ａｒ 流量： １００ ｃｃ／ｍｉｎ
圧力 ・０．Ｉ Ｔｏｒｒ
ＲＦパワー（１３，５６ＭＨｚ） ： ７００
Ｗ（〜４Ｗ／ｃＨ１２）
このスパッタエツチングにおけるエツチングレートは、
エツチング角度か基板面に対し４５度の方向で５００人
／ ｍｉｎ程度の最大の値を示し、基板面に対し直角（
９０度）方向及び平行方向ではエツチングレートか殆ど
０に近づく。Ar flow rate: 100 cc/min
Pressure ・0. I Torr RF power (13,56MHz): 700
W (~4W/cH12) The etching rate in this sputter etching is
The maximum value of about 500 people/min is shown at an etching angle of 45 degrees to the substrate surface, and the etching rate is at right angles to the substrate surface (
In the 90 degree) direction and in the parallel direction, the etching rate approaches almost zero.
そのため、上記スパッタエツチング工程においては、層
間絶縁膜５の上面と、前記スルーホール６の底面に表出
する下層ＡＩ配線３上の被覆層４は殆ど削られず、主と
してスルーホール６の開口部の角部か４５度の方向に削
られて、スルーホール６の開口部にほぼ４５度のテーパ
状側壁面７か形成される。Therefore, in the sputter etching process, the upper surface of the interlayer insulating film 5 and the covering layer 4 on the lower AI wiring 3 exposed on the bottom surface of the through hole 6 are hardly etched away, and the corners of the opening of the through hole 6 are mainly etched. The portion is cut in a direction of 45 degrees, and a tapered side wall surface 7 of approximately 45 degrees is formed at the opening of the through hole 6.
また、このスパッタエツチングによって削り取られた層
間絶縁膜５はスルーホール６の前記テーパ状側壁面７の
下部の側壁面に再堆積絶縁膜１０５となって斜面状に再
堆積する。そして、前記テーパ状側壁面７を有する開口
部と上記斜面状に側壁面に堆積する再堆積絶縁膜１０５
とによって、このスルーホール６はテーパ状スルーホー
ル６Ｔとなる。Further, the interlayer insulating film 5 scraped off by this sputter etching is re-deposited on the lower side wall surface of the tapered side wall surface 7 of the through hole 6 as a re-deposited insulating film 105 in the form of a slope. Then, the redeposited insulating film 105 is deposited on the opening having the tapered side wall surface 7 and the side wall surface in the slope shape.
As a result, this through hole 6 becomes a tapered through hole 6T.
そして更に、再堆積絶縁膜１０５の一部は、薄い層とな
ってスルーホール６底部のＴｉＮ被覆層４上にも部分的
に再堆積絶縁膜１０５Ｐとして被着する。Further, a part of the redeposited insulating film 105 becomes a thin layer and is partially deposited on the TiN coating layer 4 at the bottom of the through hole 6 as a redeposited insulating film 105P.
なお、前述のようにこのスパッタエツチングにおいて、
基板面に直角方向のエツチングレートは殆と０であるの
で、層間絶縁膜４の厚さの目減りは殆となく、また下層
Ａｌ配線３のコンタクト面上に存在する前記ＴｉＮ被覆
層４の厚さも前記数百人程度の厚さでエツチング完了ま
て充分に耐え残留する。In addition, as mentioned above, in this sputter etching,
Since the etching rate in the direction perpendicular to the substrate surface is almost 0, there is almost no reduction in the thickness of the interlayer insulating film 4, and the thickness of the TiN coating layer 4 existing on the contact surface of the lower layer Al wiring 3 is also reduced. A thickness of about several hundred layers is enough to withstand etching and leave a residue.
第１図げ）参照
次いで上記基板面を下層Ａｔ配線３との間でエツチング
の選択性の得られる弗素系のガス例えば６弗化硫黄（Ｓ
Ｆ、）をエツチングガスに用いるＲＩＥ処理により全面
エツチングし、テーパ状スルーホール６Ｔの底部に表出
するＴｉＮ被覆層４をエツチング除去し、同時にこのＴ
ｉＮ被覆層４上に被着していた再堆積絶縁膜１０５Ｐを
リフトオフする。これによりテーパ状スルーホール６Ｔ
の底面には、下層ＡＩ配線３の再堆積物のない清浄なコ
ンタクト面（ＡＩ−３ｉ−Ｃｕ合金層面）か表出する。Next, the substrate surface is etched with a fluorine-based gas such as sulfur hexafluoride (S
F,) is etched over the entire surface by RIE processing using an etching gas, and the TiN coating layer 4 exposed at the bottom of the tapered through hole 6T is etched away, and at the same time, this T
The redeposited insulating film 105P deposited on the iN coating layer 4 is lifted off. This makes the tapered through hole 6T
A clean contact surface (AI-3i-Cu alloy layer surface) free from redeposited material of the lower AI wiring 3 is exposed on the bottom surface.
なおこの全面エツチングで層間絶縁膜５は多少目減りす
るが、層間絶縁膜５の厚さがＴｉＮ被覆層４の厚さに比
べて充分に厚いので、ＴｉＮ被覆層４のエツチングが完
了した時点で、層間ショート等の弊害を生ずるような大
きな目減りを生ずることはない。Although the interlayer insulating film 5 is slightly reduced by this etching of the entire surface, since the thickness of the interlayer insulating film 5 is sufficiently thicker than that of the TiN covering layer 4, when the etching of the TiN covering layer 4 is completed, There will be no significant loss of weight that would cause problems such as interlayer short circuits.
以上で、本発明に係るテーパ状スルーホール６Ｔの形成
は完了する。This completes the formation of the tapered through hole 6T according to the present invention.
第１図（ｇ）参照
次いて本発明に係る多層配線形成工程においては、上記
テーパ状スルーホール６Ｔを有する眉間絶縁膜５上に通
常速リスバッタ法等により、厚さ７０００人程度０例え
ば下層配線の材料と同じ配線材料であるＡｌ−３ｉ−Ｃ
ｕ合金層を形成し、次いでこのＡｌ−３ｉ−Ｃｕ合金層
を通常のフォトリソグラフィによりパターニングして、
テーパ状スルーホール６Ｔ上に上記Ａｌ−３ｉ−Ｃｕ合
金からなる上層ＡＩ配線８を形成する。Refer to FIG. 1(g) Next, in the multilayer wiring forming process according to the present invention, the glabellar insulating film 5 having the tapered through hole 6T is coated with a thickness of about 7,000 layers, for example, the lower layer wiring by a normal high-speed rebatter method or the like. Al-3i-C, which is the same wiring material as the material of
Forming a u alloy layer, then patterning this Al-3i-Cu alloy layer by normal photolithography,
Upper layer AI wiring 8 made of the Al-3i-Cu alloy is formed on tapered through hole 6T.
上記実施例に示したように本発明の方法においては、不
活性ガスのプラズマによるスパッタエツチングによって
スルーホールをテーパ状に加工する工程を含む多層配線
の形成方法において、下層配線を配線材料層上に薄い被
覆膜を積層してなる積層構造に形成しておき、眉間絶縁
膜に形成した底部に上記被覆層を表出する垂直側壁面を
有するスルーホールを、前記スパッタエツチングにより
テーパ状側壁形状に加工する際に、スルーホール底部の
下層配線のコンタクト面上に被着する再堆積絶縁膜を上
記被覆層上に被着せしめ、このスルーホール底部に表出
する被覆層を選択的にエツチング除去する際、この被覆
層上に被着している再堆積絶縁膜を被覆層と共にリフト
オフする。As shown in the above embodiments, in the method of the present invention, in the method of forming a multilayer wiring including the step of processing through holes into a tapered shape by sputter etching using inert gas plasma, the lower wiring is formed on the wiring material layer. A layered structure is formed by laminating thin coating films, and a through hole having a vertical sidewall surface exposing the coating layer is formed at the bottom of the glabella insulating film into a tapered sidewall shape by the sputter etching. During processing, a re-deposited insulating film that is deposited on the contact surface of the lower wiring at the bottom of the through hole is deposited on the covering layer, and the covering layer exposed at the bottom of the through hole is selectively etched away. At this time, the redeposited insulating film deposited on the covering layer is lifted off together with the covering layer.
これによって、テーパ状スルーホールの底部に表出する
下層配線のコンタクト面には、再堆積物の付着しない清
浄な配線金属面が表出するので、このコンタクト面を介
して接続される下層配線と上層配線とのコンタクト抵抗
は充分に低い値となる。As a result, the contact surface of the lower layer wiring exposed at the bottom of the tapered through-hole exposes a clean wiring metal surface free from redeposited matter, so that the lower layer wiring connected through this contact surface The contact resistance with the upper layer wiring becomes a sufficiently low value.
そのため、スルーホール径がりソグラフィの限界まで微
細化された際にも良好な配線の層間コンタクトが得られ
る。Therefore, even when the through-hole diameter is miniaturized to the limit of lithography, good interlayer contact of wiring can be obtained.
なお、上記実施例においては、被覆層に導電性を有する
ＴｉＮ層を用いたが、この被覆層は導電性物質に限られ
るものではなく、例えば窒化シリコン（Ｓ１３Ｎ４）等
、層間絶縁膜及び下層配線材料とエツチングの選択性か
得られる物質ならば絶縁膜を用いてもよい。In the above embodiment, a TiN layer having conductivity was used as the covering layer, but this covering layer is not limited to a conductive material, and may include, for example, silicon nitride (S13N4), an interlayer insulating film, and lower wiring. An insulating film may be used as long as the material and etching selectivity can be obtained.
以上説明したように本発明によれば、層間絶縁膜のスル
ーホールがテーパ状側壁を有して形成されるので、スル
ーホールの底部開口径をフォトリソグラフィの限界程度
に微細化した際にも上層配線層のカバレッジ性か良くそ
の断線か防止され、且つスルーホールのテーパ状側壁を
形成する際に下層配線のコンタクト面に被着する再堆積
絶縁膜を皆無にすることかできるので、微細コンタクト
面積においてもコンタクト抵抗の低い良好な配線の層間
接続が得られる。As explained above, according to the present invention, the through hole in the interlayer insulating film is formed with a tapered side wall, so even when the bottom opening diameter of the through hole is miniaturized to the limit of photolithography, the upper layer The coverage of the wiring layer is good, and disconnection is prevented, and when forming the tapered sidewall of the through hole, there is no redeposited insulating film deposited on the contact surface of the lower wiring, so the fine contact area is reduced. Also, good interlayer connections with low contact resistance can be obtained.
従って本発明は、半導体装置の高密度・高集積化する際
の、性能及び信頼性向上に寄与するところが大きい。Therefore, the present invention greatly contributes to improving performance and reliability when increasing the density and integration of semiconductor devices.
第１図（ａ）〜（ｇ）は本発明の方法の一実施例の工程
断面図、
第２図（ａ）〜（ｄ）は従来方法の工程断面図である。
図こおいて、
１は半導体基板、
２は下層絶縁膜、
３は下層Ａｔ配線、
４はＴｉＮ被覆層、
５は層間絶縁膜、
６はスルーホール、
６Ｔはテーパ状スルーホール、
７はテーパ状側壁面、
を示す。
２ト１−％ ＢＲ、ｙ）、シシ２（６リーづ（′オ色４
クリｔつコニじヂ乍−肘ｔｒうＣ七り第
図（で
の
Ａ発Ｂ月の方３λめ
実旌倚１の工科断面ｍ
第
肥ぼ／）２）FIGS. 1(a) to 1(g) are process sectional views of an embodiment of the method of the present invention, and FIGS. 2(a) to 2(d) are process sectional views of a conventional method. In the figure, 1 is a semiconductor substrate, 2 is a lower layer insulating film, 3 is a lower layer At wiring, 4 is a TiN coating layer, 5 is an interlayer insulation film, 6 is a through hole, 6T is a tapered through hole, 7 is a tapered hole The side wall surface is shown. 2 to 1-% BR, y), Shishi 2 (6 reeds ('Oiro 4
clitoris tsconjijiji - elbow tr C 7th diagram (from A to B month direction 3λ eyes 1 cross section m 2)
Claims (1)
グの選択性が得られる被覆層を上面に有する下層配線を
形成する工程と、 該下層配線形成面を覆う層間絶縁膜を形成する工程と、 次いで、異方性ドライエッチング手段を用い、該層間絶
縁膜に、該下層配線上の被覆層をエッチング停止層とし
て、該被覆層の上面に達するスルーホールを形成する工
程と、 次いで、該層間絶縁膜の表面を不活性ガスのプラズマを
用いてスパッタエッチングし、該スルーホールの側壁面
を斜面状に形成する工程と、次いで、該スルーホール底
部に表出する該被覆層を選択的にエッチング除去して該
スルーホールの底部に下層配線を直に表出せしめる工程
を含むことを特徴とする半導体装置の製造方法。 ２、前記被覆層が、下層配線の材料に対してエッチング
の選択性が得られる導電体層からなることを特徴とする
請求項１記載の半導体装置の製造方法。 ３、前記被覆層が、層間絶縁膜に対してエッチングの選
択性が得られる絶縁物層からなることを特徴とする請求
項１記載の半導体装置の製造方法。[Claims] 1. When forming a multilayer interconnection having interlayer connections, a lower interconnection layer is formed on the lower insulating film, the lower interconnection layer having a covering layer on the upper surface that provides etching selectivity with respect to the insulating film and the interconnection metal. a step of forming an interlayer insulating film covering the surface on which the lower wiring is formed, and then using an anisotropic dry etching means to apply a covering layer on the lower wiring to the interlayer insulating film as an etching stop layer. , forming a through hole reaching the upper surface of the coating layer; and then sputter etching the surface of the interlayer insulating film using inert gas plasma to form a side wall surface of the through hole in an inclined shape. and then selectively etching away the covering layer exposed at the bottom of the through hole to directly expose the lower wiring at the bottom of the through hole. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the covering layer is made of a conductive layer that provides etching selectivity with respect to the material of the underlying wiring. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the covering layer is made of an insulating material layer that provides etching selectivity with respect to an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22029490A JPH04102331A (en) | 1990-08-22 | 1990-08-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22029490A JPH04102331A (en) | 1990-08-22 | 1990-08-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04102331A true JPH04102331A (en) | 1992-04-03 |
Family
ID=16748911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22029490A Pending JPH04102331A (en) | 1990-08-22 | 1990-08-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04102331A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661193A (en) * | 1992-04-16 | 1994-03-04 | Micron Technol Inc | Method for treatment of semiconductor wafer |
| DE4331549A1 (en) * | 1993-09-16 | 1995-04-13 | Gold Star Electronics | Method for producing a ULSI semiconductor device |
| JPH07147322A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| JPH09186145A (en) * | 1995-12-29 | 1997-07-15 | Hyundai Electron Ind Co Ltd | Method for forming contact hole in semiconductor element |
-
1990
- 1990-08-22 JP JP22029490A patent/JPH04102331A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661193A (en) * | 1992-04-16 | 1994-03-04 | Micron Technol Inc | Method for treatment of semiconductor wafer |
| DE4331549A1 (en) * | 1993-09-16 | 1995-04-13 | Gold Star Electronics | Method for producing a ULSI semiconductor device |
| JPH07147322A (en) * | 1993-11-25 | 1995-06-06 | Nec Corp | Manufacture of semiconductor device |
| JPH09186145A (en) * | 1995-12-29 | 1997-07-15 | Hyundai Electron Ind Co Ltd | Method for forming contact hole in semiconductor element |
| US5940730A (en) * | 1995-12-29 | 1999-08-17 | Hyundai Electronics Industries Co., Ltd. | Method of forming a contact hole of a semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0360055A (en) | Manufacturing method of integrated circuit | |
| KR100267106B1 (en) | Method for fabricating multi-layer metal interconnection of semiconductor device | |
| JPH0519818B2 (en) | ||
| JPS61280638A (en) | Manufacture of semiconductor device | |
| US8514033B2 (en) | BAW structure with reduced topographic steps and related method | |
| JPH04102331A (en) | Manufacture of semiconductor device | |
| JPS59155128A (en) | Manufacture of semiconductor device | |
| JPH04102321A (en) | Manufacture of semiconductor device | |
| KR100278995B1 (en) | Method for forming via hole in semiconductor device | |
| JP2001313336A (en) | Manufacturing method of copper structure | |
| JPH07221110A (en) | Interconnection structure of semiconductor device and manufacture thereof | |
| JPH0570301B2 (en) | ||
| JP2783898B2 (en) | Method for manufacturing semiconductor device | |
| JPS5966125A (en) | Manufacture of semiconductor device | |
| JPH0338041A (en) | Manufacture of semiconductor device | |
| JPH04150034A (en) | Manufacture of semiconductor device | |
| JPH0366128A (en) | Multilayer interconnection structure body and its manufacture | |
| JPH06163714A (en) | Semiconductor device having multilayer interconnection structure and manufacture thereof | |
| JPH08181213A (en) | Manufacture of semiconductor device | |
| JPS6255701B2 (en) | ||
| JPS63111644A (en) | Manufacture of semiconductor device | |
| JPH0621238A (en) | Semiconductor device and manufacture thereof | |
| JPH04147650A (en) | Semiconductor device and manufacture thereof | |
| JP2002313909A (en) | Method of manufacturing multi-layer wiring structure, and semiconductor device | |
| JPS60227440A (en) | Manufacture of semiconductor device |