JPH0414859A - Lead terminal structure for electronic component - Google Patents
Lead terminal structure for electronic componentInfo
- Publication number
- JPH0414859A JPH0414859A JP11940190A JP11940190A JPH0414859A JP H0414859 A JPH0414859 A JP H0414859A JP 11940190 A JP11940190 A JP 11940190A JP 11940190 A JP11940190 A JP 11940190A JP H0414859 A JPH0414859 A JP H0414859A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- lead terminal
- electronic component
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 241000272168 Laridae Species 0.000 abstract description 3
- 238000005452 bending Methods 0.000 abstract description 2
- 230000007257 malfunction Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、例えばフラットバックＩＣ等の表面実装用
電子部品のリード端子の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a lead terminal of a surface-mounted electronic component such as a flat back IC.
第７図、第８図は例えば雑誌（Ｊｏｕｒｎａｌ ｏｆ
Ｍａｔｅｒｉａｌ ５ｃｉｅｎｃｅ Ｖｏｌ、２２．Ｎ
ｏ、１１，１９８７年、第３９０１頁〜第３９０６頁に
示された従来のフラットバックＩＣ等の表面実装用電子
部品のリード端子構造であり、第７図はＪリード型、第
８図はガルウィングリード型である。図において、（１
）はＩＣパッケージ、（２）はリード、（３）ははんだ
ペースト層、（４）はポンディングパッド、（５）は配
線基板である。Figures 7 and 8 show, for example, magazines (Journal of
Material 5science Vol, 22. N
o, 11, 1987, pp. 3901 to 3906, which show the lead terminal structures of conventional surface-mount electronic components such as flat back ICs. It is a lead type. In the figure, (1
) is an IC package, (2) is a lead, (3) is a solder paste layer, (4) is a bonding pad, and (5) is a wiring board.
従来のフラットバックＩＣ等は上記の様に構成され、こ
れらは配線基板（５）上に通常はんだ付接続により実装
して構成されている。このような基板（５）上に各種電
子部品を実装して構成される素子基板においては、多数
の電子部品を高密度に実装できて基板サイズの小形なも
のが要望される。Conventional flat back ICs and the like are constructed as described above, and are typically mounted on a wiring board (5) by soldering connections. In an element substrate constructed by mounting various electronic components on such a substrate (5), it is desired that a large number of electronic components can be mounted at high density and the substrate size be small.
従来の電子部品のり−ト端子構造は以上の様に構成され
ているので、高密度化によってリードピッチか小さくな
るにつれて、第９図に示す様にはんだか完全にポンディ
ングパッド（４）上へ吸収されず、ホンディング間にブ
リッジ（６）を生し易くなる。このブリッジ（６）を防
止するためにハンダペースト層（３）の厚さを薄くする
とオーブン不良の生じるおそれがあり信頼性が低下する
。Since the conventional electronic component glue terminal structure is constructed as described above, as the lead pitch becomes smaller due to higher density, the solder completely reaches the bonding pad (4) as shown in Figure 9. It is not absorbed and tends to cause a bridge (6) between the hondings. If the thickness of the solder paste layer (3) is reduced in order to prevent this bridge (6), there is a risk of oven failure and reliability will be lowered.
この発明の上記のような問題点を解消するためになされ
たものて、ブリッジおよびオーブン不良の発生を防止す
るとともに、フラットバックＩＣ等の高密度化を可能と
することを目的とする。This invention has been made to solve the above-mentioned problems, and it is an object of the present invention to prevent the occurrence of bridging and oven defects, and to enable higher density of flatback ICs and the like.
この発明による電子部品のリード端子構造は、２本以上
のリードを縦列に配置したものである。The lead terminal structure of an electronic component according to the present invention has two or more leads arranged in tandem.
この発明による電子部品のリード端子構造は、横方向の
リード間の間隔を大きくあけることができるようになり
、これによ７て接続に十分な量のはんだを与えても、ブ
リッジの発生を防止することができる。また、フラット
バックＩＣ等の高密度化が可能となる。The lead terminal structure of electronic components according to the present invention allows for large gaps between the leads in the lateral direction, thereby preventing the occurrence of bridging even if a sufficient amount of solder is applied for connection. can do. Further, it becomes possible to increase the density of flat back ICs and the like.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による電子部品のり−上端子構
造として、例えばフラットバックＩＣのリード端子の構
造を示す断面図である。また、第２図は第１図の■−■
線における断面図である。図において、（１）はＩＣパ
ッケージ、（２ａ） 、 （２ｂ）はリードで、２本
のリードを縦列に配置しである。（３ａ） 、 （３
ｂ）ははんだペースト層、（４ａ＞ 、 （４ｂ）は
ホンディングバット、（５）は配線基板、（７）はチッ
プ、（８）はダイパッドである。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing the structure of a lead terminal of a flat back IC, for example, as an electronic component glue-top terminal structure according to an embodiment of the present invention. Also, Figure 2 shows ■-■ in Figure 1.
FIG. In the figure, (1) is an IC package, (2a) and (2b) are leads, and two leads are arranged in a vertical line. (3a), (3
b) is a solder paste layer, (4a>, (4b) is a soldering butt, (5) is a wiring board, (7) is a chip, and (8) is a die pad.
この実施例の動作を以下に説明する。隣り合う２本のリ
ード（２ａ） 、 （２ｂ）は異なった高さで設置さ
れ、一方のリード（２ａ）はＩＣパッケージ（１）の中
てもう一方のり−１”（２ｂ）の位置まで高さを変えず
曲げ加工により移動され、ＩＣパッケージ（１）からリ
ード（２ａ） 、 （２ｂ）が高さ方向に２本並んで
出されている。この２本のリード（２）は、ともにガル
ウィングリード型に加工され、配線基板（５）にはんだ
付けされている。The operation of this embodiment will be explained below. Two adjacent leads (2a) and (2b) are installed at different heights, and one lead (2a) is placed at a height of 1" (2b) within the other IC package (1). The IC package (1) is moved by bending without changing its height, and two leads (2a) and (2b) are taken out side by side in the height direction.These two leads (2) are both attached to the gull wing. It is processed into a lead type and soldered to the wiring board (5).
上記の様に構成されたフラットバックＩＣでは、横方向
（第２図矢印へ方向）のリードの列数が従来の局となり
、リード間に十分な間隔をとることができるので、はん
だのブリッジ不良を防止することかできる。さらに、リ
ードの横方向の間隔に十分余裕ができるため、従来に比
べてリードの本数を増加することもでき、フラットバッ
クＩＣの高密度化が可能になる。In the flatback IC configured as described above, the number of rows of leads in the lateral direction (in the direction of the arrow in Figure 2) is the same as that of the conventional one, and sufficient spacing can be maintained between the leads, resulting in solder bridging problems. Is it possible to prevent this? Furthermore, since there is a sufficient margin in the lateral spacing between the leads, the number of leads can be increased compared to the conventional method, making it possible to increase the density of the flatback IC.
なお、上記実施例では縦列配置したリード（２ａ） 、
（２ｂ）を、ともにガルウィング型で形成していた
が、第３図、第４図に示すように、縦列設置した内側の
リード（２ｂ）をＪリード型としても上記実施例と同様
の効果を奏する。さらに、第３図、第４図に示す形状の
場合、上記実施例の効果に加えて、幅方向（第３図矢印
Ｂ方向）に小型化することも可能である。また、上記実
施例では２本のり−ド（２ａ） 、 （２ｂ）を縦列
配置としていたが、第５図、第６図に示すように、３本
のリード（２ａ） 、 （２ｂ） 、 （２ｃ）を
縦列配置しても上記実施例と同様の効果を奏す。この第
５図、第６図の形状では、上記実施例に比べ、さらにリ
ード（２）の横方向（第６図矢印へ方向）の間隔に余裕
ができることから、よりフラットバックＩＣの高密度化
が可能になる。In addition, in the above embodiment, the leads (2a) arranged in tandem,
(2b) were both formed of a gull wing type, but as shown in Figures 3 and 4, the same effect as in the above embodiment can be obtained by changing the inner leads (2b) installed in tandem to a J lead type. play. Furthermore, in the case of the shapes shown in FIGS. 3 and 4, in addition to the effects of the above embodiments, it is also possible to reduce the size in the width direction (direction of arrow B in FIG. 3). Furthermore, in the above embodiment, two leads (2a), (2b) were arranged in tandem, but as shown in FIGS. 5 and 6, three leads (2a), (2b), ( Even if 2c) is arranged in tandem, the same effect as in the above embodiment can be obtained. With the shapes shown in FIGS. 5 and 6, compared to the above embodiment, there is more space between the leads (2) in the lateral direction (in the direction of the arrow in FIG. 6), so the density of the flatback IC can be further increased. becomes possible.
以上のように、この発明によれば２本以上のリードを縦
列に配置するように構成したので、はんだのブリッジ不
良を防止でき、しかもＩＣ等の高密度化が容易に可能と
なる電子部品のリード端子構造か得られる効果がある。As described above, according to the present invention, since two or more leads are arranged in tandem, it is possible to prevent solder bridging defects, and moreover, it is possible to easily increase the density of electronic components such as ICs. There is an effect that can be obtained due to the lead terminal structure.
第１図はこの発明の一実施例によるフラットバックＩＣ
のリード端子の構造を示す断面図、第２図は第１図の■
−■線における断面図、第３図はこの発明の他の実施例
を示すフラットバックＩＣのり−上端子の構造の断面図
、第４図は第３図のｒＶ−ｒＶ線における断面図、第５
図はこの発明のさらに他の実施例を示すフラットバック
ＩＣの断面図、第６図は第５図のｒＶ−ｒＶ線における
断面図、第７図は従来のフラットバックＩＣのリード構
造の１つであるＪリード型を示す側面図、第８図は従来
のフラットバックＩＣのリード構造の１っであるガルウ
ィングリード型を示す側面図、第９図は配線基板上のハ
ンダのブリッジ不良状態を示す平面図である。
図において、（１）はＩＣパッケージ、（２） 、
（２ａ） 、 （２ｂ） 、 （２ｃ）はリード、
（３） 、 （３ａ） 、 （３ｂ） 、 （３
ｃ）ははんだペースト層、（４）はホンディングパッド
、（５）は配線基板である。
なお、図中、同一符号は同一 または相当部分を示す。FIG. 1 shows a flat back IC according to an embodiment of the present invention.
Figure 2 is a cross-sectional view showing the structure of the lead terminal in Figure 1.
3 is a sectional view of the structure of the flat back IC glue upper terminal showing another embodiment of the present invention; FIG. 4 is a sectional view taken along the rV-rV line in FIG. 3; 5
The figure is a sectional view of a flatback IC showing still another embodiment of the present invention, FIG. 6 is a sectional view taken along the rV-rV line of FIG. 5, and FIG. 7 is one of the lead structures of a conventional flatback IC. 8 is a side view showing a gull-wing lead type, which is one of the lead structures of conventional flatback ICs, and FIG. 9 is a side view showing a defective solder bridge on a wiring board. FIG. In the figure, (1) is an IC package, (2) is
(2a), (2b), (2c) are leads,
(3) , (3a) , (3b) , (3
c) is a solder paste layer, (4) is a bonding pad, and (5) is a wiring board. In addition, the same symbols in the figures indicate the same or equivalent parts.
Claims (1)
電子部品のリード端子構造。A lead terminal structure for an electronic component characterized by two or more leads arranged in a vertical line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11940190A JPH0414859A (en) | 1990-05-08 | 1990-05-08 | Lead terminal structure for electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11940190A JPH0414859A (en) | 1990-05-08 | 1990-05-08 | Lead terminal structure for electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0414859A true JPH0414859A (en) | 1992-01-20 |
Family
ID=14760583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11940190A Pending JPH0414859A (en) | 1990-05-08 | 1990-05-08 | Lead terminal structure for electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0414859A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| JP2008124228A (en) * | 2006-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| WO2009004878A1 (en) * | 2007-07-04 | 2009-01-08 | Fujitsu Ten Limited | Electronic part package, package parts and electronic device having the package, and package part manufacturing method |
-
1990
- 1990-05-08 JP JP11940190A patent/JPH0414859A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5592019A (en) * | 1994-04-19 | 1997-01-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and module |
| JP2008124228A (en) * | 2006-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| WO2009004878A1 (en) * | 2007-07-04 | 2009-01-08 | Fujitsu Ten Limited | Electronic part package, package parts and electronic device having the package, and package part manufacturing method |
| JP2009016572A (en) * | 2007-07-04 | 2009-01-22 | Fujitsu Ten Ltd | Package for electronic component, package component provided with the same, electronic device, and manufacturing method of package component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6760227B2 (en) | Multilayer ceramic electronic component and manufacturing method thereof | |
| US6736306B2 (en) | Semiconductor chip package comprising enhanced pads | |
| JP2756184B2 (en) | Surface mounting structure of electronic components | |
| JPH07288309A (en) | Semiconductor device, manufacture thereof and semiconductor module | |
| US6512293B1 (en) | Mechanically interlocking ball grid array packages and method of making | |
| JPH07336030A (en) | Solder land structure for printed circuit board | |
| JPH0414859A (en) | Lead terminal structure for electronic component | |
| JPH0230169A (en) | Semiconductor device | |
| JP2001094000A (en) | Semiconductor device | |
| JPS60200559A (en) | Semiconductor device | |
| JPH04243187A (en) | Printed circuit board | |
| KR950006837Y1 (en) | Outlead surface exposure type semiconductor package | |
| JPH03132092A (en) | Printed wiring board | |
| JP2822446B2 (en) | Hybrid integrated circuit device | |
| JPH0414858A (en) | Lead terminal structure for electronic component | |
| JP2611672B2 (en) | Hybrid integrated circuit device | |
| JP2536892Y2 (en) | Surface mount electronic components | |
| JPH04271190A (en) | Mounting method for surface mount semiconductor device | |
| JPH04255261A (en) | Outer lead connection structure of electronic component mounting board | |
| JPH05206359A (en) | Semiconductor electronic component and method for mounting the same | |
| JPH04199554A (en) | Semiconductor device | |
| JPS61189695A (en) | Pattern structure for multi-layer printed circuit board | |
| JPH02112267A (en) | Semiconductor device | |
| JPH07312412A (en) | Semiconductor module and its assembling method | |
| JPH0590335A (en) | Semiconductor device |