JP2536892Y2 - Surface mount electronic components - Google Patents
Surface mount electronic componentsInfo
- Publication number
- JP2536892Y2 JP2536892Y2 JP1992004906U JP490692U JP2536892Y2 JP 2536892 Y2 JP2536892 Y2 JP 2536892Y2 JP 1992004906 U JP1992004906 U JP 1992004906U JP 490692 U JP490692 U JP 490692U JP 2536892 Y2 JP2536892 Y2 JP 2536892Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- lead
- solder
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本考案は面実装電子部品に係り、
特に余剰半田を吸収することができる面実装部品のリー
ド端子の形状に関するものである。The present invention relates to a surface mount electronic component.
In particular, the present invention relates to a shape of a lead terminal of a surface mount component capable of absorbing excess solder.
【０００２】[0002]
【従来の技術】半導体材料等で形成されたチップの各端
子から信号線等を金線で引出し、複数のリードフレーム
に接続し、そのリードフレームの端子（リード端子）を
介してプリント基板等の上に設けられた外部回路に接続
可能にすると共に、前記チップ、金線及びリードフレー
ムの基部等を樹脂製ボディで覆って固定したフラットパ
ッケージは、電子装置等の多くの機器に利用されてい
る。2. Description of the Related Art A signal wire or the like is drawn out from each terminal of a chip formed of a semiconductor material or the like by a gold wire, connected to a plurality of lead frames, and a printed circuit board or the like is connected via the terminals (lead terminals) of the lead frame. The flat package, which can be connected to an external circuit provided thereon and has the chip, the gold wire, and the base of the lead frame covered with a resin body and fixed, is used in many devices such as electronic devices. .
【０００３】図３に、こうしたフラットパッケージの一
種であるＱＦＰ（Ｑuad Ｆlat Ｐackage）の従来の構成
例を示す。図３に示したＱＦＰによれば、複数のリード
フレーム１の一端が金線２でチップ３に接続され、樹脂
製ボディ４で覆われ固定されている。リードフレーム１
の他端である樹脂製ボディ４の外に引き出された脚部、
リード端子１ａは、例えばプリント基板等の上に形成さ
れた回路等に、半田付け等により接続装着される。FIG. 3 shows a conventional configuration example of a QFP (Quad Flat Package) which is a kind of such a flat package. According to the QFP shown in FIG. 3, one end of each of the plurality of lead frames 1 is connected to the chip 3 by the gold wire 2 and is covered and fixed by the resin body 4. Lead frame 1
Legs pulled out of the resin body 4 at the other end of the
The lead terminal 1a is connected and mounted to a circuit or the like formed on a printed circuit board or the like by soldering or the like.
【０００４】上記半田付けは、通常リフロー半田付けに
よる場合が多く、そのリフロー半田付けは、プリント基
板の所定ランドにクリーム状半田をスクリーン印刷によ
り適量塗布し、ＱＦＰその他を自動装着後、リフロー炉
により加熱溶融することによりなされる。The above soldering is usually performed by reflow soldering. In the reflow soldering, an appropriate amount of creamy solder is applied to a predetermined land of a printed circuit board by screen printing, QFP or the like is automatically mounted, and then a reflow furnace is used. This is done by heating and melting.
【０００５】[0005]
【考案が解決しようとする課題】ところで、最近のＱＦ
Ｐ等のフラットパッケージは、多ピン、狭ピッチ化
（１．０、０．８ｍｍ→０．６５、０．５ｍｍピッチ）
する傾向にあり、上記リフロー半田付け工程において、
半田がリード端子間を接続して半田ショートを招く半田
ブリッジが発生しやすい状況にあった。[Problems to be solved by the invention] By the way, recent QF
Flat package such as P has more pins and narrower pitch (1.0, 0.8mm → 0.65, 0.5mm pitch)
In the reflow soldering process,
There was a situation where solder connected between the lead terminals and a solder bridge which caused a solder short was likely to occur.
【０００６】この半田ブリッジは半田の量が所定量以上
に過剰となる場合や、ランドやリード端子の濡れ性が悪
く半田が広がらずに、結果として半田過剰となる場合に
生じ易い。This solder bridge is likely to occur when the amount of solder is excessive beyond a predetermined amount, or when the wettability of lands and lead terminals is poor and the solder does not spread, resulting in excessive solder.
【０００７】上記半田ブリッジ対策としてし、実開平３
−６９２４７号公報に、半田接合側のリード端子１ｂの
底辺部を図４に示すように弓形に曲げて、ランド６上の
余剰半田７を吸収する構造が開示されている。５はプリ
ント基板である。As a measure against the above solder bridge,
JP-A-69247 discloses a structure in which the bottom side of the lead terminal 1b on the solder joint side is bent in an arc shape as shown in FIG. 5 is a printed circuit board.
【０００８】しかし、上述したリード端子形状をとって
も、最近の多ピン、狭ピッチ化に伴って発生する半田ブ
リッジを防止することはできなかった。However, even with the above-described lead terminal shape, it has not been possible to prevent solder bridges that occur with recent multi-pin, narrow pitch.
【０００９】更に、また、実開平３−８３９５４号公報
に、図５に示すように複数のリード端子の長さを複数種
類設け（長いリード端子１ｃ、短いリード端子１ｄ）、
かつ、隣接するリード端子が互いに異なる長さに配設す
る構造が開示されている。しかし、この構造も上記技術
と同様に最近の多ピン、狭ピッチ化に伴って発生する半
田ブリッジを防ぐことは困難であった。In addition, Japanese Utility Model Laid-Open No. 3-83954 discloses a plurality of lead terminals having different lengths (long lead terminals 1c and short lead terminals 1d) as shown in FIG.
In addition, a structure is disclosed in which adjacent lead terminals are arranged at different lengths. However, with this structure, it is difficult to prevent solder bridges that occur with recent multi-pin and narrow pitches, similarly to the above technology.
【００１０】そこで、本考案は、多ピン、狭ピッチ化し
たＱＦＰ等のリフロー半田工程において、半田ブリッジ
の発生をより低減した面実装電子部品を提供することを
目的とする。Accordingly, an object of the present invention is to provide a surface mount electronic component in which the occurrence of solder bridges is further reduced in a reflow soldering process for a multi-pin, narrow-pitch QFP or the like.
【００１１】[0011]
【課題を解決するための手段】この考案は、電子部品本
体にプリント基板の導体部と半田接合するための複数の
リード端子を有し、この複数のリード端子として、リー
ド端子の半田接合面がプリント基板の導体部に半田付け
されるような高さの第１のリード端子と、リード端子の
半田接合面が前記第１のリード端子よりもプリント基板
の導体部から離れて、浮いた状態で半田付けされるよう
な高さの第２のリード端子とが交互に配設されてなる面
実装電子部品であって、電子部品本体の隅に位置するリ
ード端子は、第１のリード端子であることを特徴とする
ものである。According to the present invention, an electronic component body has a plurality of lead terminals for soldering to a conductor of a printed circuit board, and the plurality of lead terminals have a solder joint surface of the lead terminal. A first lead terminal having such a height as to be soldered to the conductor of the printed circuit board, and a solder joint surface of the lead terminal being further away from the conductor of the printed circuit board than the first lead terminal and floating. A surface-mounted electronic component in which second lead terminals having such a height as to be soldered are alternately arranged, and the lead terminal located at a corner of the electronic component body is a first lead terminal. It is characterized by the following.
【００１２】[0012]
【作用】本考案によれば、リード端子の半田接合面が、
互いに隣接するリード端子で交互に上下するように、す
なわち段差を持って形成されているため、リフロー半田
付け工程で余剰半田がその段差部で吸収されることにな
り、リード端子間を余剰半田で接合するような半田ブリ
ッジの形成を低減することができる。According to the present invention, the solder joint surface of the lead terminal is
Since it is formed so as to alternately move up and down between adjacent lead terminals, that is, with a step, excess solder will be absorbed by the step in the reflow soldering process, and the excess solder will be applied between the lead terminals. The formation of solder bridges for joining can be reduced.
【００１３】本考案では、リード端子を浮かせる（高く
する）程度としては、半田印刷量に見合う接合不良を生
じない範囲とする。In the present invention, the degree to which the lead terminals are raised (increased) is set to a range in which a bonding defect corresponding to the amount of printed solder does not occur.
【００１４】[0014]
【実施例】以下、本考案の実施例を図面に基づいて説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
【００１５】図１は、本考案に係るリード端子形状を有
するＱＦＰの一実施例を示す概略側面図であり、図２は
本考案に係るＱＦＰのリフロー半田付け後の要部側面図
である。FIG. 1 is a schematic side view showing an embodiment of a QFP having a lead terminal shape according to the present invention, and FIG. 2 is a side view of a main part of the QFP according to the present invention after reflow soldering.
【００１６】本実施例は、図１に示すように、樹脂製ボ
ディ１４内に封止されたチップに接続された長さが異な
るリード端子１１ａ及び１１ｂがその底面の高さが交互
に高低差を付ける（交互に浮かせる）ように配設されて
いる。ＱＦＰの４隅のリード端子は全て長くて、その底
面が低い方を設ける。In this embodiment, as shown in FIG. 1, lead terminals 11a and 11b having different lengths connected to a chip sealed in a resin body 14 are provided with alternately different bottom surfaces. (Alternatively float). All the lead terminals at the four corners of the QFP are long and the bottom surface is lower.
【００１７】このようなリードフレーム１１の複数のリ
ード端子（１１ａ，１１ｂ）を有したＱＦＰを、図２に
示すようにプリント基板１５にリフロー半田付けする
と、余剰半田１７がリード端子底面が高い（浮いた）方
のリード端子１１ｂの底面とランド１６面との間の間隙
に吸収される。各リード端子高低差（平坦度）は、従来
の図３の場合、実勢レベルで０．１５ｍｍ以下である
が、本実施例の場合イモ付き等の欠陥が発生しないよう
にするため、０．３ｍｍ以下であることが好ましい。When such a QFP having a plurality of lead terminals (11a, 11b) of the lead frame 11 is reflow-soldered to the printed circuit board 15 as shown in FIG. It is absorbed in the gap between the bottom surface of the (leading) lead terminal 11b and the land 16 surface. The height difference (flatness) of each lead terminal is 0.15 mm or less at the actual level in the case of FIG. 3 of the related art. The following is preferred.
【００１８】図２（ｂ）は、図２（ａ）のＡ−Ａ断面図
であり、リード端子１１ｂの底面とランド１６間の間
隙、約０．２５ｍｍに余剰半田１７が吸収されている状
況がよく示されている。FIG. 2B is a cross-sectional view taken along the line AA of FIG. 2A, showing a gap between the bottom surface of the lead terminal 11b and the land 16, where excess solder 17 is absorbed by about 0.25 mm. Is well shown.
【００１９】表１は本考案のＱＦＰ（リード端子の底面
高低差０．３ｍｍ）と従来の通常のＱＦＰ（リード端子
の高低差無し）の半田ブリッジ発生（ブリッジ発生Ｇａ
ｐ数／総Ｇａｐ数）を比較したデータである。なお、Ｇ
ａｐ数はリード端子間の間隙数を示す。Table 1 shows solder bridge generation (bridge generation Ga) between the QFP of the present invention (bottom height difference of lead terminal of 0.3 mm) and the conventional ordinary QFP (no height difference of lead terminal).
(number of p / total number of Gap). Note that G
The ap number indicates the number of gaps between the lead terminals.
【００２０】[0020]
【表１】 [Table 1]
【００２１】上記半田ブリッジ発生のためのＱＦＰ、半
田、ペースト半田印刷厚さの各条件は以下の通りとし
た。The respective conditions of QFP, solder, and paste solder printing thickness for generating the solder bridge are as follows.
【００２２】 ＱＦＰ；ピッチ：０．６ｍｍ ピン数：１００本 半田 ；Ｓｎ63Ｐｂ37（共晶） ペースト半田印刷厚さ；２００μｍ 表１に示したデータからもリード端子の底面高低差を付
与した本考案ＱＦＰでは半田ブリッジ発生が極めて少な
いことがわかる。QFP; Pitch: 0.6 mm Pin number: 100 Solder; Sn 63 Pb 37 (eutectic) Paste Solder printing thickness: 200 μm Based on the data shown in Table 1, a book having a difference in height between the bottom surfaces of the lead terminals. It can be seen that in the devised QFP, the occurrence of solder bridge is extremely small.
【００２３】[0023]
【考案の効果】以上説明したように、本考案によれば、
ＱＦＰ等のフラットパッケージのリフロー半田付けにお
いて、リフロー半田ブリッジを大幅に低減することが可
能であり、タッチアップ工数の減少、半田付け品質の向
上等に寄与することができる。また、電子部品本体の隅
に位置するリード端子はリード端子の半田接合面がプリ
ント基板の導体部に半田付けされるような高さとなって
いることから、電子部品本体のプリント基板に対する位
置決めを、この隅に位置するリード端子により容易に行
うことができる。[Effects of the Invention] As described above, according to the present invention,
In the reflow soldering of a flat package such as a QFP, the number of reflow solder bridges can be significantly reduced, which contributes to a reduction in the number of touch-up steps and an improvement in soldering quality. In addition, since the lead terminals located at the corners of the electronic component body are so high that the solder joint surfaces of the lead terminals are soldered to the conductors of the printed circuit board, positioning of the electronic component body with respect to the printed circuit board is difficult. This can be easily performed by the lead terminals located at the corners.
【図１】本考案に係るリード端子形状を有するＱＦＰの
一実施例を示す概略側面図である。FIG. 1 is a schematic side view showing one embodiment of a QFP having a lead terminal shape according to the present invention.
【図２】本考案に係るＱＦＰのリフロー半田付け後の要
部側面図である。FIG. 2 is a side view of a main part after reflow soldering of the QFP according to the present invention.
【図３】従来のＱＦＰの一構成例斜視図である。FIG. 3 is a perspective view of a configuration example of a conventional QFP.
【図４】従来のリード端子形状一例側面図である。FIG. 4 is a side view showing an example of a conventional lead terminal shape.
【図５】従来のリード端子形状一例斜視図である。FIG. 5 is a perspective view showing an example of a conventional lead terminal shape.
１，１１ リードフレーム １ａ，１１ａ，１１ｂ リード端子 １ｃ リード端子（長） １ｄ リード端子（短） ２ 金線 ３ チップ ４，１４ 樹脂製ボディ ５，１５ プリント基板 ６，１６ ランド ７，１７ 余剰半田 1,11 Lead frame 1a, 11a, 11b Lead terminal 1c Lead terminal (long) 1d Lead terminal (short) 2 Gold wire 3 Chip 4,14 Resin body 5,15 Printed circuit board 6,16 Land 7,17 Excess solder
Claims (1)
田接合するための複数のリード端子を有し、 前記複数のリード端子として、リード端子の半田接合面
が前記プリント基板の導体部に半田付けされるような高
さの第１のリード端子と、 リード端子の半田接合面が前記第１のリード端子よりも
前記プリント基板の導体部から離れて、浮いた状態で半
田付けされるような高さの第２のリード端子とが交互に
配設されてなる面実装電子部品であって、 前記電子部品本体の隅に位置する前記リード端子は、前
記第１のリード端子であることを特徴とする面実装電子
部品。An electronic component main body has a plurality of lead terminals for soldering to a conductor of a printed circuit board, and the plurality of lead terminals have a solder joint surface of the lead terminal soldered to the conductor of the printed circuit board. A first lead terminal having such a height as to be attached, and a solder joint surface of the lead terminal is separated from the conductor of the printed circuit board more than the first lead terminal and is soldered in a floating state. A surface-mounted electronic component in which heights of second lead terminals are alternately arranged, wherein the lead terminal located at a corner of the electronic component body is the first lead terminal. And surface mount electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992004906U JP2536892Y2 (en) | 1992-02-10 | 1992-02-10 | Surface mount electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1992004906U JP2536892Y2 (en) | 1992-02-10 | 1992-02-10 | Surface mount electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0567010U JPH0567010U (en) | 1993-09-03 |
| JP2536892Y2 true JP2536892Y2 (en) | 1997-05-28 |
Family
ID=11596696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1992004906U Expired - Lifetime JP2536892Y2 (en) | 1992-02-10 | 1992-02-10 | Surface mount electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536892Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164243U (en) * | 1987-04-15 | 1988-10-26 |
-
1992
- 1992-02-10 JP JP1992004906U patent/JP2536892Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0567010U (en) | 1993-09-03 |
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