JPH04199554A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04199554A JPH04199554A JP32525890A JP32525890A JPH04199554A JP H04199554 A JPH04199554 A JP H04199554A JP 32525890 A JP32525890 A JP 32525890A JP 32525890 A JP32525890 A JP 32525890A JP H04199554 A JPH04199554 A JP H04199554A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- shape
- outer lead
- semiconductor device
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 13
- 238000005476 soldering Methods 0.000 abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 abstract 7
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241000272168 Laridae Species 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、半導体装置に係り、特に高密度リード配置の
アウターリードの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a structure of an outer lead in a high-density lead arrangement.
（従来の技術）
近年、アウターリードの先端を実装基板表面に形成され
た配線パターン上に接続する面実装技術が盛んになって
きており、リード形状は第３図に一例を示すようなガル
ウィング型（Ｌ字型）の他、ストレート型、１字型等が
あり、これらはいずれも１つの半導体装置内では全て同
様の形状をなすように構成され、半田付けによりプリン
ト基板の回路パターン上に直接接続されるようになって
いる。(Prior art) In recent years, surface mount technology in which the tip of an outer lead is connected to a wiring pattern formed on the surface of a mounting board has become popular, and the lead shape is gull wing type, an example of which is shown in Figure 3. (L-shape), straight type, single-shape, etc. All of these are configured to have the same shape within one semiconductor device, and are soldered directly onto the circuit pattern of the printed circuit board. It is now connected.
しかしながら、半導体装置の高密度化および高集積化に
伴い、チップ面積が増大すると共にり一ドビン数が増加
するものの、パッケージは従来通りかもしくは小型化の
傾向にあり、狭ピッチとなるのを避けることはできず、
プリント基板への実装に際して、わずかな位置ずれに起
因する接続不良や半田付は不良が増大し、これが信頼性
低下の原因となっていた。However, as semiconductor devices become more dense and highly integrated, the chip area increases and the number of dobbins increases, but packages tend to remain the same or become smaller, avoiding narrow pitches. I can't do that,
When mounting on a printed circuit board, the number of connection failures and soldering failures due to slight positional deviation increases, which causes a decrease in reliability.
（発明が解決しようとする課題）
このように、従来の面実装用の半導体装置によれば、高
集積化に伴い、プリント基板への実装に際して、わずか
な位置すれに起因する接続不良や゛七田付は不良か増大
するという問題かあった。(Problems to be Solved by the Invention) As described above, according to conventional surface-mounting semiconductor devices, as the degree of integration increases, connection failures due to slight positional misalignment occur when mounting on a printed circuit board. There was a problem that the attachment was either defective or increased.
本発明は、前記実情に鑑みてなされたもので、リードピ
ッチの高密度化に際しても、実装が容品て信頼性の高い
半導体装置を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device that can be easily mounted and has high reliability even when the lead pitch is increased in density.
（課題を解決するための手段）
そこで本発明の半導体装置では、アウターリートを、封
止樹脂の外側領域でＬ字状に折り曲げられて実装面を形
成するものと、封止樹脂の外側領域て１字状に折り曲げ
られて実装面を形成するものとが交互に配置ｌｌされる
ようにしている。(Means for Solving the Problems) Therefore, in the semiconductor device of the present invention, the outer lead is bent into an L-shape in the area outside the sealing resin to form a mounting surface, and the outer lead is bent in the area outside the sealing resin to form a mounting surface. The parts that are bent into a single character shape to form the mounting surface are arranged alternately.
（作用）
上記構成によれば、アウターリードか交互にＬ字状と１
字状に成形されており、実装位置は実装面上で千鳥状に
位置しているため、半田付はピッチは実質的に２倍とな
り、位置すれに対する許容度も大きくなり、半田付は不
良の低減、作業時間の短縮および品質の安定化をはかる
ことができる。(Function) According to the above configuration, the outer lead is alternately L-shaped and 1-shaped.
It is shaped like a letter, and the mounting positions are staggered on the mounting surface, so the soldering pitch is essentially doubled, and the tolerance for positional misalignment is also greater, making it easier to avoid defective soldering. It is possible to reduce the amount of waste, shorten working time, and stabilize quality.
（実施例）
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.
第１図は本発明実施例の半導体装置］をプリント基板２
上に実装した状態を示す図である。FIG. 1 shows a semiconductor device according to an embodiment of the present invention] on a printed circuit board 2.
It is a figure which shows the state mounted on the top.
この半導体装置１は、アウターリード３か、封止樹脂４
の外側領域でＬ字状に折り曲げられて実装面を形成する
Ｌリード３ａと、封止樹脂の外側領域で１字状に折り曲
げられて実装面を形成するＪリード３ｂとが交互に配列
され、プリント基板２上で千鳥状に配列された各電極パ
ッド５上にそれぞれ半［■層６を介して面実装されてい
ることを特徴とするものである。This semiconductor device 1 has an outer lead 3 or a sealing resin 4.
L leads 3a, which are bent in an L-shape to form a mounting surface in the outer region of the sealing resin, and J leads 3b, which are bent in a single-character shape to form a mounting surface in the outer region of the sealing resin, are arranged alternately. It is characterized in that it is surface-mounted on each electrode pad 5 arranged in a staggered manner on the printed circuit board 2 through a half-layer 6.
パッケージ内部は、通常の半導体装置と同様、ダイパッ
ドのまわりにインナーリートが放射状に配列され、ダム
バーで連結されると共に、各インナーリードにアウター
リート３ａ、３ｂが連設されている。Inside the package, inner leads are arranged radially around the die pad and connected by dam bars, and outer leads 3a and 3b are connected to each inner lead, as in a normal semiconductor device.
また、このアウターリードの裏面または表面には半田め
っき層かあらかじめ形成されており、プリント基板への
実装に際して、加熱を行うことにより直接早口］付げに
よる接続が可能となるように構成されている。In addition, a solder plating layer is pre-formed on the back or surface of this outer lead, so that it is possible to connect directly by applying heat when mounting it on a printed circuit board. .
この半導体装置の製造は次のようにして行われる。This semiconductor device is manufactured as follows.
まず、通常の方法で、ダイパッド１］、インナーリード
１２、アウタリード３、ダムバー１４等を備えたリード
フレームの形状加工を行った後、アウターリードへのめ
っき工程を経、さらに必要に応じてインナーリードおよ
びアウターリード固定用のポリイミドテープＴを貼着し
、第２図（ａ）に示すようにリードフレームを形成する
。First, a lead frame including the die pad 1], inner leads 12, outer leads 3, dam bars 14, etc. is shaped using the usual method, and then the outer leads are plated, and then the inner leads are coated as necessary. Then, a polyimide tape T for fixing the outer leads is attached to form a lead frame as shown in FIG. 2(a).
このようにして形成されたリードフレームは、第２図（
ｂ）に内部断面図を示すように、ダイパッド１１上に半
導体チップ１７を接続し、ワイヤボンディング工程を経
て樹脂封止を行う。The lead frame formed in this way is shown in Figure 2 (
As shown in the internal cross-sectional view in b), the semiconductor chip 17 is connected on the die pad 11 and sealed with resin through a wire bonding process.
そして、サイドパー１５．１６およびダムバー１４を切
除し、面実装用にアウターリード３を交互にＬ字状およ
び１字状に折り曲げ、第２図（Ｃ）に示すように実装用
基板］の配線パターンの電極パッド５上に位置決めを行
い、実装用基板側を加熱することにより固着される。Then, the side bars 15 and 16 and the dam bar 14 are cut out, and the outer leads 3 are alternately bent into L-shapes and 1-shapes for surface mounting, and the wiring pattern of the mounting board is formed as shown in FIG. 2(C). is positioned on the electrode pad 5 and fixed by heating the mounting board side.
このようにして、高密度にアウターリード３か形成され
た半導体装置も、極めて容易に信頼性よく実装すること
が可能である。In this way, even a semiconductor device in which the outer leads 3 are formed in high density can be mounted extremely easily and with high reliability.
ここでは、アウターリードの実装面側の裏面をポリイミ
ドテープＴで補強するようにしているが、このように補
強することにより、高密度で肉薄のアウターリートを用
いた場合にも、面実装か極めて容易に信頼性よく実現可
能である。Here, the back side of the mounting surface side of the outer lead is reinforced with polyimide tape T, but by reinforcing it in this way, even when using a high-density and thin outer lead, surface mounting is extremely difficult. It can be easily and reliably realized.
なお、アウターリードへのポリイミドテープの貼着位置
については、前記実施例のように水平面に帯状に形成す
る他、垂直面に帯状に形成したり、封止樹脂から露呈す
る領域の表面全体に形成したり、適宜選択可能である。Regarding the position at which the polyimide tape is attached to the outer lead, in addition to forming it in a band shape on a horizontal surface as in the above example, it may be formed in a band shape on a vertical surface, or it may be formed on the entire surface of the area exposed from the sealing resin. or can be selected as appropriate.
また、前記実施例では、ポリイミドテープの貼着は、リ
ードフレームの製造工稈中に行うようにしているが、半
導体チップを実装し樹脂封止を行った後、タイバー、サ
イトバー等の切除に先立ち行うようにしても良いし、ま
たタイバー、サイドバー等の切除後に行うようにしても
よい。In the above embodiment, the polyimide tape is attached during the manufacturing process of the lead frame, but after mounting the semiconductor chip and sealing with resin, it is necessary to remove the tie bars, site bars, etc. This may be done in advance or after the tie bar, side bar, etc. are removed.
さらにまた、アウターリードの配設密度として高い部分
と低い部分とがあるなど特別の場合には特定の部分にお
いてのみＬ字状と３字状とを交互に成形するようにして
もよい。Furthermore, in special cases, such as when there are parts with a high density of outer leads and parts with a low density, L-shapes and 3-shapes may be formed alternately only in specific parts.
以」−説明してきたように、本発明によれば、アウター
リードか交互にＬ字状と３字状に成形されており、実装
位置は実装面上で千鳥状に位置しているため、半田付は
ピッチは実質的に２倍となり、位置づれに対する許容度
も大きくなり、半田付は不良の低減、作業時間の短縮お
よび品質の安定化をはかることが可能となる。- As explained above, according to the present invention, the outer leads are formed into an L-shape and a 3-shape alternately, and the mounting positions are staggered on the mounting surface, so that soldering is difficult. In soldering, the pitch is substantially doubled and the tolerance for positional deviation is increased, making it possible to reduce defects, shorten working time, and stabilize quality in soldering.
第１図は本発明実施例の半導体装置を示す図、第２図（
ａ）乃至第２図（Ｃ）は本発明実施例の半導体装Ｗを用
いたデバイスの形成工程を示す図、第３図は従来例の半
導体装置の一例を示す図である。
１・・・半導体装置、 ２・・プリント基板、３・
・・アウターリード、３ａ・・・しり一ド、３ｂ・・・
Ｊリード、 ４・封止樹脂、５・・・電極パッ
ド、 ６・・半田層、１１・・・ダイパッド、
１２・・・インナーリード、１３・・・ダムバー、
１４・・・アウターリード、１．５．１６・・・
サイドバー、
１７・・半導体チップ、 Ｔ・・・テープ。
代理人弁理士 則 近 憲 佑
同 山 下 −
第１図
第３図
、ＯＯFIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, and FIG.
A) to FIG. 2C are diagrams showing steps for forming a device using a semiconductor device W according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional semiconductor device. 1... Semiconductor device, 2... Printed circuit board, 3...
... Outer lead, 3a... Shiriido, 3b...
J lead, 4. Sealing resin, 5. Electrode pad, 6. Solder layer, 11. Die pad,
12... Inner lead, 13... Dam bar,
14...Outer lead, 1.5.16...
Sidebar, 17...Semiconductor chip, T...Tape. Representative patent attorney Nori Chika Yudo Yamashita - Figure 1 Figure 3, OO
Claims (1)
かって伸長する複数のインナーリードと、 前記各インナーリードに連設されたアウターリードとを
具備し、 樹脂封止のなされた半導体装置において 前記アウターリードの少なくとも一部は、封止樹脂の外
側領域でＬ字状に折り曲げられて実装面を形成するもの
と、封止樹脂の外側領域でＪ字状に折り曲げられて実装
面を形成するものとが１つおきに交互に配列されている
ことを特徴とする半導体装置。[Scope of Claims] A semiconductor device comprising a plurality of inner leads extending toward the vicinity of a semiconductor element mounting portion on which a semiconductor chip is mounted, and an outer lead connected to each of the inner leads, and sealed with resin. In a semiconductor device, at least a portion of the outer lead is bent into an L-shape in an area outside the sealing resin to form a mounting surface, and one is bent in a J-shape in an area outside the sealing resin to form a mounting surface. 1. A semiconductor device characterized in that semiconductor devices forming a semiconductor device are alternately arranged every other device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32525890A JPH04199554A (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32525890A JPH04199554A (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04199554A true JPH04199554A (en) | 1992-07-20 |
Family
ID=18174804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32525890A Pending JPH04199554A (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04199554A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014112104A (en) * | 2014-02-21 | 2014-06-19 | Seiko Epson Corp | Sensor device |
-
1990
- 1990-11-29 JP JP32525890A patent/JPH04199554A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014112104A (en) * | 2014-02-21 | 2014-06-19 | Seiko Epson Corp | Sensor device |
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