JPH04137730A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04137730A JPH04137730A JP26017490A JP26017490A JPH04137730A JP H04137730 A JPH04137730 A JP H04137730A JP 26017490 A JP26017490 A JP 26017490A JP 26017490 A JP26017490 A JP 26017490A JP H04137730 A JPH04137730 A JP H04137730A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- silicon nitride
- ions
- selective oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 26
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- -1 boron ions Chemical class 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 229920005591 polysilicon Polymers 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 6
- 238000001039 wet etching Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特に、素子
分離領域の微細化に伴う半導体装置の性能劣化を防ぐも
のである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and in particular, to preventing performance deterioration of a semiconductor device due to miniaturization of an element isolation region.
（従来の技術〕
素子同士を電気的に絶縁する素子分離領域には、通常、
選択酸化（ＬＯＧＯ５酸化）によって形成される厚い酸
化膜（ＬＯＧＯ３酸化膜）が利用される。(Conventional technology) In the element isolation region that electrically insulates elements from each other,
A thick oxide film (LOGO3 oxide film) formed by selective oxidation (LOGO5 oxidation) is used.
そして、素子分離領域を構成するＬＯＧＯ３酸化膜を微
細化すれば、素子間の幾何学的分離長が縮小されて、半
導体集積回路の高集積化を図ることができる。If the LOGO3 oxide film constituting the element isolation region is miniaturized, the geometrical separation length between elements is reduced, making it possible to achieve higher integration of semiconductor integrated circuits.
しかしながら、素子間の幾何学的分離長を縮小（例えば
、１μｍ程度に）した場合、バンチスルー耐圧を確保す
るためにチャネルストッパ用のイオンの単位面積当たり
の注入量を増加することになるが、従来は、ＬＯＧＯ３
酸化膜の下側にチャネルストッパを形成する、即ちＬＯ
ＧＯ３酸化を行う前に素子分離領域にチャネルストア１
＜用のイオン注入を行うので、ＬＯＣＯ３酸化膜形成の
際にチャネルストッパ用のイオンが素子領域の広い範囲
に拡散して、接合耐圧、狭チャネル効果、基板バイアス
効果等の制御に悪影響を与えてしまうという問題点があ
る。However, if the geometrical separation length between elements is reduced (for example, to about 1 μm), the amount of ions implanted per unit area for channel stopper will increase in order to ensure bunch-through breakdown voltage. Previously, LOGO3
Forming a channel stopper under the oxide film, i.e. LO
Channel store 1 is placed in the device isolation region before GO3 oxidation.
Since ion implantation is performed for LOCO3, ions for the channel stopper diffuse over a wide range of the device region during the formation of the LOCO3 oxide film, adversely affecting the control of junction breakdown voltage, narrow channel effect, substrate bias effect, etc. There is a problem with storing it away.
また、ＬＯＧＯ３酸化膜を微細にするにはバーズビーク
を抑制しなければならないが、バーズビークを抑制する
と、ＬＯＣＯ３酸化膜厚が同程度ならば、より大きな応
力歪みが半導体基板に発生して素子領域端部のゲート酸
化膜質が劣化してしまうし、局所的な薄膜化も起こって
しまう。In addition, to make the LOGO3 oxide film finer, bird's beak must be suppressed, but if the bird's beak is suppressed, if the LOCO3 oxide film thickness is the same, larger stress strain will be generated in the semiconductor substrate and the edges of the element region will be affected. The quality of the gate oxide film deteriorates, and local thinning of the film also occurs.
この発明は、このような従来の技術が有する未解決の課
題に着目してなされたものであり、ＬＯＣＯ３酸化膜の
微細化に伴って生じる半導体装置の性能劣化を防止する
ことができる半導体装置の製造方法を提供することを目
的としている。This invention was made by focusing on the unresolved problems of the conventional technology, and provides a semiconductor device that can prevent the performance deterioration of the semiconductor device that occurs due to the miniaturization of the LOCO3 oxide film. The purpose is to provide a manufacturing method.
上記目的を達成するために、請求項（１）記載の半導体
装置の製造方法は、半導体基板上に選択酸化用マスクを
形成する工程と、前記選択酸化用マスクを利用して選択
酸化を行い前記半導体基板に素子分離用の厚い酸化膜を
形成する工程と、前記厚い酸化膜形成後に前記選択酸化
用マスクの端部を除去する工程と、前記選択酸化用マス
クの端部を除去した後にチャネルストッパ用のイオンを
注入する工程と、を具備した。In order to achieve the above object, a method for manufacturing a semiconductor device according to claim (1) includes a step of forming a selective oxidation mask on a semiconductor substrate, and performing selective oxidation using the selective oxidation mask. forming a thick oxide film for element isolation on a semiconductor substrate; removing an end of the selective oxidation mask after forming the thick oxide film; and forming a channel stopper after removing the end of the selective oxidation mask. and a step of implanting ions for the purpose.
また、請求項（２）記載の半導体装置の製造方法は、上
記請求項（１）記載の半導体装置の製造方法において、
チャネルストッパ用のイオンとしてホウ素イオンを用い
るとともに、そのホウ素イオンの注入前にフッ素イオン
を注入する。Further, the method for manufacturing a semiconductor device according to claim (2) is the method for manufacturing a semiconductor device according to claim (1), comprising:
Boron ions are used as channel stopper ions, and fluorine ions are implanted before the boron ions are implanted.
素子分離用の厚い酸化膜を形成した後に、選択酸化用マ
スクの端部が除去されると、厚い酸化膜の周囲の半導体
基板、即ち、素子領域の縁の部分が露出するから、この
状態でチャネルストッパ用のイオンを注入すると、チャ
ネルストッパは、厚い酸化膜の周囲にのみ形成されるこ
とになる。そして、その後に選択酸化を行う必要はない
から、チャネルストッパ用のイオンが素子領域内の広い
範囲に拡散することがない。When the edge of the selective oxidation mask is removed after forming a thick oxide film for element isolation, the semiconductor substrate surrounding the thick oxide film, that is, the edge of the element region, is exposed. When ions for the channel stopper are implanted, the channel stopper is formed only around the thick oxide film. Since there is no need to perform selective oxidation after that, ions for the channel stopper do not diffuse into a wide range within the device region.
また、請求項（２）記載の発明のように、ホウ素イオン
の注入前にフッ素イオンを注入すると、チャネルストッ
パとしての効果はホウ素イオンによって得られ、フッ素
は、格子間シリコンを不動化するので、ホウ素イオンの
拡散が抑制される。さらに、フッ素は、シリコン酸化膜
の体積を膨張させる働きもあるので、素子領域端部の酸
化膜質の劣化や薄膜化が抑制される。Further, as in the invention described in claim (2), if fluorine ions are implanted before implanting boron ions, the effect as a channel stopper is obtained by the boron ions, and fluorine immobilizes the interstitial silicon. Diffusion of boron ions is suppressed. Furthermore, since fluorine also has the function of expanding the volume of the silicon oxide film, deterioration of the quality of the oxide film and thinning of the oxide film at the edge of the element region are suppressed.
以下、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図（ａ）乃至（ｅ）は、本発明の第１実施例の半導
体装置の製造工程を示す断面図である。FIGS. 1A to 1E are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention.
先ず、半導体基板としてのシリコン基ｉｆ上に、応力緩
和のための薄い酸化膜２を介して、選択酸化用マスクを
構成するポリシリコン膜３及びシリコン窒化膜４を積層
する（第１図（ａ）参照）。First, a polysilicon film 3 and a silicon nitride film 4 constituting a mask for selective oxidation are laminated on a silicon base if as a semiconductor substrate via a thin oxide film 2 for stress relaxation (see FIG. 1(a)). )reference).
次いで、エツチングを行って、素子分離領域上のポリシ
リコン膜３及びシリコン窒化膜４を除去する（第１図（
ｂ）参照）、なお、ポリシリコン膜３は、薄く残存する
ように除去する。Next, etching is performed to remove the polysilicon film 3 and silicon nitride film 4 on the element isolation region (see FIG.
b)), the polysilicon film 3 is removed so as to remain thin.
そして、シリコン窒化膜４をマスクとして、素子骨Ｍ
ｆｉＩ域の酸化膜２の下側にホウ素イオンＢ゛を注入す
る（第１図（ｂ）参照）。なお、このイオン注入は、フ
ィールドしきい値を制御するためのイオン注入であって
、極少量でよく、省略することも可能である。Then, using the silicon nitride film 4 as a mask, the element bone M
Boron ions B' are implanted under the oxide film 2 in the fiI region (see FIG. 1(b)). Note that this ion implantation is for controlling the field threshold value, and only a very small amount is required, so it can be omitted.
次いで、熱酸化を行えば、シリコン窒化膜４で覆われた
部分は、素子分離領域に比べて酸化速度が極めて遅いた
め、選択酸化（ＬＯＧＯ３酸化）となり、素子分離領域
に厚い酸化膜としてのＬＯＣＯ５酸化膜５が形成される
（第１図（Ｃ）参照）。Next, when thermal oxidation is performed, the oxidation rate of the portion covered with the silicon nitride film 4 is extremely slow compared to the element isolation region, so selective oxidation (LOGO3 oxidation) occurs, and LOCO5 is formed as a thick oxide film in the element isolation region. An oxide film 5 is formed (see FIG. 1(C)).
このＬＯＧＯ３酸化では、ポリシリコン膜３が酸化膜の
横方向への成長を抑制するため、バーズビークは極小さ
くて済むし、フィールドしきい値を制御するために注入
したホウ素イオンＢ゛は、極少量であるから、ＬＯＣＯ
３酸化の際にホウ素イオンＢ°が横方向に拡散しても、
素子領域にはほとんど影響が与えられない。In this LOGO3 oxidation, the polysilicon film 3 suppresses the lateral growth of the oxide film, so the bird's beak can be extremely small, and the amount of boron ions B implanted to control the field threshold is extremely small. Therefore, LOCO
Even if boron ions B° diffuse laterally during trioxidation,
The element area is hardly affected.
また、ＬＯＧＯ３酸化の際にポリシリコン膜３の端部も
酸化されるため、ＬＯＧＯ３酸化膜５の周縁部に酸化膜
６が形成されるから、シリコン窒化膜４及び酸化膜６を
ウェットエツチングにより除去すれば、ＬＯＧＯ３酸化
膜５酸化膜５リ囲ン基板１が露出する（第１図（ｄ）参
照）。Furthermore, since the edges of the polysilicon film 3 are also oxidized during LOGO3 oxidation, an oxide film 6 is formed at the peripheral edge of the LOGO3 oxide film 5. Therefore, the silicon nitride film 4 and the oxide film 6 are removed by wet etching. Then, the substrate 1 surrounding the LOGO 3 oxide film 5 oxide film 5 is exposed (see FIG. 1(d)).
次いで、ポリシリコン膜３及びＬＯＧＯ３酸化膜５をマ
スクとして、フッ素イオンＦ−及びホウ素イオンＢ°を
、この順序で注入する（第１図（ｄ）参照）。Next, using the polysilicon film 3 and the LOGO3 oxide film 5 as masks, fluorine ions F- and boron ions B° are implanted in this order (see FIG. 1(d)).
すると、素子分離領域を構成するＬＯＣＯ３酸化膜５の
周囲に、チャネルストッパ７が形成されるが、フッ素イ
オンＦ−は、ホウ素イオンＢ゛の拡散を抑制する（格子
間シリコンを不動化する）働きがあるため、パンチスル
ー耐圧を確保するためにホウ素イオンＢ゛を大量に注入
しても、素子領域への拡散はほとんどなく、接合耐圧や
基板バイアス効果等に悪影響は与えられない。Then, a channel stopper 7 is formed around the LOCO3 oxide film 5 constituting the element isolation region, but the fluorine ions F- act to suppress the diffusion of the boron ions B (immobilize the interstitial silicon). Therefore, even if a large amount of boron ions B are implanted to ensure punch-through breakdown voltage, there is almost no diffusion into the element region, and there is no adverse effect on junction breakdown voltage, substrate bias effect, etc.
このため、素子分離長を縮小しても半導体装置の性能が
劣化するような不具合がないから、素子分離領域の微細
化による半導体集積回路の集積度向上が有効に達成され
る。Therefore, even if the element isolation length is reduced, there is no problem that the performance of the semiconductor device deteriorates, so that the degree of integration of the semiconductor integrated circuit can be effectively achieved by miniaturizing the element isolation region.
そして、ポリシリコン膜３を除去した後にゲート酸化膜
８を形成する（第１図（ｅ）参照）。この場合、ＬＯＣ
Ｏ３酸化膜５酸化膜５リ囲ン基板１にはフッ素イオンＦ
−が含まれているが、シリコン酸化膜中に取り込まれた
フッ素は、その酸化膜の体積を膨張させる働きがあるた
め、ＬＯＣＯ３酸化膜５酸化膜５リ囲みに起因していた
ゲート酸化膜８の膜質劣化や薄膜化が抑制される。さら
には、シリコン基板１と、ＬＯＧＯ３酸化膜端部のゲー
ト酸化膜８との間の界面準位を減少させる効果もある。After removing the polysilicon film 3, a gate oxide film 8 is formed (see FIG. 1(e)). In this case, the LOC
O3 oxide film 5 Oxide film 5 Surrounding substrate 1 contains fluorine ions F
However, the fluorine incorporated into the silicon oxide film has the effect of expanding the volume of the oxide film, so the gate oxide film 8 caused by the LOCO3 oxide film 5 oxide film 5 Deterioration of film quality and thinning of the film are suppressed. Furthermore, it also has the effect of reducing the interface state between the silicon substrate 1 and the gate oxide film 8 at the end of the LOGO3 oxide film.
第２図（ａ）乃至（６）は、本発明の第２実施例の半導
体装置の製造工程を示す断面図である。FIGS. 2(a) to 2(6) are cross-sectional views showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention.
先ず、シリコン基板１上に薄い酸化膜２を介してシリコ
ン窒化膜４を積層しく第２図（ａ）参照）た後、素子分
離領域のシリコン窒化膜４及び酸化膜２を除去してシリ
コン基板１を露出させる（第２図（ｂ）参照）。First, a silicon nitride film 4 is laminated on a silicon substrate 1 via a thin oxide film 2 (see FIG. 2(a)), and then the silicon nitride film 4 and oxide film 2 in the element isolation region are removed to form a silicon substrate. 1 (see FIG. 2(b)).
次いで、表面全体を薄いシリコン窒化膜９及びポリシリ
コン膜１０で覆い（第２図（Ｃ）参照）、そしてポリシ
リコン膜ｌＯを部分的に除去して、素子分離領域の周囲
にサイドウオール１１を形成し、さらに、フィールドし
きい値を制御するために極少量のホウ素イオンＢ゛を素
子分離領域に注入する（第２図（ｄ）参照）。なお、ホ
ウ素イオンＢ゛の注入は、省略も可能である。Next, the entire surface is covered with a thin silicon nitride film 9 and a polysilicon film 10 (see FIG. 2(C)), and the polysilicon film 10 is partially removed to form a sidewall 11 around the element isolation region. Further, a very small amount of boron ions B' are implanted into the element isolation region in order to control the field threshold value (see FIG. 2(d)). Note that the implantation of boron ions B' can be omitted.
そして、ＬＯＧＯ３酸化を行いＬｏＣＯ３酸化膜５を形
成しく第２図（ｅ）参照）、そのＬＯＧＯ３酸化の際に
酸化したサイドウオール１１をウェットエツチングによ
り除去した後に、シリコン窒化膜４及びＬＯＧＯ３酸化
膜５をマスクとして、薄いシリコン窒化膜９を通過する
程度の打ち込みエネルギで、ＬＯＧＯ３酸化膜５の周囲
に、フッ素イオンＦ−及びホウ素イオンＢ“を、この順
序で注入する（第２図げ）参照）。Then, LOGO3 oxidation is performed to form a LoCO3 oxide film 5 (see FIG. 2(e)), and after removing the sidewall 11 oxidized during the LOGO3 oxidation by wet etching, the silicon nitride film 4 and the LOGO3 oxide film 5 are removed. Using as a mask, fluorine ions F- and boron ions B" are implanted in this order around the LOGO3 oxide film 5 with an implantation energy that is sufficient to pass through the thin silicon nitride film 9 (see Figure 2)). .
その後、シリコン窒化膜４及び９を除去し、ゲート酸化
膜８を形成する（第２図（６）参照）。Thereafter, the silicon nitride films 4 and 9 are removed, and a gate oxide film 8 is formed (see FIG. 2(6)).
この第２実施例にあっても、上記第１実施例と同様の作
用効果が得られるから、素子分離領域の微細化による半
導体集積回路の集積度向上が有効に達成されるとともに
、素子分離領域周辺のゲート酸化膜８の改善が図られる
。In this second embodiment as well, the same effects as in the first embodiment can be obtained, so that it is possible to effectively improve the degree of integration of a semiconductor integrated circuit by miniaturizing the element isolation region. The surrounding gate oxide film 8 can be improved.
〔発明の効果］
以上説明したように、請求項（１）記載の発明であれば
、厚い酸化膜を形成した後に、その周囲にチャネルスト
ッパ用のイオンを注入するため、素子領域へのイオン拡
散が抑制され、半導体装置の性能劣化が防止されるとい
う効果がある。[Effects of the Invention] As explained above, according to the invention set forth in claim (1), after forming a thick oxide film, ions for a channel stopper are implanted around the thick oxide film, so that ion diffusion into the element region is prevented. This has the effect of suppressing deterioration in the performance of the semiconductor device.
また、請求項（２）記載の発明であれば、チャネルスト
ッパ用のイオンの素子領域への拡散がさらに抑制される
とともに、厚い酸化膜周辺のゲート酸化膜の改善も図ら
れるという効果がある。Further, the invention as set forth in claim (2) has the effect that diffusion of channel stopper ions into the element region is further suppressed, and the gate oxide film around the thick oxide film is improved.
第１図（ａ）乃至（ｅ）は本発明の第１実施例の半導体
装置の製造工程を示す断面図、第２図（ａ）乃至（６）
は本発明の第２実施例の半導体装置の製造工程を示す断
面図である。
■・・・シリコン基板、３．１０・・・ポリシリコン膜
、４．９・・・シリコン窒化膜、５・・・ＬＯＣＯ３酸
化膜、７・・・チャネルストッパ、８・・・ゲート酸化
膜第
図FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2(a) to (6)
FIG. 3 is a cross-sectional view showing the manufacturing process of a semiconductor device according to a second embodiment of the present invention. ■...Silicon substrate, 3.10...Polysilicon film, 4.9...Silicon nitride film, 5...LOCO3 oxide film, 7...Channel stopper, 8...Gate oxide film No. figure
Claims (2)
と、前記選択酸化用マスクを利用して選択酸化を行い前
記半導体基板に素子分離用の厚い酸化膜を形成する工程
と、前記厚い酸化膜形成後に前記選択酸化用マスクの端
部を除去する工程と、前記選択酸化用マスクの端部を除
去した後にチャネルストッパ用のイオンを注入する工程
と、を具備したことを特徴とする半導体装置の製造方法
。(1) A step of forming a mask for selective oxidation on a semiconductor substrate, a step of performing selective oxidation using the mask for selective oxidation and forming a thick oxide film for element isolation on the semiconductor substrate, and a step of forming a thick oxide film for element isolation on the semiconductor substrate; A semiconductor device comprising the steps of removing an end of the selective oxidation mask after film formation, and implanting channel stopper ions after removing the end of the selective oxidation mask. manufacturing method.
を用いるとともに、そのホウ素イオンの注入前にフッ素
イオンを注入する請求項（１）記載の半導体装置の製造
方法。(2) The method of manufacturing a semiconductor device according to claim (1), wherein boron ions are used as ions for the channel stopper, and fluorine ions are implanted before implantation of the boron ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26017490A JPH04137730A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26017490A JPH04137730A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04137730A true JPH04137730A (en) | 1992-05-12 |
Family
ID=17344349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26017490A Pending JPH04137730A (en) | 1990-09-28 | 1990-09-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04137730A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5503214A (en) * | 1994-04-04 | 1996-04-02 | Cmi International, Inc. | Mold and method for casting a disk brake rotor |
| JP2007012884A (en) * | 2005-06-30 | 2007-01-18 | Seiko Epson Corp | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| JP2007103492A (en) * | 2005-09-30 | 2007-04-19 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| JP2008078600A (en) * | 2006-09-21 | 2008-04-03 | Hynix Semiconductor Inc | Method for forming element isolation film of semiconductor device |
-
1990
- 1990-09-28 JP JP26017490A patent/JPH04137730A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5503214A (en) * | 1994-04-04 | 1996-04-02 | Cmi International, Inc. | Mold and method for casting a disk brake rotor |
| JP2007012884A (en) * | 2005-06-30 | 2007-01-18 | Seiko Epson Corp | Semiconductor substrate manufacturing method and semiconductor device manufacturing method |
| JP2007103492A (en) * | 2005-09-30 | 2007-04-19 | Seiko Epson Corp | Semiconductor device and manufacturing method thereof |
| JP2008078600A (en) * | 2006-09-21 | 2008-04-03 | Hynix Semiconductor Inc | Method for forming element isolation film of semiconductor device |
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