JPH04130740A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH04130740A
JPH04130740A JP2253190A JP25319090A JPH04130740A JP H04130740 A JPH04130740 A JP H04130740A JP 2253190 A JP2253190 A JP 2253190A JP 25319090 A JP25319090 A JP 25319090A JP H04130740 A JPH04130740 A JP H04130740A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor chip
printed wiring
wiring board
outside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2253190A
Other languages
Japanese (ja)
Inventor
Hitoshi Arai
荒井　斉
Masaharu Ishikawa
正治 石川
Takeshi Kano
武司 加納
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2253190A priority Critical patent/JPH04130740A/en
Publication of JPH04130740A publication Critical patent/JPH04130740A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To mount a semiconductor chip on the surface of a printed wiring board without executing a spot facing working operation by a method wherein a ring-shaped groove is formed in a die pad on the outside of a part where the semiconductor chip is mounted. CONSTITUTION:A foil layer as a die pad 2 on which a semiconductor chip is mounted is arranged and installed in the center on one surface of a printed wiring board 1; a ring-shaped groove 3 which does not contain the copper foil layer is formed in the die pad part on the outside of the semiconductor-chip mounting part of the die pad 2 in such a way that the die pad 2 is left in a frame shape on its outside. Conductor circuits 5, 5,... are arranged and installed radially from the outside of the copper foil layer of the die pad 2 which has been formed in the frame shape. The conductor circuits 5, 5,... are bonded to respective external terminals 6, 6,.... When the circuits are formed and worked on the printed wiring board 1, the die pad 2 is obtained when a copper foil material is worked so as to be left as it is in the same manner as the conductor circuits 5. The groove 3 is obtained when copper is etched and removed. The ring-shaped groove 3 prevents the semiconductor chip 9 from being short-circuited with the conductor circuits 5 when a conductive adhesive 7 for mounting use overflows.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体チップ搭載用に用いられる半導体パ
ッケージ関するものであり、特に半導体チップの搭載部
の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor package used for mounting a semiconductor chip, and particularly to the structure of a mounting portion of a semiconductor chip.

〔従来の技術〕[Conventional technology]

プリント配線板から形成された半導体パッケージにおい
て、半導体チップが搭載される部分は通常凹部状の窪み
をなしている。このことは実開昭６１−１３９３８号公
報に示されており、第５図にその斜視図を、第６図にこ
の半導体パッケージに半導体チップを実装したものの断
面図を示す。In a semiconductor package formed from a printed wiring board, a portion on which a semiconductor chip is mounted usually has a concave shape. This is disclosed in Japanese Utility Model Application Publication No. 61-13938, and FIG. 5 shows a perspective view thereof, and FIG. 6 shows a sectional view of this semiconductor package with a semiconductor chip mounted thereon.

このプリント配線板１の一方の表面の中央に半導体チッ
プ搭載部１０が凹部状に形成され、この凹部の端から外
側に放射状に配設された導体回路５．５、・・・を有し
、この導体回路５．５、・・・はそれぞれの外部端子６
．６、・・・と接合されたものである。この半導体パッ
ケージにおいて、プリント配線板１の中央に形成された
凹部の半導体チップ搭載部１０、この搭載部１０に半導
体チップ９を導電性の接着剤７で固着した場合、余分な
導電性の接着剤７が半導体チップ９からはみ出しても半
導体チップ搭載部１０の凹部内で処理でき、プリント配
線板１の表面に配設された導体回路５．５・・・の短絡
するのを阻止できる。しかし、このために半導体チップ
搭載部ＩＯを凹部状に座ぐり切削加工する必要がある。A semiconductor chip mounting portion 10 is formed in the center of one surface of this printed wiring board 1 in the shape of a recess, and has conductor circuits 5.5, . . . arranged radially outward from the ends of the recess, These conductor circuits 5.5, . . . are connected to respective external terminals 6.
．． 6,... are joined. In this semiconductor package, when the semiconductor chip mounting part 10 is a recess formed in the center of the printed wiring board 1 and the semiconductor chip 9 is fixed to the mounting part 10 with a conductive adhesive 7, the excess conductive adhesive Even if the semiconductor chip 7 protrudes from the semiconductor chip 9, it can be disposed of within the recess of the semiconductor chip mounting portion 10, and short-circuiting of the conductor circuits 5, 5, . . . arranged on the surface of the printed wiring board 1 can be prevented. However, for this purpose, it is necessary to counterbore the semiconductor chip mounting portion IO into a concave shape.

座ぐり加工部分のプリント配線板１は樹脂と基材の接着
状態は均質でないために、半導体チップ搭載部の表面と
しては樹脂の剥離脱落や基材の毛羽立ちなどが多く発生
し、適しているとは言えなかった。また、座ぐり部分を
金属めっき加工する場合にも、これらのためにめっきピ
ンホールや剥離などの問題を生じる原因になりていた。Since the adhesion between the resin and the base material of the printed wiring board 1 in the counterbore area is not uniform, it is not suitable for use as the surface of the semiconductor chip mounting area, as the resin often peels off and the base material becomes fluffy. I couldn't say it. Furthermore, when metal plating is applied to the counterbore portion, these problems have caused problems such as plating pinholes and peeling.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

プリント配線板から形成される半導体パッケージにおい
て、座ぐり加工することなく半導体チップをプリント配
線板の表面に搭載できる半導体パッケージを提供するこ
とにある。An object of the present invention is to provide a semiconductor package formed from a printed wiring board in which a semiconductor chip can be mounted on the surface of the printed wiring board without performing counterboring.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前記課題を解決するための半導体パッケージで
あり、プリント配線板から形成される半導体パッケージ
において、半導体チップの搭載部分の外側のダイパッド
に環状の溝を有することを特徴とする半導体パンケージ
と半導体チップの搭載部分の外側のダイパッドに形成さ
れた環状の溝を有し、かつ溝の外側の環状のダイパッド
表面に絶縁性樹脂層を有することを特徴とする半導体パ
ッケージと半導体チップの搭載部分の外側に凸状で環状
に絶縁性樹脂層を有することを特徴とする半導体パッケ
ージを提供することにある。The present invention is a semiconductor package for solving the above-mentioned problems, and the present invention is a semiconductor package formed from a printed wiring board, and includes a semiconductor package having an annular groove in a die pad outside a mounting portion of a semiconductor chip. A semiconductor package having an annular groove formed in a die pad outside the chip mounting area, and an insulating resin layer on the surface of the annular die pad outside the groove, and the outside of the semiconductor chip mounting area. An object of the present invention is to provide a semiconductor package characterized by having an annular insulating resin layer with a convex shape.

〔実施例〕〔Example〕

以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.

第１図は本発明の一実施例の平面図で、第２図はその断
面図に半導体チップを実装した場合のものである。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the same with a semiconductor chip mounted thereon.

銅張り積層板から作られたプリント配線板を基板として
形成された半導体チップキャリアであり、プリント配線
板ｌの一方の表面の中央に半導体チップが搭載されるダ
イパッド２として銅箔層が半導体チップの形状に応じて
、特に限定しないが通常四角形状で配設され、この銅箔
層のダイパッド２の半導体チップ搭載部の外側のダイパ
ッド部分において四角形の環状に銅箔層のない溝３がそ
の外側にダイパッド２が額縁状に残存するように形成さ
れ、この額縁状に形成さたダイパッド２の銅箔層の外側
から放射状に配設された導体回路５．５・・・を有し、
この導体回路５．５・・・はそれぞれの外部端子６．６
、・・・と接合されたものである。This is a semiconductor chip carrier formed using a printed wiring board made of a copper-clad laminate as a substrate, and a copper foil layer serves as a die pad 2 on which a semiconductor chip is mounted at the center of one surface of the printed wiring board l. Depending on the shape, although not particularly limited, it is usually arranged in a rectangular shape, and in the die pad part outside the semiconductor chip mounting area of the die pad 2 of this copper foil layer, a square ring-shaped groove 3 without a copper foil layer is formed on the outside thereof. The die pad 2 is formed to remain in the shape of a picture frame, and has conductor circuits 5, 5, . . . arranged radially from the outside of the copper foil layer of the die pad 2 formed in the picture frame shape,
This conductor circuit 5.5... is connected to each external terminal 6.6.
,... are joined.

プリント配線板１の中央に配設された半導体チップが搭
載されるダイパッド２は、プリント配線板の回路形成加
工の際に導体回路５と同様に銅箔材料がそのまま残るよ
うに加工して得ることができ、ダイパッド２に環状に形
成される溝３も回路形成加工の際にエッチングレジソト
を銅箔表面に被覆しないで銅をエツチング除去すること
により回路形成と同時に容易に得ることが出来る。The die pad 2 on which the semiconductor chip is mounted, which is arranged in the center of the printed wiring board 1, is obtained by processing the printed wiring board so that the copper foil material remains as is, similar to the conductor circuit 5, during circuit formation processing of the printed wiring board. The annular groove 3 formed in the die pad 2 can also be easily obtained at the same time as the circuit is formed by etching away the copper without covering the surface of the copper foil with an etching resist during the circuit forming process.

なお、銅箔の厚み以上の溝の深さを必要とするときは、
前記溝３をガイドとしてルータ−マシンなどによってさ
らに、深い溝を加工することもできる。In addition, when the depth of the groove is required to be greater than the thickness of the copper foil,
A deeper groove can also be machined using a router machine or the like using the groove 3 as a guide.

この半導体パッケージは半導体チップの搭載されるダイ
パッド２が、導体回路５とおなし銅箔層なので、その表
面は平滑で半導体チップの搭載に適している。同時に、
ダイパッド２を金属めっきするのにも好適な素地を与え
るのである。In this semiconductor package, the die pad 2 on which the semiconductor chip is mounted is made of a copper foil layer that is similar to the conductor circuit 5, so its surface is smooth and suitable for mounting the semiconductor chip. at the same time,
This provides a suitable base for metal plating the die pad 2.

以上、ダイパッド２に環状の溝３を配設したことにより
、半導体チップ９を実装する際に用いる導電性の接着剤
７が溢れ出てもこの溝３の外側のダイパッド２の銅箔層
よって堰き止めることができ、ダイパッド２の銅箔層の
外側から放射状に配設された導体回路５に短絡は生じな
かった。As described above, by arranging the annular groove 3 in the die pad 2, even if the conductive adhesive 7 used for mounting the semiconductor chip 9 overflows, the copper foil layer of the die pad 2 outside the groove 3 can be used as a dam. No short circuit occurred in the conductor circuits 5 arranged radially from the outside of the copper foil layer of the die pad 2.

第３図には本発明の他の一実施例の断面図で半導体チッ
プを実装した場合のものである。このプリント配線板は
、前記実施例のプリント配線板１のダイパッド２に形成
された環状の溝３の外側に額縁状に形成さたダイパッド
２の銅箔層の表面に絶縁性樹脂層８が配設され、その外
側から放射状に形成された導体回路５．５、・・・を有
し、この導体回路５．５・・・はそれぞれの外部端子６
．６・・・と接合されたものである。FIG. 3 is a sectional view of another embodiment of the present invention in which a semiconductor chip is mounted. In this printed wiring board, an insulating resin layer 8 is disposed on the surface of the copper foil layer of the die pad 2 formed in a frame shape outside the annular groove 3 formed in the die pad 2 of the printed wiring board 1 of the above embodiment. and has conductor circuits 5.5, . . . formed radially from the outside, and these conductor circuits 5.5, .
．． 6... is joined.

鋼箔層からなるダイパッドの２の配設は前記と同様で、
このダイパッド２の周縁部の額縁状の銅箔層の表面にお
いて額縁状に配設された絶縁性樹脂層８は、ガラス布基
材エポキシ樹脂積層板を額縁状に加工したものに、エポ
キシ樹脂接着剤を塗布し貼り合わせた後、加熱して固着
する方法で配設した。なお、この接着側用樹脂としては
、エポキシ樹脂以外に、フェノール樹脂、ポリイミド樹
脂、および、これらの変性樹脂などを主要成分としたも
のを用いることができる。その用い方は、前記の絶縁性
樹脂層８に予め塗布したもの以外に、予め塗布し半硬化
させたもの、または、前記ダイパッド２の銅箔層に予め
塗布したもの、予め塗布し半硬化させたものなど適宜選
択して用いることができる。また、ガラス布基材エポキ
シ樹脂積層板用のプリプレグを額縁状に加工したものを
加熱加圧して貼り合わせる方法などによって配設するこ
ともできる。The arrangement of die pad 2 consisting of a steel foil layer is the same as above,
The insulating resin layer 8 arranged in a frame shape on the surface of the frame-shaped copper foil layer on the peripheral edge of the die pad 2 is made of a glass cloth base epoxy resin laminate processed into a frame shape, and is bonded with epoxy resin. After applying the agent and bonding them together, they were arranged by heating and fixing them. In addition to the epoxy resin, resins containing phenol resins, polyimide resins, modified resins thereof, etc. as main components can be used as the adhesive side resin. In addition to coating the insulating resin layer 8 in advance, it can be coated in advance and semi-cured, or it may be coated in advance on the copper foil layer of the die pad 2, or it may be coated in advance and semi-cured. These can be selected and used as appropriate. Further, it can also be provided by a method such as a method in which a prepreg for a glass cloth base epoxy resin laminate is processed into a frame shape and bonded together by heating and pressing.

なお、絶縁性樹脂層は、ガラス布基材エポキシ樹脂に限
定するのもではなく、後述するプリント配線板用の樹脂
や基材を適宜選択して用いることができる。また、これ
らの樹脂フィルムやシート物を用いることもできる。Note that the insulating resin layer is not limited to the glass cloth base epoxy resin, and resins and base materials for printed wiring boards, which will be described later, can be appropriately selected and used. Moreover, these resin films and sheets can also be used.

この半導体パッケージにおいては、ダイパッド２に半導
体チップを導電性の接着剤７で実装した場合、この接着
剤７が溢れて出ても、前記溝３と、凸部状で額縁状の絶
縁性樹脂層８によって、接着剤７がさらに外にのはみ出
るのを堰き止めることができた。In this semiconductor package, when a semiconductor chip is mounted on the die pad 2 with a conductive adhesive 7, even if this adhesive 7 overflows, the groove 3 and the convex frame-shaped insulating resin layer 8 was able to prevent the adhesive 7 from further protruding outside.

また、前記絶縁性樹脂層８がプリント配線板１０表面に
凸状に形成されているために、半導体チップ９と導体回
路５をワイヤー４を接続した後、この半導体チップ９を
保護するためにおこなう樹脂封止の樹脂封止成形加工時
にワイヤー４が変形した場合も、この凸状に配設された
絶縁性樹脂層８によって絶縁が確保でき電気的不良の発
生を防止しすることができた。In addition, since the insulating resin layer 8 is formed in a convex shape on the surface of the printed wiring board 10, after the wire 4 is connected between the semiconductor chip 9 and the conductor circuit 5, this is carried out in order to protect the semiconductor chip 9. Even if the wire 4 was deformed during the resin sealing process, the convexly disposed insulating resin layer 8 ensured insulation and prevented the occurrence of electrical defects.

第４図も本発明の他の一実施例の断面図で半導体チップ
を実装した場合のものである。このプリント配線板は、
その一方の表面の中央に半導体チップが搭載されるダイ
パッド２を有し、このダイパッド２は銅箔層からなり半
導体チップの形状に応じて特に限定しないが通常四角形
状で配設され、このダイパッド２の銅箔層の表面におい
て半導体チップ搭載部の外側のダイパッド２の周囲端部
に凸部状で額縁状に配設された絶縁樹脂層８とその外側
から放射状に形成された導体回路５．５、・・・を有し
、この導体回路５．５・・・はそれぞれの外部端子６．
６、・・・と接合されたものである。FIG. 4 is also a sectional view of another embodiment of the present invention, in which a semiconductor chip is mounted. This printed wiring board is
It has a die pad 2 on which a semiconductor chip is mounted in the center of one surface, and this die pad 2 is made of a copper foil layer and is usually arranged in a rectangular shape depending on the shape of the semiconductor chip, although not particularly limited. On the surface of the copper foil layer, an insulating resin layer 8 is arranged in a convex frame shape at the peripheral end of the die pad 2 outside the semiconductor chip mounting area, and conductor circuits 5.5 are formed radially from the outside. , . . . and these conductor circuits 5.5 . . . have respective external terminals 6.
6,... are joined.

この場合の作り方は、前記の第３図の実施例に準じて行
うことができ、この半導体パッケージも前記二つの実施
例と同様半導体チップ接着用の接着剤の溢れだしを堰き
止める効果を有した。In this case, the manufacturing method can be carried out in accordance with the embodiment shown in FIG. .

次に、プリント配線板の使用材料について述べる。プリ
ント配線板としては、基材に樹脂を含浸乾燥して得られ
たプリプレグの樹脂を硬化させて用いることができる。Next, the materials used for the printed wiring board will be described. As a printed wiring board, a prepreg resin obtained by impregnating a base material with a resin and drying it can be cured and used.

プリント配線板の樹脂としては耐熱性、耐湿性に優れか
つ樹脂純度、特にイオン性不純物の少ないものが好まし
い、具体的にはエポキシ樹脂、ポリイミド樹脂、フッ素
樹脂、ポリフェニレンオキサイド樹脂などの樹脂の単独
または、変性などの樹脂が適している。なお、プリント
配線板の基材としては、紙よりガラス繊維などの無機材
料の方が耐熱性、耐湿性などに優れ好ましい。As the resin for printed wiring boards, it is preferable to use resins that have excellent heat resistance and moisture resistance, and have high resin purity, especially low ionic impurities.Specifically, resins such as epoxy resins, polyimide resins, fluororesins, and polyphenylene oxide resins may be used alone or , modified resins, etc. are suitable. Note that as a base material for a printed wiring board, an inorganic material such as glass fiber is preferable to paper because it has superior heat resistance, moisture resistance, and the like.

プリント配線板の表面に配設された導体回路としては銅
、アルミニウム、鉄、ステンレス、真鍮、などの金属箔
をエツチング加工して回路形成して用いることができ、
中でも銅が導電性に優れ特に好ましい０回路形成法は、
前記エツチングのサブトラクティブ法に限定するもので
はなくアディティブ法、セミアデイティブ法など種々の
方法を用いることができる。The conductor circuit arranged on the surface of the printed wiring board can be formed by etching metal foil such as copper, aluminum, iron, stainless steel, or brass.
Among them, copper has excellent conductivity, so the particularly preferred 0 circuit formation method is as follows:
The etching method is not limited to the subtractive method, and various methods such as an additive method and a semi-additive method can be used.

本発明のプリント配線板は、半導体チップ搭載用として
用いることができるので、実施例で示したプリント配線
板で形成されるプラスチックビングリッドアレイ、プラ
スチックリードレスチップキャリア、および半導体チッ
プオンボードの基板として有用なものである。Since the printed wiring board of the present invention can be used for mounting semiconductor chips, it can be used as a substrate for plastic bin grid arrays, plastic leadless chip carriers, and semiconductor chip onboards formed of the printed wiring boards shown in the examples. It is useful.

〔作用〕[Effect]

プリント配線板に形成されたダイパッドに配設された溝
や、絶縁性樹脂層によって、ダイパッドに半導体チップ
を実装するのに使用する導電性の接着剤のはみ出し分が
、この溝に落ち込み溝より外にはみ出ない、絶縁性樹脂
層の凸形状で導電性の接着剤のはみ出し分が、この凸形
状で堰き止められ流出を阻止するので絶縁性樹脂層より
外にはみ出さないのである。Due to the grooves provided on the die pad formed on the printed wiring board and the insulating resin layer, the protruding portion of the conductive adhesive used to mount the semiconductor chip on the die pad falls into this groove and is removed from the groove. The protruding part of the conductive adhesive from the convex shape of the insulating resin layer is dammed by the convex shape and prevented from flowing out, so that it does not protrude outside the insulating resin layer.

絶縁性樹脂層の凸部形状は、半導体チップを封止保護す
る成形材料の成形時の流れによってワイヤーが接触する
のを阻止する作用も有する。The convex shape of the insulating resin layer also has the effect of preventing wires from coming into contact with each other due to the flow during molding of the molding material that seals and protects the semiconductor chip.

ダイパッドは、プリント配線板の金属箔層をそのまま使
用するので、回路形成と同様に行うことができ、その加
工は容易で既存の公知技術で行うことができるのである
。また、ダイパッドを金属めっきする場合もめっきに適
した平滑な表面を提供するものである。Since the die pad uses the metal foil layer of the printed wiring board as it is, it can be formed in the same way as circuit formation, and its processing is easy and can be performed using existing known techniques. Also, when metal plating the die pad, it provides a smooth surface suitable for plating.

〔発明の効果〕〔Effect of the invention〕

本発明によって、プリント配線板から形成される半導体
パッケージにおいて、座ぐり加工することなく半導体チ
ップをプリント配線板の表面に搭載できる半導体パッケ
ージが得られる。According to the present invention, it is possible to obtain a semiconductor package formed from a printed wiring board in which a semiconductor chip can be mounted on the surface of the printed wiring board without performing counterboring.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す斜視図、第２図は第１
図に半導体チップを搭載した一実施例の断面図、 第３図は本発明の他の一実施例の断面図、第４図も本発
明の他の一実施例の断面図、第５図は一従来例の斜視図
、 第６図は第５図に半導体チップを搭載したー従来例の断
面図をそれぞれ示す。 ・・・プリント配線板 ・・・ダイパッド ・・・溝 ・・・ワイヤー ・・・導体回路 ・・・外部端子 ・・・接着剤 ・・・絶縁性樹脂層 ・・・半導体チップ ・・・半導体チップ搭載部 特許出願人　　松下電工株式会社 代理人弁理士　佐藤　成示（ほか１名）箒１ 図 １１２図 １３図 １４図 １１５図 １６図FIG. 1 is a perspective view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing one embodiment of the present invention.
3 is a sectional view of another embodiment of the present invention, FIG. 4 is also a sectional view of another embodiment of the present invention, and FIG. 5 is a sectional view of another embodiment of the present invention. FIG. 6 is a perspective view of a conventional example, and FIG. 6 is a sectional view of a conventional example in which a semiconductor chip is mounted in FIG. 5. ...Printed wiring board...Die pad...Groove...Wire...Conductor circuit...External terminal...Adhesive...Insulating resin layer...Semiconductor chip...Semiconductor chip Loading section patent applicant Matsushita Electric Works Co., Ltd. Patent attorney Narji Sato (and one other person) Broom 1 Figure 112 Figure 13 Figure 14 Figure 115 Figure 16

Claims (3)

【特許請求の範囲】[Claims] （１）プリント配線板から形成される半導体パッケージ
において、半導体チップの搭載部分の外側のダイパッド
に環状の溝を有することを特徴とする半導体パッケージ
。(1) A semiconductor package formed from a printed wiring board, characterized in that a die pad outside a mounting portion of a semiconductor chip has an annular groove. （２）プリント配線板から形成される半導体パッケージ
において、半導体チップの搭載部分の外側のダイパッド
に形成された環状の溝を有し、かつ溝の外側の環状のダ
イパッド表面に絶縁性樹脂層を有することを特徴とする
半導体パッケージ。(2) A semiconductor package formed from a printed wiring board, which has an annular groove formed on the die pad outside the mounting area of the semiconductor chip, and has an insulating resin layer on the surface of the annular die pad outside the groove. A semiconductor package characterized by: （３）プリント配線板から形成される半導体パッケージ
において、半導体チップの搭載部分の外側に凸状で環状
に絶縁性樹脂層を有することを特徴とする半導体パッケ
ージ。(3) A semiconductor package formed from a printed wiring board, characterized by having a convex annular insulating resin layer on the outside of a mounting portion of a semiconductor chip.
JP2253190A 1990-09-21 1990-09-21 Semiconductor package Pending JPH04130740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2253190A JPH04130740A (en) 1990-09-21 1990-09-21 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2253190A JPH04130740A (en) 1990-09-21 1990-09-21 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH04130740A true JPH04130740A (en) 1992-05-01

Family

ID=17247802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2253190A Pending JPH04130740A (en) 1990-09-21 1990-09-21 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH04130740A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1848045A2 (en) * 2006-04-19 2007-10-24 Nichia Corporation Housing for semiconductor light emitting or receiving device
JP2008153610A (en) * 2006-11-22 2008-07-03 Nichia Chem Ind Ltd Semiconductor device
US8124881B2 (en) * 2008-02-27 2012-02-28 Kyocera Corporation Printed board and portable electronic device which uses this printed board
JP2015053442A (en) * 2013-09-09 2015-03-19 三菱電機株式会社 Semiconductor device
CN111010815A (en) * 2019-12-27 2020-04-14 安捷利（番禺）电子实业有限公司 Semiconductor chip embedded circuit board and processing method and processing device thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1848045A2 (en) * 2006-04-19 2007-10-24 Nichia Corporation Housing for semiconductor light emitting or receiving device
JP2007311749A (en) * 2006-04-19 2007-11-29 Nichia Chem Ind Ltd Semiconductor device
EP1848045A3 (en) * 2006-04-19 2012-07-18 Nichia Corporation Housing for semiconductor light emitting or receiving device
JP2008153610A (en) * 2006-11-22 2008-07-03 Nichia Chem Ind Ltd Semiconductor device
US8124881B2 (en) * 2008-02-27 2012-02-28 Kyocera Corporation Printed board and portable electronic device which uses this printed board
JP2015053442A (en) * 2013-09-09 2015-03-19 三菱電機株式会社 Semiconductor device
CN111010815A (en) * 2019-12-27 2020-04-14 安捷利（番禺）电子实业有限公司 Semiconductor chip embedded circuit board and processing method and processing device thereof

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