JPH04102375A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH04102375A JPH04102375A JP22061290A JP22061290A JPH04102375A JP H04102375 A JPH04102375 A JP H04102375A JP 22061290 A JP22061290 A JP 22061290A JP 22061290 A JP22061290 A JP 22061290A JP H04102375 A JPH04102375 A JP H04102375A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- oxide film
- film
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000010453 quartz Substances 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 27
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明は、薄膜トランジスタ（ＴＰＴ）に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to thin film transistors (TPTs).
ゲート絶縁膜の耐圧性を向上させるためにゲート絶縁膜
をＳｉ、 Ｎ４とＳｉＯ□とからなる二重構造とするこ
とは、すでに提案されている。In order to improve the voltage resistance of the gate insulating film, it has already been proposed to form the gate insulating film into a double structure consisting of Si, N4 and SiO□.
（Ｙ、 ０ｈｊｉ、 Ｔ、 Ｋｕｓａｋａ、 Ａ、 ｔ
（ｉｒａｉｗａ、 Ｋ、 Ｙａｇｉ、 Ｋ、 Ｍｕｋａ
ｉ ａｎｄ Ｏ，Ｋａｓａｈａｒａ ： ”Ｒｅ１ｉ
ａｂｉｌｉｔｙ ｏｆ ｎａｎｏ−ｍｅｔｅｒｔｈユｃ
ｋ ｍｕｌｔｉ−１ａｙｅｒ ｄｉｅｌｅｃｔｒｉ
ｃ ｏｎ ｐｏｌｙ−ｃｒｙｓｔａｌｌｉｎｅｓｉ
ｌｉｃｏｎ、” Ｐｒｏｃ、 ｏｆ Ｉｎｔｅｒｎａ
ｔｉｏｎａｌ Ｒｅ１ｉａｂｉｌｉｔｙ Ｐｈｙｓｉｃ
ｓ Ｓｙｍｐｏｓｉｕｍ （１９８７）ｐ、５５）しか
しながら、多結晶シリコン（Ｐｏｌｙ Ｓｉ）を基本材
料とした薄膜トランジスタ（ＴＰＴ）のゲート絶縁膜で
あるＳｉＯ□上にＳｉ、 Ｎ４を形成した場合、その製
膜方法がＰＣＶＤ法のようなプラズマプロセスでは製膜
中の水素プラズマによりヒステリシスを生じさせ、トラ
ンジスタ動作に、誤動作を生じさせる。又窒化膜と酸化
膜とではエツチング方法が異るため、ゲート絶縁膜を加
工するさい、工程数の増加とそれにともなうエツチング
時の加工精度の低下から歩留りの低下が問題である。さ
らに、通常のＴＰＴを駆動する場合、ゲート絶縁膜は薄
くてかつその容量が大きい程すぐれた開動特性を有する
が、Ｓｉ３Ｎ４膜との２層構造は、 Ｓｉ３Ｎ４層の容
量が５ｉｏ２ｉの容量より大きいため、これを直列にし
たことに相当するこの構造は、容量の小さい３１０２層
の厚みが大きく影響することになる。そのため、ＳｉＯ
□層を必要以上に薄くした２層構造にさぜるを得ない。(Y, 0hji, T, Kusaka, A, t
(iraiwa, K., Yagi, K., Muka
i and O, Kasahara: ”Re1i
ability of nano-meter
k multi-1ayer dielectri
c on poly-crystallinesi
licon,” Proc, of Interna
tional Re1iability Physics
s Symposium (1987) p. 55) However, when Si and N4 are formed on SiO□, which is the gate insulating film of a thin film transistor (TPT) whose basic material is polycrystalline silicon (PolySi), the film formation method is In a plasma process such as the PCVD method, hydrogen plasma during film formation causes hysteresis, which causes malfunction in transistor operation. Furthermore, since the etching methods for the nitride film and the oxide film are different, when processing the gate insulating film, there is a problem of a decrease in yield due to an increase in the number of steps and a concomitant decrease in processing accuracy during etching. Furthermore, when driving a normal TPT, the thinner the gate insulating film and the larger the capacitance, the better the opening characteristics.However, in the two-layer structure with the Si3N4 film, the capacitance of the Si3N4 layer is larger than the capacitance of 5io2i. This structure, which is equivalent to arranging 3102 layers in series, is greatly influenced by the thickness of the 3102 layer, which has a small capacitance. Therefore, SiO
□It is unavoidable to create a two-layer structure where the layers are made thinner than necessary.
本発明の目的は、上記不具合をなくすると同時に、２層
構造にともなって薄膜トランジスタの駆動特性をおとす
ことなく、高信頼性、高歩留りな、ＴＰＴを形成する点
にある。An object of the present invention is to eliminate the above-mentioned disadvantages and at the same time form a TPT with high reliability and high yield without degrading the driving characteristics of the thin film transistor due to the two-layer structure.
本発明は、絶縁基板上に設けた薄膜トランジスタのゲー
ト絶縁膜が少なくとも酸化物の２層構造であることを特
徴とする薄膜トランジスタに関する。なお１本発明にお
いては、前記ゲート絶縁膜の少なくとも活性層に近い側
の酸化物膜の厚さが５００Å以下であることが好ましい
。The present invention relates to a thin film transistor, in which a gate insulating film of the thin film transistor provided on an insulating substrate has at least a two-layer structure of oxide. Note that in the present invention, it is preferable that the thickness of at least the oxide film of the gate insulating film on the side closer to the active layer is 500 Å or less.
第４図に、従来構成であるＳｉ、ＮＪＳｉ０２２層構造
でのＴＤＤＢ（Ｔｉｍｅ Ｄｅｐｅｕｄｏｗｔ Ｄｉｅ
ｌｅｃｔｒｉｃ Ｂｒｅａｋｄｏｗｎ）特性を示す。Ｓ
ｉＯ□単層と比較して２層構造では約４桁ストレス時間
に対する奉命が延びていることがわかる。Figure 4 shows the conventional structure of TDDB (Time Depeudowt Die) with Si and NJSi022 layer structure.
electric breakdown) characteristics. S
It can be seen that the two-layer structure has a longer service life for stress time by about four orders of magnitude compared to the iO□ single layer.
本発明の構成を第１図に示す、 Ｐｏ１ｙＳｉを基本材
料としたＴＰＴのゲート絶縁膜を５ｉｎ２の２層構造と
することで第４図に示したＳｉ、Ｎ、／ＳｉＯ２と同程
度の寿命とすることができる４図中で、上部ゲート絶縁
膜はＥＣＲ、ＣＶＤ等による堆積によって形成した５ｉ
ｎ２膜であり、下部ゲート絶縁膜は熱酸化膜あるいは陽
極酸化膜が好ましい。この場合艇動特性は下部ゲート絶
縁膜の膜質及び膜厚で大きく変わってくるため、この層
の最適化が重要である。第３図に全膜厚９００人とした
場合のＳｉＯ□単層と２層（この場合下地が５００人の
熱酸化膜）の場合の工。ｎとゲートリーク電流の比較を
示す。５ｉｎ２を２層化することでゲートリーク電流は
従来より１桁以下低下している。輛動能力を示すＩｏｎ
にライては７．９５ Ｘ １０−’Ａのものが５．５Ｘ
１０−’Ａと約３０％の低下があるものの実質、問題
のないレベルを維持できることが明らかとなった。ここ
では下地ＳｉＯ□を５００人としたが、さらにこれより
うすくした場合の方がＩｏｎ及びゲートリーク電流は改
善の方向にむかい、より都合がいいことがわかった。こ
のことは、下地５ｉｎ２膜はトランジスタ特性を保証す
る膜厚さえあれば、５００Å以下で充分であることを意
味する（全５ｉｎ２の厚さは一定）。これらの構成の形
成方法を第３図に示す。■絶縁基板１上に、Ｐｏ１ｙＳ
ｉ２を形成、加工後、■熱酸化膜３、ＤｅＰＯａ化膜４
及びゲート電極５を順次堆積させ、■所定形状に加工後
、■イオン注入等の方法でゲートおよび／または、ソー
ス、ドレインに不純物を拡散、活性化を行なう、■そし
て眉間絶縁膜６を堆積し、コンタクトホール形成後、■
ＡＱを堆積、加工して電極７を形成しＴＰＴを完成する
。The structure of the present invention is shown in FIG. 1. By making the TPT gate insulating film made of Po1ySi as a basic material into a 5in2 two-layer structure, it has a lifespan comparable to that of Si, N, /SiO2 shown in FIG. 4. In Figure 4, the upper gate insulating film is a 5i film formed by deposition by ECR, CVD, etc.
The lower gate insulating film is preferably a thermal oxide film or an anodic oxide film. In this case, since the floating characteristics vary greatly depending on the quality and thickness of the lower gate insulating film, it is important to optimize this layer. Figure 3 shows the process for SiO□ single layer and double layer (in this case, the base is a thermal oxide film of 500 layers) with a total film thickness of 900 layers. A comparison of n and gate leakage current is shown. By forming 5in2 into two layers, the gate leakage current is reduced by one order of magnitude or less compared to the conventional structure. Ion showing maneuverability
7.95 x 10-'A is 5.5 x
Although there was a decrease of about 30% to 10-'A, it became clear that it was possible to maintain a practically problem-free level. Here, the thickness of the underlying SiO□ was set at 500, but it was found that making it thinner than this would improve Ion and gate leakage current, which would be more convenient. This means that a base 5in2 film of 500 Å or less is sufficient as long as it has a thickness that guarantees transistor characteristics (the thickness of the entire 5in2 film is constant). A method of forming these structures is shown in FIG. ■PolyS on the insulating substrate 1
After forming and processing i2, ■ thermal oxide film 3, DePOa film 4
and the gate electrode 5 are sequentially deposited, 1) after being processed into a predetermined shape, 2) impurities are diffused and activated in the gate and/or source and drain by a method such as ion implantation, and 2) the glabella insulating film 6 is deposited. , After contact hole formation, ■
AQ is deposited and processed to form the electrode 7 and complete the TPT.
石英基板１上ニＬＰＣＶＤ法テロ２０℃、０．１ｔｏｒ
ｒ、５ｉＨ４１００％ テ約１０００人（７）Ｐｏｌｙ
Ｓｉを堆積し、活性層２を形成後、Ｄｒｙ ０２１００
０’Ｃ１１時！’ｆｌｌｌテ約５００人の熱酸化膜３を
形成する（第１の酸化膜３の形成）。そして低温酸化膜
（ＬＴＯ）あるいは高温酸化膜（ＨＴＯ）をＬＰＣＶＤ
法（Ｓｉｌ（４１０２： ８０／２０ｓｅｃＭ、約１０
００人）により第２の酸化膜４を形成し、さらにさき程
と同一条件でＰｏ１ｙＳｉ ５を形成する。この場合、
膜厚のみ３０００人と厚くしておく。次にレジストでゲ
ート部をカバーして、ＳＦＩ； ３０ｓｅｃＭ、０、１
Ｔｏｒｒ １′Ｐｏ１ｙＳｉゲート電極をドライエツチ
ングし、ＨＦ：Ｈ２０＝１：６．３０″でゲート５ｉＯ
２（２層とも）をウェットエツチングしてソース、ドレ
イン部２′、２″を露出させる。そしてイオン注入でＰ
ｌをＩＥ１５■−２でインプラ後、９００°Ｃ１３０分
の活性化を施こす６その後、同じ＜ ＬＰＣＤ法で５ｉ
Ｈ４１０２＝８０／ ２００ｓｅｃＭで５０００人の眉
間＃ｌ！縁膜６を堆積し、ウェットエツチング（前述と
同条件）でコンタクトホールをあける。−最後にＡｆｌ
をスパッタリングにより１μｍ厚に形成し、ドライエツ
チング（ｃ２Ｆ６＋５ｉｃ１４系）で所定形状の電極７
に加工して完成する。LPCVD method on quartz substrate 1 at 20℃, 0.1torr
r, 5iH4100% Te approximately 1000 people (7) Poly
After depositing Si and forming active layer 2, dry 02100
0'C11 o'clock! A thermal oxide film 3 of approximately 500 layers is formed (formation of the first oxide film 3). Then, low temperature oxide film (LTO) or high temperature oxide film (HTO) is formed by LPCVD.
method (Sil (4102: 80/20secM, approximately 10
A second oxide film 4 is formed using a method (000 persons), and a PolySi 5 is further formed under the same conditions as before. in this case,
Only the film thickness will be increased to 3,000 people. Next, cover the gate part with resist and perform SFI; 30secM, 0, 1
Torr 1'Po1ySi gate electrode was dry etched and the gate 5iO was etched with HF:H20=1:6.30''.
2 (both layers) are wet-etched to expose the source and drain parts 2' and 2''.Then, P is etched by ion implantation.
After implanting l with IE15■-2, activate it at 900°C for 130 minutes.
H4102=80/ 5000 people's eyebrows #l at 200secM! A rim film 6 is deposited and contact holes are made by wet etching (under the same conditions as described above). -Finally Afl
was formed to a thickness of 1 μm by sputtering, and an electrode 7 of a predetermined shape was formed by dry etching (c2F6+5ic14 system).
Process and complete.
本発明は、２層にするために２回の酸化膜形成工程を経
る。そのため、それぞれの層にピンホールがあっても１
回目の層と２回目の層では発生個所が異なるため、ピン
ホールの発生が抑制されることになる。これに対して１
層の場合は、いくら厚みを厚くしても、ピンホールを完
全になくすことはできない。In the present invention, the oxide film forming process is performed twice in order to form two layers. Therefore, even if there are pinholes in each layer, 1
Since the locations where pinholes occur are different between the first layer and the second layer, the occurrence of pinholes is suppressed. 1 for this
In the case of layers, no matter how thick they are, pinholes cannot be completely eliminated.
本発明の薄膜トランジスタは、従来品に較べ高信頼性で
かつ従来と同等の駆動特性を有したＴＰＴの提供が可能
となった。The thin film transistor of the present invention makes it possible to provide a TPT that is more reliable than conventional products and has drive characteristics equivalent to conventional products.
本ＴＰＴは光読取り装置等の半導体装置として極めて有
用である。This TPT is extremely useful as a semiconductor device such as an optical reader.
第１図は、本発明ＴＰＴの基本構成を示す断面図、第２
図Ａは、５ｉｎ２単層（９００人厚定形５ｉｎ２の２層
（下層５００人厚１上層４００人厚１のそれぞれのＩｏ
ｎ（Ｎｃｈ）（Ｘ １０−’Ａ 〕を示し、Ｂは１両者
のゲートリーク電流を示す。第３図は、本発明ＴＰＴの
製造工程例を■〜■で示す。第４図は、従来のＳｉ３Ｎ
４／５ｉ０２２層構造タイプのＰｏ１ｙ−５ｉ上の各種
絶縁膜のＴＤＤＢ特性例を示す。
１・・・絶縁基板 ２・・・Ｐｏ１ｙＳｉ （活
性層）２’、２”・・・ソース、ドレイン部
３・・・熱酸化膜（下部ゲート絶縁膜）４・・Ｄｅｐｏ
酸化膜（上部ゲートＭ縁膜）５・・・ゲート電極
６・・・層間絶縁膜７・・・１１電極
特許出顕人
株式会社
第
図
第３
第４
図
ストレス１藺（ＳｌFIG. 1 is a sectional view showing the basic configuration of the TPT of the present invention, and FIG.
Diagram A shows the Io
n (Nch) (X 10-'A ], and B indicates the gate leakage current of both. Fig. 3 shows an example of the manufacturing process of the TPT of the present invention with ■ to ■. Fig. 4 shows the conventional TPT. Si3N
Examples of TDDB characteristics of various insulating films on 4/5i022 layer structure type Po1y-5i are shown. 1... Insulating substrate 2... Po1ySi (active layer) 2', 2''... Source, drain part 3... Thermal oxide film (lower gate insulating film) 4... Depo
Oxide film (upper gate M edge film) 5...gate electrode
6... Interlayer insulating film 7... 11 Electrode Patented Kenjin Co., Ltd. Figure 3 Figure 4 Stress 1 (Sl
Claims (1)
膜が少なくとも酸化物の２層構造であることを特徴とす
る薄膜トランジスタ。 ２、前記ゲート絶縁膜の少なくとも活性層に近い側の酸
化物膜の厚さが５００Å以下であることを特徴とする請
求項１記載の薄膜トランジスタ。[Scope of Claims] 1. A thin film transistor characterized in that a gate insulating film of the thin film transistor provided on an insulating substrate has at least a two-layer structure of oxide. 2. The thin film transistor according to claim 1, wherein the oxide film of the gate insulating film at least on the side closer to the active layer has a thickness of 500 Å or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22061290A JPH04102375A (en) | 1990-08-22 | 1990-08-22 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22061290A JPH04102375A (en) | 1990-08-22 | 1990-08-22 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04102375A true JPH04102375A (en) | 1992-04-03 |
Family
ID=16753703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22061290A Pending JPH04102375A (en) | 1990-08-22 | 1990-08-22 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04102375A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591989A (en) * | 1990-11-16 | 1997-01-07 | Seiko Epson Corporation | Semiconductor device having first and second gate insulating films |
| US5663077A (en) * | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
| US6124153A (en) * | 1995-07-14 | 2000-09-26 | Samsung Electronics Co., Ltd. | Method for manufacturing a polysilicon TFT with a variable thickness gate oxide |
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6329229B1 (en) | 1993-11-05 | 2001-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Method for processing semiconductor device, apparatus for processing a semiconductor and apparatus for processing semiconductor device |
-
1990
- 1990-08-22 JP JP22061290A patent/JPH04102375A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591989A (en) * | 1990-11-16 | 1997-01-07 | Seiko Epson Corporation | Semiconductor device having first and second gate insulating films |
| US5811323A (en) * | 1990-11-16 | 1998-09-22 | Seiko Epson Corporation | Process for fabricating a thin film transistor |
| US6168980B1 (en) | 1992-08-27 | 2001-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5663077A (en) * | 1993-07-27 | 1997-09-02 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films |
| US5966594A (en) * | 1993-07-27 | 1999-10-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6210997B1 (en) | 1993-07-27 | 2001-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6465284B2 (en) | 1993-07-27 | 2002-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6329229B1 (en) | 1993-11-05 | 2001-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Method for processing semiconductor device, apparatus for processing a semiconductor and apparatus for processing semiconductor device |
| US6124153A (en) * | 1995-07-14 | 2000-09-26 | Samsung Electronics Co., Ltd. | Method for manufacturing a polysilicon TFT with a variable thickness gate oxide |
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