US20030211682A1 - Method for fabricating a gate electrode - Google Patents

Method for fabricating a gate electrode Download PDF

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US20030211682A1
US20030211682A1 US10/141,870 US14187002A US2003211682A1 US 20030211682 A1 US20030211682 A1 US 20030211682A1 US 14187002 A US14187002 A US 14187002A US 2003211682 A1 US2003211682 A1 US 2003211682A1
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layer
rapid thermal
thermal process
gate electrode
barrier layer
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Jason Jenq
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JENQ, JASON JYH-SHYANG
Priority to CN02156118A priority patent/CN1457086A/en
Priority to US10/655,866 priority patent/US6884671B2/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention generally relates to a method for fabricating a gate electrode on a substrate, and more particularly to a method for reducing the dielectric constant of gate electrode.
  • Refractory metals or refractory metal alloys, their nitrides, and aluminum are alternative materials currently being investigated for use as gate electrodes. These materials offer potential advantages over materials such as polysilicon because of their patternability, low sheet resistance, and scalability to advanced metal oxide semiconductor technologies.
  • refractory metals currently being considered include titanium, tantalum, tungsten, molybdenum, zirconium, or the like.
  • refractory metal materials for use as a gate electrode, a number of factors must be considered. Among these include the electric, chemical, and physical properties of the refractory metal material. The selection process is further complicated because these properties can change as the refractory metal material is subjected to various thermal processing steps. Failure to compensate for these thermally induced changes can impact yield and potentially affect the reliability of the semiconductor device.
  • the SiO 2 or SiN as a gate dielectric material is formed on the substrate.
  • the S/D current source/drain current
  • the thickness of gate dielectric must be reduced.
  • the SiO 2 or SiN has EOT (effective oxide thickness) is smaller than 17 angstrom such that the tunneling will be occurred, and further the gate leakage current will be increased extremely.
  • the dielectric material such as Hf (hafnium) and Zr (zirconium) are deposited on the semiconductor device during the CMOS (complementary metal oxide semiconductor) process.
  • the dielectric material has been attention for low resistivity, and the thermal and chemical stability are poor such as for Hf and Zr.
  • other dielectric materials are used only for 100 nm CMOS (complementary metal oxide semiconductor) fabrication such as Ta 2 O 5 (tantalum pentoxide) and PZT (Lead Zirconium Titanate).
  • the first object of the present invention is to increase the coupling ratio of gate electrode with first nitrogen-containing rapid thermal process (nitrogen-containing RTP) treatment during the fabrication of the CMOS (complementary metal oxide semiconductor) process.
  • the second object of the present invention is to provide the alternative dielectric material has a dielectric constant higher than 10 to form on the substrate to improve the thermal stability and chemical stability for the gate electrode.
  • the third object of the present invention is to provide a treatment to improve the quality of the gate dielectric film and gate electrode.
  • the leakage current and reliability is the most issue for the fabrication of the semiconductor device.
  • a method is provided to increase the coupling ratio of the gate electrode.
  • the prevent invention is utilized the nitrogen-containing RTP treatment on the substrate to form an interface diffusion barrier layer thereon.
  • the interface diffusion barrier layer is used to separate the dielectric layer and substrate in order to reduce the likelihood of adverse interactions between the two materials.
  • the invention is utilized the dielectric material to deposit on the interface diffusion barrier layer to improve the thermal stability and chemical stability of the semiconductor substrate.
  • the post-deposition annealing in nitrogen gas is performed on the dielectric layer to release the stress and reduce the interface charge. The leakage current will be reduced and the reliability and quality of semiconductor device are also to be improved.
  • FIG. 1 is a schematic representation showing a field oxide region and a gate oxide layer on a substrate in accordance with a method disclosed herein;
  • FIG. 2 is a schematic representation showing a first nitrogen-containing rapid thermal process (nitrogen-containing RTP) treatment performed on the semiconductor substrate in accordance with a method disclosed;
  • FIG. 3 is a schematic representation showing an interface diffusion barrier layer is formed on the structure of FIG. 2 after the first ammonia rapid thermal process (NH 3 RTP) treatment, and a dielectric layer is deposited on the interface diffusion barrier layer;
  • NH 3 RTP ammonia rapid thermal process
  • FIG. 4 is a schematic representation showing a post-deposition annealing in nitrogen to treat the dielectric layer in accordance with a method disclosed;
  • FIG. 5 is a schematic representation showing a barrier layer and a metal gate layer formed on the structure of FIG. 4 in accordance with a method disclosed;
  • FIG. 6 is a schematic representation showing a second nitrogen-containing rapid thermal process (nitrogen-containing RTP) to treat a gate electrode after the gate electrode is formed on the substrate in accordance with a method disclosed; and
  • FIG. 7 is showing a schematic representation showing a surface inhibition layer on the sidewall of the gate electrode in accordance with a method disclosed.
  • a SiO 2 layer (silicon dioxide layer) (not shown) is first formed on the substrate 10 by thermal oxidation method. Then, a SiN layer (silicon nitride layer) (not shown) is deposited on the SiO 2 layer by conventional chemical vapor deposition method, such as low-pressure chemical vapor deposition (LPCVD). Next, the active regions are now defined with a photolithography step. A photoresist layer is normally used to protect all of the areas where active devices will be formed. The SiN layer is then dry etched, and the SiO 2 layer is etched by means of either a dry- or wet-chemical process.
  • LPCVD low-pressure chemical vapor deposition
  • the photoresist layer is not removed but instead is left in place to serve as a masking layer during the formation of twin wells (not shown) and channel-stop implant step.
  • the channel stop layer (not shown) is formed in the substrate 10 by conventional implanting process.
  • the field oxide 12 is thermally grown by means of wet oxidation.
  • the oxide grows where there is no masking nitride, but at the edge of the nitride, some oxidant also diffuses laterally. This causes the oxide to grow under and lift the nitride edges. Because the shape of the oxide at the oxide edges is that of a slowly tapering oxide wedge that merges into the pad oxide, it has been named a bird's beak.
  • the bird's beak is a lateral extension of the field oxide 12 into the active area of the devices.
  • a gate oxide 14 is grown on the substrate 10 by thermal oxidation method.
  • the prevent invention is provided a first nitrogen-containing RTP (nitrogen-containing rapid thermal process) treatment 16 to treat the substrate 10 to form an interface diffusion barrier layer 18 over the substrate 10 as shown in FIG. 3.
  • the nitrogen-containing gas can be N 2 gas (nitrogen gas) or NH 3 gas (ammonia gas). Then, the interface diffusion barrier layer 18 used to separate the dielectric material and substrate 10 in order to reduce the likelihood of adverse interactions between the two materials.
  • the material of the interface diffusion barrier layer can be SiON y or SiON x .
  • the temperature of the first nitrogen-containing RTP treatment 16 is between 600° C. to 750° C. and duration is between 10 to 20 minutes. Then, referring to FIG. 3 and FIG. 4, a dielectric layer 20 has dielectric constant higher than 10 that is deposited on the interface diffusion barrier layer 18 by conventional chemical vapor deposition method.
  • the material of dielectric layer 20 can be zirconium dioxide, hafnium dioxide, zirconium-silicates ((ZrO 2 ) x (SiO 2 ) 1 ⁇ x ), and hafnium-silicates (HfO 2 ) x (SiO 2 ) 1 ⁇ x ), which are good candidates for high dielectric for their reasonable high dielectric constant, has low resistivity, good thermal stability, and chemical stability, wherein the suffix x preferably 25% to 35%.
  • the post deposition treatment of the present invention is a series of anneal steps that together improve the interface characteristics and electrical properties of deposited metal oxide dielectric film.
  • a post-deposition annealing in nitrogen 22 is treated on the dielectric layer 20 to release the stress and reduce the interface charge such that the gate leakage current will be reduced, wherein the temperature of the post-deposition annealing in nitrogen 22 is between 700° C. to 900° C. and the duration is between 20 to 45 minutes.
  • the TiN (titanium nitride) as a barrier layer 24 with thickness 20 to 60 angstroms is first deposited on the dielectric layer 20 , and the Ta (tantalum) as a metal gate layer is then deposited on barrier layer 24 .
  • the Ta is widely used as a material of metal gate layer 26 its low resistivity, good thermal and chemical stability.
  • a photoresist layer (not shown) is formed on the metal gate layer 26 , and an etching process is performed on the metal gate layer 26 , barrier layer 24 , dielectric layer 20 , and interface diffusion barrier layer 18 to form a gate electrode structure on the substrate 10 .
  • the second nitrogen-containing RTP treatment 30 is performed on the gate electrode structure with temperature at 600° C. and duration of the process is about 20 minutes to form a surface inhibition layer 40 such as TaN x film on sidewall of the metal gate layer 26 of the gate electrode structure (shown in FIG. 7). Due to the surface inhibition layer 40 is formed on the surface of metal gate layer 26 , therefore, the Ta server as a metal gate layer 26 has a low resistivity and good thermal stability, especially with the nitrogen-containing RTP treatment.
  • the dielectric layer 20 is utilized to improve the quality of gate electrode for their reasonable high dielectric constant, good thermal stability, and chemical stability. Furthermore, the metal gate layer 26 has low resistivity, good thermal and chemical stability to serve as a metal gate material, especially with nitrogen-containing RTP treatment such that the quality and reliability of gate electrode can be improved.

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Abstract

A method for fabricating a gate electrode is disclosed. The present invention is provided a method to utilize the first nitrogen-containing RTP treatment to treat the substrate to form an interface diffusion barrier layer thereon. Then, the dielectric material has high dielectric constant that is deposited on the interface diffusion barrier layer to improve the thermal stability and chemical stability of the semiconductor substrate. Next, a barrier layer and a metal gate layer are sequentially formed on the dielectric layer. After a photolithography process, a gate electrode structure is formed on the semiconductor substrate. Thereafter, a surface inhibition layer is formed on sidewall of the gate electrode structure to improve the resistivity and thermal stability for metal gate layer after a second nitrogen-containing RTP treatment is performed on the gate electrode structure,

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention generally relates to a method for fabricating a gate electrode on a substrate, and more particularly to a method for reducing the dielectric constant of gate electrode. [0002]
  • 2. Description of the Prior Art [0003]
  • The use of conventional gate electrode and gate dielectric material is becoming increasingly problematic as feature sizes of semiconductor devices are continuing to be scaled to smaller dimensions. Among the problems encountered include increased resistance of the gate electrode, leakage of the gate dielectric, and polysilicon gate depletion effects. In an effort to overcome these problems, alternative materials are being investigated to replace conventional gate dielectric and gate electrode materials. [0004]
  • Refractory metals or refractory metal alloys, their nitrides, and aluminum are alternative materials currently being investigated for use as gate electrodes. These materials offer potential advantages over materials such as polysilicon because of their patternability, low sheet resistance, and scalability to advanced metal oxide semiconductor technologies. Among the refractory metals currently being considered include titanium, tantalum, tungsten, molybdenum, zirconium, or the like. [0005]
  • In selecting refractory metal materials for use as a gate electrode, a number of factors must be considered. Among these include the electric, chemical, and physical properties of the refractory metal material. The selection process is further complicated because these properties can change as the refractory metal material is subjected to various thermal processing steps. Failure to compensate for these thermally induced changes can impact yield and potentially affect the reliability of the semiconductor device. [0006]
  • In generally, after the isolation structure such as STI (shallow trench isolation) or LOCOS (local oxidation) formed in the substrate, the SiO[0007] 2 or SiN as a gate dielectric material is formed on the substrate. In order to increase the S/D current (source/drain current), therefore, the thickness of gate dielectric must be reduced. However the SiO2 or SiN, has EOT (effective oxide thickness) is smaller than 17 angstrom such that the tunneling will be occurred, and further the gate leakage current will be increased extremely.
  • Further another disadvantage is that the dielectric material such as Hf (hafnium) and Zr (zirconium) are deposited on the semiconductor device during the CMOS (complementary metal oxide semiconductor) process. The dielectric material has been attention for low resistivity, and the thermal and chemical stability are poor such as for Hf and Zr. Furthermore, other dielectric materials are used only for 100 nm CMOS (complementary metal oxide semiconductor) fabrication such as Ta[0008] 2O5 (tantalum pentoxide) and PZT (Lead Zirconium Titanate).
    • SUMMARY OF THE INVENTION
  • The first object of the present invention is to increase the coupling ratio of gate electrode with first nitrogen-containing rapid thermal process (nitrogen-containing RTP) treatment during the fabrication of the CMOS (complementary metal oxide semiconductor) process. [0009]
  • The second object of the present invention is to provide the alternative dielectric material has a dielectric constant higher than [0010] 10 to form on the substrate to improve the thermal stability and chemical stability for the gate electrode.
  • The third object of the present invention is to provide a treatment to improve the quality of the gate dielectric film and gate electrode. [0011]
  • In the present invention, the leakage current and reliability is the most issue for the fabrication of the semiconductor device. In the present invention is that a method is provided to increase the coupling ratio of the gate electrode. The prevent invention is utilized the nitrogen-containing RTP treatment on the substrate to form an interface diffusion barrier layer thereon. The interface diffusion barrier layer is used to separate the dielectric layer and substrate in order to reduce the likelihood of adverse interactions between the two materials. Then, the invention is utilized the dielectric material to deposit on the interface diffusion barrier layer to improve the thermal stability and chemical stability of the semiconductor substrate. Next, the post-deposition annealing in nitrogen gas is performed on the dielectric layer to release the stress and reduce the interface charge. The leakage current will be reduced and the reliability and quality of semiconductor device are also to be improved.[0012]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: [0013]
  • FIG. 1 is a schematic representation showing a field oxide region and a gate oxide layer on a substrate in accordance with a method disclosed herein; [0014]
  • FIG. 2 is a schematic representation showing a first nitrogen-containing rapid thermal process (nitrogen-containing RTP) treatment performed on the semiconductor substrate in accordance with a method disclosed; [0015]
  • FIG. 3 is a schematic representation showing an interface diffusion barrier layer is formed on the structure of FIG. 2 after the first ammonia rapid thermal process (NH[0016] 3 RTP) treatment, and a dielectric layer is deposited on the interface diffusion barrier layer;
  • FIG. 4 is a schematic representation showing a post-deposition annealing in nitrogen to treat the dielectric layer in accordance with a method disclosed; [0017]
  • FIG. 5 is a schematic representation showing a barrier layer and a metal gate layer formed on the structure of FIG. 4 in accordance with a method disclosed; [0018]
  • FIG. 6 is a schematic representation showing a second nitrogen-containing rapid thermal process (nitrogen-containing RTP) to treat a gate electrode after the gate electrode is formed on the substrate in accordance with a method disclosed; and [0019]
  • FIG. 7 is showing a schematic representation showing a surface inhibition layer on the sidewall of the gate electrode in accordance with a method disclosed.[0020]
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims. [0021]
  • Referring to FIG. 1, a SiO[0022] 2 layer (silicon dioxide layer) (not shown) is first formed on the substrate 10 by thermal oxidation method. Then, a SiN layer (silicon nitride layer) (not shown) is deposited on the SiO2 layer by conventional chemical vapor deposition method, such as low-pressure chemical vapor deposition (LPCVD). Next, the active regions are now defined with a photolithography step. A photoresist layer is normally used to protect all of the areas where active devices will be formed. The SiN layer is then dry etched, and the SiO2 layer is etched by means of either a dry- or wet-chemical process. After the SiO2 layer has been etched, the photoresist layer is not removed but instead is left in place to serve as a masking layer during the formation of twin wells (not shown) and channel-stop implant step. The channel stop layer (not shown) is formed in the substrate 10 by conventional implanting process.
  • Next, after the photoresist layer is stripped, the [0023] field oxide 12 is thermally grown by means of wet oxidation. The oxide grows where there is no masking nitride, but at the edge of the nitride, some oxidant also diffuses laterally. This causes the oxide to grow under and lift the nitride edges. Because the shape of the oxide at the oxide edges is that of a slowly tapering oxide wedge that merges into the pad oxide, it has been named a bird's beak. The bird's beak is a lateral extension of the field oxide 12 into the active area of the devices. Then, a gate oxide 14 is grown on the substrate 10 by thermal oxidation method.
  • Next, referring to FIG. 2, in order to improve the quality of gate dielectric film and gate electrode, the prevent invention is provided a first nitrogen-containing RTP (nitrogen-containing rapid thermal process) [0024] treatment 16 to treat the substrate 10 to form an interface diffusion barrier layer 18 over the substrate 10 as shown in FIG. 3. In the embodiment of the present invention, the nitrogen-containing gas can be N2 gas (nitrogen gas) or NH3 gas (ammonia gas). Then, the interface diffusion barrier layer 18 used to separate the dielectric material and substrate 10 in order to reduce the likelihood of adverse interactions between the two materials. During the fist nitrogen-containing RTP treatment 16, the ammonia reacted with gate oxide 14 and substrate 10, the material of the interface diffusion barrier layer can be SiONy or SiONx. The temperature of the first nitrogen-containing RTP treatment 16 is between 600° C. to 750° C. and duration is between 10 to 20 minutes. Then, referring to FIG. 3 and FIG. 4, a dielectric layer 20 has dielectric constant higher than 10 that is deposited on the interface diffusion barrier layer 18 by conventional chemical vapor deposition method. The material of dielectric layer 20 can be zirconium dioxide, hafnium dioxide, zirconium-silicates ((ZrO2)x(SiO2)1−x), and hafnium-silicates (HfO2)x(SiO2)1−x), which are good candidates for high dielectric for their reasonable high dielectric constant, has low resistivity, good thermal stability, and chemical stability, wherein the suffix x preferably 25% to 35%.
  • Next, the post deposition treatment of the present invention is a series of anneal steps that together improve the interface characteristics and electrical properties of deposited metal oxide dielectric film. Referring to FIG. 4, a post-deposition annealing in [0025] nitrogen 22 is treated on the dielectric layer 20 to release the stress and reduce the interface charge such that the gate leakage current will be reduced, wherein the temperature of the post-deposition annealing in nitrogen 22 is between 700° C. to 900° C. and the duration is between 20 to 45 minutes.
  • Then, referring to FIG. 5, in order to reduce the diffuse of oxygen atom to Ta layer (tantalum) [0026] 26 in high thermal temperature, in the present invention, the TiN (titanium nitride) as a barrier layer 24 with thickness 20 to 60 angstroms is first deposited on the dielectric layer 20, and the Ta (tantalum) as a metal gate layer is then deposited on barrier layer 24. Herein, the Ta is widely used as a material of metal gate layer 26 its low resistivity, good thermal and chemical stability. Next, referring to FIG. 6, a photoresist layer (not shown) is formed on the metal gate layer 26, and an etching process is performed on the metal gate layer 26, barrier layer 24, dielectric layer 20, and interface diffusion barrier layer 18 to form a gate electrode structure on the substrate 10.
  • Next, the second nitrogen-containing [0027] RTP treatment 30 is performed on the gate electrode structure with temperature at 600° C. and duration of the process is about 20 minutes to form a surface inhibition layer 40 such as TaNx film on sidewall of the metal gate layer 26 of the gate electrode structure (shown in FIG. 7). Due to the surface inhibition layer 40 is formed on the surface of metal gate layer 26, therefore, the Ta server as a metal gate layer 26 has a low resistivity and good thermal stability, especially with the nitrogen-containing RTP treatment.
  • According to above-mentioned, the [0028] dielectric layer 20 is utilized to improve the quality of gate electrode for their reasonable high dielectric constant, good thermal stability, and chemical stability. Furthermore, the metal gate layer 26 has low resistivity, good thermal and chemical stability to serve as a metal gate material, especially with nitrogen-containing RTP treatment such that the quality and reliability of gate electrode can be improved.
  • Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims. [0029]

Claims (27)

What is claimed is:
1. A method for fabricating a gate electrode, wherein said method comprising:
providing a substrate;
forming an interface diffusion barrier layer on said substrate;
forming a dielectric layer with a high dielectric constant on said interface diffusion barrier layer;
forming a metal gate layer on said dielectric layer; and
removing portion of said metal gate layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate.
2. The method according to claim 1, wherein the steps of forming said interface diffusion barrier layer comprises a first nitrogen-containing rapid thermal process.
3. The method according to claim 2, wherein said first nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.
4. The method according to claim 2, wherein the temperature of said first nitrogen-containing rapid thermal process is between 600° C. to 750° C.
5. The method according to claim 2, wherein the duration of said first nitrogen-containing rapid thermal process is between the 10 to 20 minutes.
6. The method according to claim 1, wherein the steps of said fabricating said gate electrode on said substrate further comprising:
performing a post-deposition annealing to said dielectric layer;
depositing a barrier layer on said dielectric layer and a metal gate layer on said barrier layer;
forming a photoresist layer on said metal gate layer; and
sequentially etching said metal gate layer, said barrier layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate.
7. The method according to claim 1, wherein material of said dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO2), hafnium dioxide (HfO2), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).
8. The method according to claim 1, wherein said dielectric layer with said high dielectric constant is about 10.
9. The method according to claim 6, further comprising a second nitrogen-containing rapid thermal process treatment on said gate electrode.
10. The method according to claim 9, wherein said second nitrogen-containing rapid thermal process comprises an ammonia rapid thermal process.
11. A method for fabricating a gate electrode, said method comprising:
providing a substrate;
treating said substrate by a first nitrogen-containing rapid thermal process to form an interface diffusion barrier layer thereon;
depositing a dielectric layer with a high dielectric constant on said interface diffusion barrier layer;
performing a post-deposition annealing process on said dielectric layer;
forming a barrier layer on said dielectric layer;
forming metal gate layer on said barrier layer;
forming a photoresist layer on said metal gate layer;
sequentially etching said metal gate layer, said barrier layer, said dielectric layer, and said interface diffusion barrier layer to form said gate electrode on said substrate; and
performing a second nitrogen-containing rapid thermal process on said gate electrode.
12. The method according to claim 11, wherein said first nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.
13. The method according to claim 11, wherein said dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO2), hafnium dioxide (HfO2), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).
14. The method according to claim 11, wherein said dielectric layer with said high dielectric constant is about 10.
15. The method according to claim 11, wherein said performing post-deposition annealing comprises a post-deposition annealing in nitrogen gas.
16. The method according to claim 11, wherein the material of said barrier layer comprises titanium nitride (TiN).
17. The method according to claim 11, wherein the material of said metal gate layer comprises tantalum (Ta).
18. The method according to claim 11, wherein said second nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.
19. A method for forming the gate electrode, said method comprising:
providing a substrate;
treating said substrate by a first ammonia rapid thermal process (NH3 RTP) to form an interface diffusion barrier layer on said substrate;
chemical vapor depositing a dielectric layer on said interface diffusion barrier layer, wherein the dielectric constant of said dielectric layer is about 10;
performing a post-deposition annealing in nitrogen gas on said dielectric layer;
chemical vapor depositing a titanium nitride layer on said dielectric layer;
chemical vapor depositing a tantalum layer on said tantalum layer;
forming a photoresist layer on said tantalum layer; and
sequentially etching said tantalum layer, said titanium nitride layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate; and
performing a second ammonia rapid thermal process (NH3 RTP) on said gate electrode to form a surface inhibition layer on the sidewall of said gate electrode.
20. The method according to claim 19, wherein dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO2), hafnium dioxide (HfO2), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).
21. The method according to claim 19, wherein the temperature of said first ammonia rapid thermal process (NH3 RTP) is between 600° C. to 750° C.
22. The method according to claim 19, wherein the duration of said first ammonia rapid thermal process (NH3 RTP) is between 10 to 20 minutes.
23. The method according to claim 19, wherein the temperature of said post-deposition annealing is between 700° C. to 900° C.
24. The method according to claim 19, wherein the duration of said post-deposition annealing is between 20 to 45 minutes.
25. The method according to claim 19, wherein the temperature of said second ammonia rapid thermal process is about 600° C.
26. The method according to claim 19, wherein the duration of said second ammonia rapid thermal process is about 20 minutes.
27. The method according to claim 19, wherein said surface inhibition layer comprises TaNx.
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