JPH0396273A - Complementary-type mis semiconductor device - Google Patents
Complementary-type mis semiconductor deviceInfo
- Publication number
- JPH0396273A JPH0396273A JP1233483A JP23348389A JPH0396273A JP H0396273 A JPH0396273 A JP H0396273A JP 1233483 A JP1233483 A JP 1233483A JP 23348389 A JP23348389 A JP 23348389A JP H0396273 A JPH0396273 A JP H0396273A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- diffused layer
- impurity diffused
- input
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 230000015556 catabolic process Effects 0.000 claims abstract description 12
- 230000000295 complement effect Effects 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、相補型Ｍ Ｉ Ｓ （ Ｍｅｔａｌ Ｉｎｓ
ｕｌａｔｏｒ Ｓｅｍ！ｃｏｎｄｕｃｔｏｒ ）半導体
装置に係り、特に、ラッチアップ耐性を高めた相補型Ｍ
ＩＳ半導体装置に関する．
［従来の技術］
相補型ＭＩＳ半導体装置においては、本質的にｐｎｐｎ
構造の寄生サイリスタが存在しているので、これによる
ラッチアップ現象が発生しやすくそのためその動作範囲
が制限されている．従来、このラッチアップ現象を抑制
するためにレイアウト上様々な提案がなされているが、
この種半導体装置においては高集積化、小型化の要請が
強いので、ラッチアップ対策としてチップサイズを大き
くするものはその採用が困難である．すなわち、素子の
微細化が進むにつれて、チップ上の面積をあまり占めな
い範囲でのラッチアップ対策が非常に重要となってきて
いる。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to complementary MIS (Metal Ins.
ulator Sem! conductor) related to semiconductor devices, especially complementary type M with improved latch-up resistance
Regarding IS semiconductor devices. [Prior Art] In complementary MIS semiconductor devices, essentially pnpn
Due to the presence of parasitic thyristors in the structure, latch-up phenomena are likely to occur due to this, which limits its operating range. In the past, various layout proposals have been made to suppress this latch-up phenomenon.
Since there is a strong demand for high integration and miniaturization in this type of semiconductor device, it is difficult to adopt a device that increases the chip size as a countermeasure against latch-up. That is, as elements become increasingly finer, measures against latch-up within a range that does not occupy much area on a chip are becoming extremely important.
従来の相補型ＭＩＳ半導体装置について、その平面図で
ある第３図（ａ）およびその断面図である第３図（ｂ）
を参照して説明する．第３図（ａ）、（ｂ）に示される
ように、ｐ型半導体基板１上には、ｎ＋型ソース領域３
Ｃ、ドレイン領域３ｂおよびゲート電極５ｂを有するｎ
チャネルＭＯＳトランジスタ（以下、ｎＭＯｓと記す）
Ｑｎが形或されており、また、ｐ型半導体基板１の表面
領域内に形成されたｎウェル領域２内には、ｐ１型ソー
ス領域４ａ、ドレイン領域４ｂおよびゲート電極５ａを
有するｐチャネルＭＯＳ｝ランジスタ（以下、ｐＭＯＳ
と記す）Ｑｐが形成されている．両ＭＯＳ｝ランジスタ
Ｑｐ．Ｑｎは、インバータ回路を楕戒するように金属配
線により接続される．すなわち、金属配線６ａによって
ｐＭＯｓＱｐのソース領域４ａとｎ＋型拡散領域３ａと
が電源電圧Ｖｃｃに接続され、金属配Ｍ６ｂによってｐ
ＭＯｓＱＰのドレイン領域４ｂとｎＭＯｓＱｎのドレイ
ン領域３ｂとが接続され、金属配線６ＣによってｎＭＯ
ｓＱｎのソース領域３Ｃは接地電位ＧＮＤに接続され、
金属配線６ｄによってｐＭＯＳＱｐのゲート電極５ａと
ｎＭＯｓＱｎのゲート電極５ｂとはｎ＋型ドレイン領域
３ｅに接続されている。また、入力端子であるパッド用
金属配線６ｅとインバータ回路を構成するＭＯＳ｝ラン
ジスタＱｐ，Ｑｎとの間に、ｎ＋型ドレイン領域３ｅ内
に形成された入力抵抗Ｒｉｎと、ｎ＋型ドレイン領域３
ｅ．ｎ＋型ンース領域３ｄおよび金属配線６ｃによって
接地電位に接続されたゲート電極５ｃ’を有するｎＭＯ
ｓＱｉｎとで楕戒される入力保護回路が設置されている
。Regarding a conventional complementary MIS semiconductor device, FIG. 3(a) is a plan view thereof, and FIG. 3(b) is a sectional view thereof.
This will be explained with reference to. As shown in FIGS. 3(a) and 3(b), an n+ type source region 3 is formed on the p-type semiconductor substrate 1.
C, n having a drain region 3b and a gate electrode 5b
Channel MOS transistor (hereinafter referred to as nMOS)
In addition, in the n-well region 2 formed in the surface region of the p-type semiconductor substrate 1, there is a p-channel MOS having a p1-type source region 4a, a drain region 4b, and a gate electrode 5a. transistor (hereinafter referred to as pMOS)
) Qp is formed. both MOS} transistor Qp. Qn is connected by metal wiring so as to overlap the inverter circuit. That is, the source region 4a and the n+ type diffusion region 3a of the pMOSQp are connected to the power supply voltage Vcc by the metal wiring 6a, and the pMOSQp is connected to the power supply voltage Vcc by the metal wiring M6b.
The drain region 4b of MOsQP and the drain region 3b of nMOsQn are connected, and the nMO
The source region 3C of sQn is connected to the ground potential GND,
The gate electrode 5a of the pMOSQp and the gate electrode 5b of the nMOSQn are connected to the n+ type drain region 3e by a metal wiring 6d. In addition, an input resistor Rin formed in the n+ type drain region 3e and an input resistor Rin formed in the n+ type drain region 3e between the pad metal wiring 6e which is the input terminal and the MOS transistors Qp and Qn forming the inverter circuit.
e. nMO having an n+ type source region 3d and a gate electrode 5c' connected to the ground potential by a metal wiring 6c.
An input protection circuit that is protected by sQin is installed.
斯かる相補型ＭＩＳ半導体装置においては、第３図（ｂ
）に等価回路で示す回路が形威されており、ラッチアッ
プは、電源電圧Ｖｃｏにつながるｎウェル領域２内のｐ
＋型ソース領域４ａと電源電圧Ｖ。。にｎ＋型拡散領域
３ａを介してつながるｎウェル領域２とｐ型半導体基板
１とからｎ４威されるｐｎｐバイボーラトランジスタＴ
ｒ １と、ｎウェル領域２とｐ型半導体基板１と接地
電位ＧＮＤにつながるｎ１型ソース領域３ｃとから横戒
されるｎｐｎバイボーラトランジスタＴｒ２とが何らか
のトリガーを受けて導通状態になったときに発生する．
［発明が解決しようとする課題］
上述した従来の相補型ＭＩＳ半導体装置は、入力端子に
静電気等の外部ノイズが印加された場合に簡単にラッチ
アップ状態に陥いるという欠点があった．そのメカニズ
ムを以下に示す．第３図（ｂ）に示すように、入力端子
に外部からノイズが印加されると、すなわちパッド用金
属配線６ｅにノイズが印加されると、まずｎ１型ドレイ
ン領域３ｅにノイズが加わる．この際に、ｎ１型ドレイ
ン領域３ｅ−ｐ型半導体基板ｌ間の降服電圧ＢＶＪに比
べ、ｎＭＯｓＱｉｎのドレイン領域３ｅ−ソース領域３
ｄ間の導通開始電圧ＢＶｏｓが高い場合、ｎ＋型ドレイ
ン領域３ｅに印加されたノイズレベルが降服電圧ＢＶｊ
を超えると、ｎ“型ドレイン領域３ｅからｐ型半導体基
板１へ電流が流れる．
これを第４図に示す等価回路を用いて説明すると、前述
のように入力端子Ｐに高い外部ノイズが印加されると、
ドレイン領域３ｅ一半導体基板１間で形威されるダイオ
ードＤが逆方向に導通状態となり、電流Ｉｊが流れる．
その結果、ｐ型半導体基板ｌの抵抗Ｒ ｓｕｂの存在に
より節点■の電位が上昇し、トランジスタＴｒ２が導通
して、このトランジスタ内を電流Ｉ２が流れる。このた
めｎウェル領域２の抵抗Ｒｗｅｌｌの端子の節点■の電
位が下降し、トランジスタＴｒｉが導通し、電流■１が
流れる．その結果、トランジスタＴｒｉとＴｒ２からな
るループに正帰還がかかり、トランジスタＴｒｉとＴ
ｒ ２とで構成されるサイリスタが導通し（ラッチアッ
プ現象が起こり）、電源一接地端子間に大電流が流れ、
最悪の場合デバイスが破壊する．
［課題を解決するための千段］
本発明による相補型ＭＩＳ半導体装置は、入力端子に接
続された入力保護抵抗を構戒する第１の不純物拡散層と
、該第ｌの不純物拡散層およびこれと近接して形成され
接地電位に接続される第２の不純物拡散層を含んで構戒
される入力保護素子とを有するものであって、前記第１
の不純物拡散層と半導体基板との間の接合の降服電圧は
、前記入力保護素子の導通開始電圧より高く設定されて
いる．
［実施例］
次に、本発明の実施例について図面を参照して説明する
．
第１図は、本発明の一実施例を示す断面図であって、同
図において、第３図の従来例と同一の部分には同一の参
照番号が付されているので重複した説明は省略する．こ
の実施例の第３図に示される従来例と相違する点は、本
実施例においては、入力保護回路におけるｎＭＯｓＱｉ
ｎのゲート電極５Ｃのゲート長が従来例のそれより短か
くなされており、そして、このトランジスタの導通開始
電圧ＢＶｏｓが、ｎ＋型ドレイン領域３ｅ−ｐ型半導体
基板間の降服電圧ＢＶＪより低く設定されている点であ
る．
次に、本発明の動作原理について第２図を参照して説明
する．まず、入力端子Ｐに外部ノイズが印加されると、
ｎ＋型ドレイン領域３ｅ一半導体基板間の降服電圧ＢＶ
ｊ （例えば２０Ｖ）より、ｎ Ｍ Ｏ Ｓ Ｑ ｉｎ
の導通開始電圧ＢＶｏｓ（例えば１５Ｖ）の方が低く設
定されているために、ｎＭＯｓＱｉｎの方が先に導通し
て、このトランジスタ内を電流Ｉ。Ｓが流れる．したが
って、第５図に示した場合のように、基板電流Ｉｊが流
れることはなくなり、トランジスタＴｒ２は導通するこ
とはなくラッチアップ現象は生じない．また、入力電圧
がさらに上昇して降服電圧ＢＶＪを超えても、ｎＭＯＳ
Ｑｉｎのサイズを適当な大きさにすることにより、Ｑｉ
ｎの導通抵抗Ｒｌ）Ｓ、ドレイン領域３ｅとｐ型半導体
基板１との接合の導通抵抗ＲＪ，ｐ型半導体基板抵抗Ｒ
ｓｕｂとの関係を、
Ｒ ａｓ＜ Ｒ Ｊ ＋ Ｒ ｓｕｂ
の条件を満足するようにすれば、
Ｉｏｓ＞ＩＪ
となり、外部ノイズによるｐ型半導体基板１への電流Ｉ
Ｊを小さく抑えることができる．したがって、この場合
にもラッチアップ境象のトリガーとなるｐ型半導体基板
への電流Ｉｊが小さいため、ラッチアップ現象は大きく
抑制される．なお、上記実施例では、ｎＭＯｓＱｉｎの
ゲート長を短くすることによりこのトランジスタの導通
開始電圧ＢＶｏｓを接合降服電圧ＢＶＪより低く設定し
ていたが，これに替えて、ｎ“型ドレイン領域３ｅの不
純物濃度を下げることにより、上記条件を達成できるよ
うにしてもよい．いずれにしても、本発明によれば、ラ
ッチアップ防止のために格別なスペースを消費すること
なく確実にその目的を達成することができる．
［発明の効果］
以上説明したように、本発明による相補型ＭＩＳ半導体
装置は、入力端子に接続された、第１の不純物拡散層で
構成された入力保護抵抗と、前記第１の不純物拡散層お
よび接地電位に接続された第２の不純物拡散層を含む入
力保護素子とを備えるものであって、前記入力保護素子
の導通開始電圧は、前記第１の不純物拡散層と半導体基
板との間の降服電圧より低く設定したものであるので、
本発明によれば、入力端子に印加される外部ノイズを入
力保護素子により接地電位へ引き落すことができる．し
たがって、本発明によれば、第１の不純物拡散層の接合
降服による基板電流を生じさせないかあるいはこれを僅
少なものとすることができるので、寄生トランジスタを
導通させないようにすることができ、ラッチアップ現象
を大きく抑制することができる．そして、このような効
果はチップ面積の拡大を伴うことなくもたらされるもの
であるので、本発明は半導体装置の高集積化に寄与する
ところ大である．In such a complementary MIS semiconductor device, as shown in FIG.
) is shown as an equivalent circuit, and the latch-up occurs in the p well region 2 connected to the power supply voltage Vco.
+ type source region 4a and power supply voltage V. . A pnp bibolar transistor T is connected to an n-well region 2 and a p-type semiconductor substrate 1 through an n+-type diffusion region 3a.
When r1, the npn bibolar transistor Tr2, which is connected to the n-well region 2, the p-type semiconductor substrate 1, and the n1-type source region 3c connected to the ground potential GND, receive some trigger and become conductive. Occur. [Problems to be Solved by the Invention] The conventional complementary MIS semiconductor device described above has the disadvantage that it easily falls into a latch-up state when external noise such as static electricity is applied to the input terminal. The mechanism is shown below. As shown in FIG. 3(b), when noise is applied from the outside to the input terminal, that is, when noise is applied to the pad metal wiring 6e, the noise is first applied to the n1 type drain region 3e. At this time, compared to the breakdown voltage BVJ between n1 type drain region 3e and p type semiconductor substrate l, the drain region 3e and source region 3 of nMOsQin
When the conduction start voltage BVos between d and d is high, the noise level applied to the n+ type drain region 3e becomes the breakdown voltage BVj
, a current flows from the n" type drain region 3e to the p type semiconductor substrate 1. To explain this using the equivalent circuit shown in FIG. 4, as mentioned above, high external noise is applied to the input terminal P. Then,
The diode D formed between the drain region 3e and the semiconductor substrate 1 becomes conductive in the opposite direction, and a current Ij flows.
As a result, the potential at the node (2) increases due to the presence of the resistor R sub of the p-type semiconductor substrate l, the transistor Tr2 becomes conductive, and a current I2 flows through this transistor. Therefore, the potential at the node (2) at the terminal of the resistor Rwell in the n-well region 2 drops, the transistor Tri becomes conductive, and the current (1) flows. As a result, positive feedback is applied to the loop consisting of transistors Tri and Tr2, and transistors Tri and T
The thyristor consisting of r2 conducts (a latch-up phenomenon occurs), and a large current flows between the power supply and ground terminals,
In the worst case, the device will be destroyed. [A Thousand Steps to Solve the Problems] A complementary MIS semiconductor device according to the present invention includes a first impurity diffusion layer that prevents an input protection resistor connected to an input terminal, the first impurity diffusion layer, and the second impurity diffusion layer. and an input protection element including a second impurity diffusion layer formed adjacent to the first impurity diffusion layer and connected to the ground potential, the input protection element comprising:
The breakdown voltage of the junction between the impurity diffusion layer and the semiconductor substrate is set higher than the conduction start voltage of the input protection element. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing one embodiment of the present invention. In the same figure, the same parts as in the conventional example shown in FIG. do. This embodiment is different from the conventional example shown in FIG.
The gate length of the n gate electrode 5C is made shorter than that of the conventional example, and the conduction start voltage BVos of this transistor is set lower than the breakdown voltage BVJ between the n+ type drain region 3e and the p type semiconductor substrate. This is the point. Next, the operating principle of the present invention will be explained with reference to FIG. First, when external noise is applied to the input terminal P,
Breakdown voltage BV between n+ type drain region 3e and semiconductor substrate
j (for example, 20V), n M O S Q in
Since the conduction start voltage BVos (for example, 15V) is set lower, the nMOSQin becomes conductive first, and a current I flows through this transistor. S flows. Therefore, as in the case shown in FIG. 5, the substrate current Ij no longer flows, the transistor Tr2 does not become conductive, and no latch-up phenomenon occurs. Also, even if the input voltage increases further and exceeds the breakdown voltage BVJ, the nMOS
By setting the size of Qin to an appropriate size, Qi
n conduction resistance Rl)S, conduction resistance RJ of the junction between drain region 3e and p-type semiconductor substrate 1, p-type semiconductor substrate resistance R
If the relationship with sub is made to satisfy the condition Ras<R J + R sub, Ios>IJ, and the current I to the p-type semiconductor substrate 1 due to external noise is
J can be kept small. Therefore, in this case as well, since the current Ij flowing to the p-type semiconductor substrate, which triggers the latch-up phenomenon, is small, the latch-up phenomenon is largely suppressed. In the above embodiment, the conduction start voltage BVos of this transistor was set lower than the junction breakdown voltage BVJ by shortening the gate length of the nMOSQin, but instead of this, the impurity concentration of the n" type drain region 3e is The above conditions may be achieved by lowering the latch-up.In any case, according to the present invention, the purpose can be reliably achieved without consuming special space for latch-up prevention. [Effects of the Invention] As explained above, the complementary MIS semiconductor device according to the present invention includes an input protection resistor configured of a first impurity diffusion layer connected to an input terminal, and a first impurity diffusion layer connected to an input terminal. and an input protection element including a diffusion layer and a second impurity diffusion layer connected to a ground potential, wherein the conduction start voltage of the input protection element is equal to the voltage between the first impurity diffusion layer and the semiconductor substrate. It is set lower than the breakdown voltage between
According to the present invention, external noise applied to the input terminal can be reduced to ground potential by the input protection element. Therefore, according to the present invention, the substrate current due to junction breakdown of the first impurity diffusion layer is not generated or can be made small, so that the parasitic transistor can be prevented from conducting, and the latch The up phenomenon can be greatly suppressed. Since such effects are achieved without increasing the chip area, the present invention greatly contributes to higher integration of semiconductor devices.
第１図は、本発明の一実施例を示す断面図、第２図は、
その等価回路図、第３図（ａ）は、従来例を示す平面図
、第３図（ｂ）は、その断面図、第４図は、その等価回
路図である．
１・・・ρ型半導体基板、 ２・・・ｎウエル領域、
３ａ・・・ｎ＋型拡散領域、 ３ｂ、３ｅ・・・ｎ＋
型ドレイン領域、 ３Ｃ、３ｄ・・・ｎ＋型ソース
領域、 ４ａ・・・ｐ＋型ソース領域、 ４ｂ・・
・ｐ１型トレイン領域、 ５ａ、５ｂ、５Ｃ、
５ｃ＝−・ゲート電極、 ６ａ，６ｂ、６Ｃ、６ｄ、
６ｅ・・・金属配線、 Ｄ・・・領域３ｅ一基板１間
の寄生ダイオード、 Ｑｉｎ・・・入力保護素子であ
るｎチャネルＭＯＳ｝ランジスタ、 Ｑｎ・・・イン
バータを楕戒するｎチャネルＭＯＳトランジスタ、
Ｑｐ・・・インバータを構成するｐチャネルＭＯＳトラ
ンジスタ、 Ｔｒｌ・・・寄生ｐｎｐバイボーラトラ
ンジスタ、 Ｔ ｒ ２・・・寄生ｎｐｎバイボーラ
トランジスタ、 Ｒｗｅｌｌ・・・ｎウエル領域抵抗
、 Ｒ ｓｕｂ・・・ｐ型半導体基板抵抗、Ｒｊ・・
・ｎ＋型ドレイン領域３ｅ−ｐ型半導体基板１間接合の
逆方向導通抵抗．FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention.
3(a) is a plan view showing a conventional example, FIG. 3(b) is a sectional view thereof, and FIG. 4 is an equivalent circuit diagram thereof. 1... ρ-type semiconductor substrate, 2... n-well region,
3a...n+ type diffusion region, 3b, 3e...n+
type drain region, 3C, 3d...n+ type source region, 4a...p+ type source region, 4b...
・p1 type train region, 5a, 5b, 5C,
5c=-・gate electrode, 6a, 6b, 6C, 6d,
6e...metal wiring, D...parasitic diode between region 3e and substrate 1, Qin...n-channel MOS transistor which is an input protection element, Qn...n-channel MOS transistor that protects the inverter,
Qp...p channel MOS transistor constituting the inverter, Trl...parasitic pnp bibolar transistor, Tr2...parasitic npn bibolar transistor, Rwell...n well region resistance, Rsub...p type semiconductor substrate resistance, Rj...
・Reverse conduction resistance of the junction between the n+ type drain region 3e and the p type semiconductor substrate 1.
Claims (1)
子とｎチャネル型ＭＩＳ半導体素子とが形成され、前記
ｐチャネルおよびｎチャネルＭＩＳ半導体素子が前記半
導体基板の表面領域に形成された第１の不純物拡散層を
介して入力端子に接続され、前記第１の不純物層は接地
電位に接続された第２の不純物拡散層とともに入力保護
素子を構成している相補型ＭＩＳ半導体装置において、
前記第１の不純物拡散層と前記半導体基板との間の降服
電圧は、前記入力保護素子の導通開始電圧より高いこと
を特徴とする相補型ＭＩＳ半導体装置。A p-channel MIS semiconductor element and an n-channel MIS semiconductor element are formed on a semiconductor substrate of one conductivity type, and the p-channel and n-channel MIS semiconductor elements include a first impurity formed in a surface region of the semiconductor substrate. In a complementary MIS semiconductor device connected to an input terminal via a diffusion layer, the first impurity layer constitutes an input protection element together with a second impurity diffusion layer connected to a ground potential,
A complementary MIS semiconductor device, wherein a breakdown voltage between the first impurity diffusion layer and the semiconductor substrate is higher than a conduction start voltage of the input protection element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1233483A JPH0396273A (en) | 1989-09-08 | 1989-09-08 | Complementary-type mis semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1233483A JPH0396273A (en) | 1989-09-08 | 1989-09-08 | Complementary-type mis semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0396273A true JPH0396273A (en) | 1991-04-22 |
Family
ID=16955717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1233483A Pending JPH0396273A (en) | 1989-09-08 | 1989-09-08 | Complementary-type mis semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0396273A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5771179A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Input protective circuit device |
| JPS61296773A (en) * | 1985-06-26 | 1986-12-27 | Toshiba Corp | Input protective circuit |
-
1989
- 1989-09-08 JP JP1233483A patent/JPH0396273A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5771179A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Input protective circuit device |
| JPS61296773A (en) * | 1985-06-26 | 1986-12-27 | Toshiba Corp | Input protective circuit |
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