JPH0383396A - Multilayer printed circuit board - Google Patents
Multilayer printed circuit boardInfo
- Publication number
- JPH0383396A JPH0383396A JP21847889A JP21847889A JPH0383396A JP H0383396 A JPH0383396 A JP H0383396A JP 21847889 A JP21847889 A JP 21847889A JP 21847889 A JP21847889 A JP 21847889A JP H0383396 A JPH0383396 A JP H0383396A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ground
- multilayer printed
- line
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 48
- 239000000758 substrate Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
多層プリント配線板に関し、
層数減少を図りながら、基板製作コストや基板設計の自
由度拡大を図り得る多層プリント配線板を提供すること
を目的とし、
電源層及び接地層を同一の平面内に併設した内層を少な
くとも１つ有するよう構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a multilayer printed wiring board, and aims to provide a multilayer printed wiring board that can reduce the number of layers while increasing the board manufacturing cost and the degree of freedom in board design. It is configured to have at least one inner layer in which a ground layer and a ground layer are provided in the same plane.
本発明は、電気絶縁性基板の外層の他に、内層にも電気
良導体金属による配線図形を有するいわゆる多層プリン
ト配線板に関する。The present invention relates to a so-called multilayer printed wiring board having wiring patterns made of electrically conductive metal not only on the outer layer but also on the inner layer of an electrically insulating substrate.
電子機器の急速な高精度・高密度高信頼性化への要求を
満足させるため、絶縁体（又は誘電体）と導電体とを層
状に積層形威し、各導電層間の電気的接続を行い、１つ
のシステムにまとめあげたいわゆる多層プリント配線板
が多用されている。In order to satisfy the rapid demand for high precision, high density, and high reliability in electronic devices, insulators (or dielectrics) and conductors are laminated in layers, and electrical connections are made between each conductive layer. , so-called multilayer printed wiring boards that are integrated into one system are often used.
例えば、４層レベルでは電源層及び接地（アース）層の
２層をそれぞれ内部に、信号線層を外部両面に配置する
積層構成が標準となっている。また、高密度化に対応す
る６層及び８層レベルにおいても同様である。For example, at a four-layer level, a laminated structure in which two layers, a power supply layer and a ground layer are arranged inside each layer, and signal line layers are arranged on both outside surfaces, is standard. The same applies to the 6-layer and 8-layer levels that correspond to higher density.
しかるに、基板製作コストやパターンレイアウト設計等
を考慮すると、上記従来の積層構成の如く常に電源層と
接地層とを別個独立の層として積層するのは必ずしも得
策ではない場合が起きる可能性がある。However, in consideration of substrate manufacturing costs, pattern layout design, etc., it may not always be a good idea to always laminate the power supply layer and the ground layer as separate and independent layers as in the conventional laminate structure described above.
そこで、本発明においては基板の積層構造における層数
の減少を図りながら、同時に基板のコスト及び設計の自
由度等の改善が可能な新奇な基板構造を提供することを
課題とする。Therefore, an object of the present invention is to provide a novel substrate structure that can reduce the number of layers in the laminated structure of the substrate, while at the same time improving the cost and freedom of design of the substrate.
〔課題を解決するための手段］
上記課題を解決するために本発明によれば、電源層及び
接地層を同一の平面内に併設した内層を少なくとも１つ
有することを構成上の特徴とする。[Means for Solving the Problems] In order to solve the above problems, the present invention is characterized in that it has at least one inner layer in which a power supply layer and a ground layer are provided in the same plane.
電源層と接地層を同一平面内に併設するため、−層の内
層で済む。従って、本来的に必要であった他の一層が全
く不要となり、その分のコストが少なくとも低減し、あ
るいはそれを他の用途に使用できる。Since the power supply layer and the ground layer are placed on the same plane, only the inner layer of the - layer is required. Therefore, the other layer that was originally required is completely unnecessary, and the cost is at least reduced by that amount, or it can be used for other purposes.
以下、図示実施例に基づき本発明を説明する。 The present invention will be explained below based on illustrated embodiments.
第１図は、本発明に係る多層プリント配線板の基本原理
を説明するための、一実施例の表層を捲り取ってそのレ
イアウトが見えるようにされた電源層及び接地層が併設
された内層の平面図である。FIG. 1 shows an inner layer with a power supply layer and a ground layer, the surface layer of which is turned over to reveal the layout of an embodiment, in order to explain the basic principle of a multilayer printed wiring board according to the present invention. FIG.
基板内層１には、いわゆるスルーホール・コネクション
のためあるいは部品実装のためのスルーホール２が複数
個形成され、これらのスルーホール２はＸＹ直交座標系
に基づき、２．５４＋＋＋ｍピッチの基本格子間隔で規
則正しく配置されている。A plurality of through holes 2 for so-called through hole connections or component mounting are formed in the inner layer 1 of the board, and these through holes 2 are arranged at a basic lattice spacing of 2.54+++m pitch based on the XY orthogonal coordinate system. They are arranged regularly.
また、この内層１上には、本発明に従い電源層及び接地
層が併設されるが、本実施例の場合、例えば電源ライン
（層〉をＡ１接地ライン（層）をＢとすると、両ライン
Ａ、Ｂは横一列に並ぶスルーホール２に沿いスルーホー
ル間の中央を所定の輻で略直線的に平行に延び且つ互い
違いに位置するように配置されている。そして、各電源
ラインＡは左方側で、各接地ラインＢは右方側でそれぞ
れ一体化接続されている。Further, on this inner layer 1, a power supply layer and a ground layer are provided together according to the present invention, but in the case of this embodiment, for example, if the power supply line (layer) is A1 and the ground line (layer) is B, both lines A , B are arranged so as to extend substantially linearly parallel to each other at a predetermined radius in the center between the through holes along the through holes 2 arranged in a row horizontally, and to be positioned alternately. On the side, each ground line B is integrally connected on the right side.
このように、両ラインＡ・Ｂを平行に（交互に〉配設す
るのは、基板外側に実装された部品のビン足が挿入され
るスルーホールに両ラインＡ・Ｂのいずれかを接続する
パターンレイアウトにする場合に簡便に対処できるから
である。このことは、以下の第２図に関する説明により
更に明らかになろう。なお、言うまでもないが第１図に
おいて電源層及び接地層がＡ、Ｂ相互に逆であっても差
し支えない。また、本図のレイアウトにおいては電源ラ
インＡ及び接地ラインＢのいずれもスルーホール２と接
続されているようには描いていない。The reason for arranging both lines A and B in parallel (alternately) in this way is to connect either line A or B to the through hole into which the pin feet of the components mounted on the outside of the board are inserted. This is because it can be easily handled when creating a pattern layout.This will become clearer from the explanation regarding Figure 2 below.It goes without saying that in Figure 1, the power layer and ground layer are A and B. They may be reversed. In addition, in the layout of this figure, neither the power line A nor the ground line B is depicted as being connected to the through hole 2.
ここで、実際に基板外側に所定のＩＣが実装された場合
のその内層パターンの一例を第２図に示すと、本図のＩ
Ｃｌ３は図示しない基板外面に実装されたものであるた
め想像（二点１ｉｌ）線で描いてあり、これは例えばロ
ジック・レベル反転用のゲートを具えた７４０４等のい
わゆるロジックＩＣである。Here, an example of the inner layer pattern when a predetermined IC is actually mounted on the outside of the board is shown in Fig. 2.
Cl3 is drawn with an imaginary line (two points 1il) because it is mounted on the outer surface of the substrate (not shown), and is a so-called logic IC such as 7404, which is equipped with a gate for logic level inversion.
このようなりＩＰタイプＩＣｌ３は、図で向かって下方
側の左から右に１番から７番の７個のビン足を有し、さ
らに上方側の右から左に８番から１４番の７個のピン足
を有する。この１４個のくその断面が示される〉ピン足
のうち少なくとも７番ピン１５ｇ及び１４番ビン１５ｎ
は、ＩＣｌ３を作動させるために接地ラインＢ及び電源
ライン八にそれぞれ電気的に接続されている必要がある
。このため本実施例においては、それぞれ近傍の電源ラ
イン八及び接地ラインＢから各ビン１５ｎ・１５ｇが挿
入されたスルーホール１２ｎ 、 １２ｇに向かってそ
れらが上方側に延長・突設され、接地ラインＡ及び電源
ラインＢとスルーホール１２ｎ、１２ｇとがそれぞれ一
体的に導通接続される。In this way, the IP type ICl3 has 7 bin legs numbered 1 to 7 from left to right on the lower side in the figure, and further 7 bin legs numbered 8 to 14 from right to left on the upper side. It has a pin foot. A cross section of these 14 pieces is shown> Among the pin legs, at least the 7th pin 15g and the 14th bottle 15n
must be electrically connected to ground line B and power line 8, respectively, in order to operate ICl3. Therefore, in this embodiment, the power line 8 and the ground line B are extended and protruded upward toward the through holes 12n and 12g into which the bottles 15n and 15g are inserted, respectively, and the ground line A The power supply line B and the through holes 12n and 12g are each integrally electrically connected.
このように、第１図の実際の例を挙げて説明した第２図
の実施例の内層レイアウトによれば、同一層に電源ライ
ンと接地ラインとを同居させて適切に両者を配置したこ
とにより、確実且つ容易な電源供給及びアース接続が可
能となり、同時に基板製作コスト低減、部品実装量の拡
大、パターンレイアウト設計の自由度拡大等の様々の効
果が得られる。In this way, according to the inner layer layout of the embodiment shown in FIG. 2, which was explained using the actual example shown in FIG. , it becomes possible to provide a reliable and easy power supply and ground connection, and at the same time, various effects such as reduction in board manufacturing cost, increase in the amount of components to be mounted, and increased freedom in pattern layout design can be obtained.
〔発明の効果〕
以上の如く本発明によれば、実質的な層数の減少により
、基板製作コストの低減が図れ、また、基板設計の自由
度等が拡大する。[Effects of the Invention] As described above, according to the present invention, by substantially reducing the number of layers, it is possible to reduce the cost of manufacturing the board, and to increase the degree of freedom in board design.
第１図は本発明に係る多層プリント配線板の内層の一実
施例の平面図、
第２図は内層の別の実施例の平面図である。
１・・・内層、 ２・・・スルーホール、
Ａ・・・電源ライン（層）、Ｂ・・・接地ライン（層）
、１１・・・内層、１２・・・スルーホール。FIG. 1 is a plan view of one embodiment of the inner layer of a multilayer printed wiring board according to the present invention, and FIG. 2 is a plan view of another embodiment of the inner layer. 1...Inner layer, 2...Through hole,
A...Power line (layer), B...Ground line (layer)
, 11...inner layer, 12... through hole.
Claims (1)
設した内層（１，１１）を少なくとも１つ有することを
特徴とする多層プリント配線板。1. A multilayer printed wiring board characterized by having at least one inner layer (1, 11) in which a power supply layer (A) and a ground layer (B) are provided in the same plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21847889A JPH0383396A (en) | 1989-08-28 | 1989-08-28 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21847889A JPH0383396A (en) | 1989-08-28 | 1989-08-28 | Multilayer printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0383396A true JPH0383396A (en) | 1991-04-09 |
Family
ID=16720561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21847889A Pending JPH0383396A (en) | 1989-08-28 | 1989-08-28 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0383396A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06181389A (en) * | 1992-12-11 | 1994-06-28 | Nec Corp | Multilayer printed-wiring board |
| JP2008192740A (en) * | 2007-02-02 | 2008-08-21 | Shinko Electric Ind Co Ltd | Wiring substrate, manufacturing method thereof, and semiconductor device |
-
1989
- 1989-08-28 JP JP21847889A patent/JPH0383396A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06181389A (en) * | 1992-12-11 | 1994-06-28 | Nec Corp | Multilayer printed-wiring board |
| JP2008192740A (en) * | 2007-02-02 | 2008-08-21 | Shinko Electric Ind Co Ltd | Wiring substrate, manufacturing method thereof, and semiconductor device |
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