JPH0380544A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0380544A JPH0380544A JP21630189A JP21630189A JPH0380544A JP H0380544 A JPH0380544 A JP H0380544A JP 21630189 A JP21630189 A JP 21630189A JP 21630189 A JP21630189 A JP 21630189A JP H0380544 A JPH0380544 A JP H0380544A
- Authority
- JP
- Japan
- Prior art keywords
- collector
- region
- insulating film
- substrate
- isolation insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 22
- 241000238557 Decapoda Species 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 210000004709 eyebrow Anatomy 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 241000721047 Danaus plexippus Species 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔概要〕 バイポーラトランジスタを有する半導体装置に関し。[Detailed description of the invention] 〔overview〕 Regarding a semiconductor device having a bipolar transistor.
埋込領域を有しない新規の構造を提案して、バイポーラ
トランジスタの動作速度を向上させることを目的とし。We aim to improve the operating speed of bipolar transistors by proposing a new structure without buried regions.
表面に段差を持つ基板上に、コレクタ領域と素子分離絶
縁膜とコレクタ引出領域とを有し、コレクタ領域は段差
下の基板表面に接続する一導電型半導体層からなり、内
部にその表面より順次一導電型エミッタ領域、・反対導
電型ベース領域が形成されており、素子分離絶縁膜はコ
レクタ領域の周縁に接して段差に沿って基板表面に形成
されており、コレクタ引出領域はコレクタ領域の側面に
接して段差下の素子分離絶縁膜上に形成された一導電型
半導体層からなるように構成する。A substrate with a step on its surface has a collector region, an element isolation insulating film, and a collector lead-out region. An emitter region of one conductivity type and a base region of an opposite conductivity type are formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed on the side surface of the collector region. The structure is made up of a semiconductor layer of one conductivity type formed on the element isolation insulating film in contact with and under the step.
本発明はバイポーラトランジスタを有する半導体装置に
関する。The present invention relates to a semiconductor device having a bipolar transistor.
バイポーラトランジスタは高速集積回路の構成素子とし
て広く用いられている。Bipolar transistors are widely used as components of high speed integrated circuits.
バイポーラトランジスタの基本構造は周知のように基板
上に高濃度埋込領域を形成し、その上にコレクタ領域と
なるエビ層を基板上全面に形成し。As is well known, the basic structure of a bipolar transistor is to form a highly doped buried region on a substrate, and then form a shrimp layer, which will become a collector region, over the entire surface of the substrate.
埋込領域上のエビ層内に順次ベース領域、エミッタ領域
を形成した構造である。It has a structure in which a base region and an emitter region are sequentially formed in the shrimp layer above the buried region.
第３図は従来例によるバイポーラトランジスタの断面図
である。FIG. 3 is a sectional view of a conventional bipolar transistor.
図において、２１はｐ型の半導体基板、２２はｎ１型の
高不純物濃度埋込領域、２３はｎ型エピタキシャル戒長
層でコレクタを構成し、２４はｐ型の素子分離領域、２
５はｐ型の不純物導入層でベースを構威し、２６はｎ０
型の不純物導入層でエミッタを構威し、２７はｎ３型の
コレクタ電極引出し領域、２８゜２９、３０は導電層よ
りなり、それぞれコレクタ、ベース、工ξツタ電極を構
威し、３１はフィールド絶縁層である。In the figure, 21 is a p-type semiconductor substrate, 22 is an n1-type buried region with high impurity concentration, 23 is an n-type epitaxial layer forming a collector, 24 is a p-type element isolation region, 2
5 is a p-type impurity-introduced layer that forms the base, and 26 is n0.
A type impurity-introduced layer constitutes an emitter, 27 is an n3 type collector electrode extraction region, 28, 29, and 30 are conductive layers, each forming a collector, a base, and an ivy electrode, and 31 is a field. It is an insulating layer.
このような構造のトランジスタにおいては、ベース電極
２９と工ξツタ電極３０間の絶縁距離を確保するため、
ベース領域２５はエミッタ領域２６よりかなり大きくし
なければならない。しかしトランジスタ作用にあずかる
動作領域はエミッタ領域２６の直下の領域のみで、それ
以外の領域はベース電極引出し用のものであり、その大
きさはできるだけ小さいことが望ましい。In a transistor having such a structure, in order to ensure an insulating distance between the base electrode 29 and the ivy electrode 30,
Base region 25 must be significantly larger than emitter region 26. However, the operating region that takes part in the transistor action is only the region immediately below the emitter region 26, and the other region is for drawing out the base electrode, and it is desirable that the size of the region be as small as possible.
従来例によるバイポーラトランジスタにおいては、動作
領域を機能的に必要とする大きさより大きくしなければ
ならず、集積度を向上する制約となり、さらに動作速度
を制限するという欠点があった。Conventional bipolar transistors have disadvantages in that the operating area must be made larger than functionally necessary, which limits the degree of integration and further limits the operating speed.
近年、デバイスの高速化、高集積化の要請によりベース
の引き出し方法については種々な工夫がなされ、多くの
提案がなされている。In recent years, in response to demands for higher speed and higher integration of devices, various methods of extracting the base have been devised and many proposals have been made.
コレクタの引き出しについては、埋込領域から基板表面
に引き出しているのが一般的である。The collector is generally drawn out from the buried region to the substrate surface.
コレクタの引き出しに埋込領域を用いた場合はコレクタ
の寄生容量が大きく、コレクタ抵抗は埋込領域を経由す
る分だけ大きくなるため、素子特性を阻害していた。When a buried region is used to lead out the collector, the parasitic capacitance of the collector is large, and the collector resistance increases by the amount that passes through the buried region, which impairs device characteristics.
本発明は埋込領域を有しない新規の構造を提案して、バ
イポーラトランジスタの動作速度を向上させることを目
的とする。The present invention aims to improve the operating speed of bipolar transistors by proposing a new structure without buried regions.
上記課題の解決は９表面に段差を持つ基板上に。 The above problem was solved on a substrate with steps on the surface.
コレクタ領域と素子分離絶縁膜とコレクタ引出領域とを
有し、コレクタ領域は段差下の基板表面に接続する一導
電型半導体層からなり、内部にその表面より順次一導電
型エミッタ領域２戻対導電型ベース領域が形成されてお
り、素子分離絶縁膜はコレクタ領域の周縁に接して段差
に沿って基板表面に形成されており、コレ−フタ引出領
域はコレクタ領域の側面に接して段差下の素子分離絶縁
膜上に形成された一導電型半導体層からなる半導体装置
にまり達成される。It has a collector region, an element isolation insulating film, and a collector lead-out region, and the collector region is made of a one-conductivity type semiconductor layer connected to the substrate surface under the step, and one-conductivity type emitter region 2 is returned to the inside from the surface in order. A mold base region is formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed in contact with the side surface of the collector region to protect the elements below the step. This is achieved in a semiconductor device consisting of a semiconductor layer of one conductivity type formed on an isolation insulating film.
本発明は、埋込領域がなくコレクタ領域の側面から直接
コレクタを引き出しているためコレクタ抵抗を低減し、
更にコレクタ引き出し領域が厚い分離絶縁膜上にあるた
めコレクタの寄生容量を低減して、素子の高速化をはか
ったものである。The present invention has no embedded region and draws out the collector directly from the side of the collector region, reducing collector resistance.
Furthermore, since the collector lead-out region is located on a thick isolation insulating film, the parasitic capacitance of the collector is reduced, thereby increasing the speed of the device.
第１図は本発明の一実施例を説明する一部断面を示す斜
視図である。FIG. 1 is a partially sectional perspective view illustrating an embodiment of the present invention.
図において、ｌはｐ−Ｓｔ基板、 ＩＣはチャネルカッ
ト領域、２はコレクタ領域でｎ−３ｉ工ビ層、３は素子
分離絶縁膜でＳｉ０ｇ膜、４はコレクタ引出領域、５は
眉間絶縁膜、６はｐ型ベース領域、７は眉間絶縁膜、８
はｎ・型工ａツタ領域、Ｅは工電ツタ電極、Ｂはベース
電極、Ｃはコレクタ電極である。In the figure, l is a p-St substrate, IC is a channel cut region, 2 is a collector region with an n-3i bilayer, 3 is an element isolation insulating film and is a Si0g film, 4 is a collector lead-out region, 5 is an insulating film between the eyebrows, 6 is a p-type base region, 7 is an insulating film between the eyebrows, 8
is an n-type vine area, E is a vine electrode, B is a base electrode, and C is a collector electrode.
この実施例の構造は次のようである。The structure of this embodiment is as follows.
表面に段差を持つｐ−５ｉ基板ｌに、コレクタ領域２と
素子分離絶縁膜３とコレクタ引出領域４とを有し。A p-5i substrate 1 having a step on its surface has a collector region 2, an element isolation insulating film 3, and a collector lead-out region 4.
コレクタ領域２は段差下の基板表面に接続するｎ−５ｔ
工ビ層からなり、内部にその表面より順次一導電型王政
ツタ領域８９反対導電型ベース領域６が形威されており
。Collector region 2 is n-5t connected to the substrate surface under the step.
It consists of a vinyl layer, and inside thereof, a monarch ivy region 89 of one conductivity type and a base region 6 of the opposite conductivity type are formed sequentially from the surface.
素子分離絶縁膜３はコレクタ領域２の周縁に接して段差
に沿って基板表面に形威されており。The element isolation insulating film 3 is formed on the substrate surface in contact with the periphery of the collector region 2 and along the steps.
コレクタ引出領域４はコレクタ領域２の側面に接して段
差下の素子分離絶縁膜３上に形威された高濃度のｎ型ポ
リＳｉ層からなっている。The collector lead-out region 4 is made of a highly concentrated n-type poly-Si layer formed on the element isolation insulating film 3 under the step in contact with the side surface of the collector region 2.
次に実施例の半導体装置の製造工程の概略を説明する。Next, the outline of the manufacturing process of the semiconductor device of the example will be explained.
第２図（１）〜（６）は実施例の製造工程を説明する断
面図である。FIGS. 2(1) to 2(6) are cross-sectional views illustrating the manufacturing process of the embodiment.
第２図（１）において、 ｐ−Ｓｉ基板１上全面に厚さ
０．５〜１．０ ａｍのｎ−３ｉ エビ層２と厚さ５０
００人の気相成長（ＣＶＤ）−ＳｉＯｚ膜２１を成長す
る。In FIG. 2 (1), there is an n-3i layer 2 with a thickness of 0.5 to 1.0 am on the entire surface of the p-Si substrate 1 and a layer 2 with a thickness of 50 am.
A SiOz film 21 is grown by chemical vapor deposition (CVD).
次にエビ層２を積んだ基板の表面に段差（溝）を形成す
る。Next, steps (grooves) are formed on the surface of the substrate on which the shrimp layer 2 is laminated.
エビ層２のコレクタ領域の周囲に幅１〜２μｍの溝２２
を形成する。溝２２の深さはｐ−３ｉ基板が７０００〜
１２０００人くぼむように形成する。A groove 22 with a width of 1 to 2 μm is formed around the collector region of the shrimp layer 2.
form. The depth of the groove 22 is 7000 mm for the p-3i substrate.
It will be formed to hold 12,000 people.
溝の形成は、まずＳｉｎｇ膜２１をバターニングして溝
の形成部を開口し、開口されたＳｉＯ□膜２１をマスク
にした反応性イオンエツチング（ＲＩＥ）により行う。The grooves are formed by first buttering the Sing film 21 to open the groove forming portions, and then performing reactive ion etching (RIE) using the opened SiO□ film 21 as a mask.
ＲＩＢは１例えば、平行平板型装置でＣＩＺガスを用い
、これを０．１ Ｔｏｒｒに減圧して１３．５６ ＭＨ
ｚの電力を基板当たり２００ ＩＩ印加して行う。RIB is 1. For example, using CIZ gas in a parallel plate type device, the pressure is reduced to 0.1 Torr to 13.56 MH.
This is done by applying a power of 200 II per substrate.
溝の内側のエビ層２がコレクタ領域となる。The shrimp layer 2 inside the groove becomes the collector region.
第２図（２）において、熱酸化により、溝内面に厚さ５
００ ＡのパッドＳｉＯ！膜２３を形成し、この層を通
して硼素イオン（Ｂ＋）を注入して 、 ＋型のチャネ
ルカッ） ６Ｎ域ＩＣを形成する。In Fig. 2 (2), due to thermal oxidation, the inner surface of the groove has a thickness of 5 mm.
00 A pad SiO! A film 23 is formed, and boron ions (B+) are implanted through this layer to form a 6N region IC with a + type channel.
Ｂ１の注入条件は エネルギー８０ ＫｅＶ、 ドー
ズ量５Ｘ１０′３〜２Ｘ１０”ｃｍ−”である。The implantation conditions for B1 are as follows: energy: 80 KeV; dose: 5×10'3 to 2×10"cm-".
第２図（３）において９通常のりソゲラフイエ程を用い
て溝２２の内側側面に厚さ１０００人の５ｉｚＮ４膜２
４を形威する。In Fig. 2 (3), a 5izN4 film 2 with a thickness of 1000 mm is applied to the inner side surface of the groove 22 using 9 ordinary glue steps.
Express 4.
溝２２の内側側面のみに５Ｌ３Ｎ、膜２４を形成するに
は例えば次のようにする。To form the film 24 of 5L3N only on the inner side surface of the groove 22, for example, the following procedure is performed.
まず、溝内部（側面、底面）を覆って基板全面にＳｉ３
Ｎ４膜を気相成長し、 ＲＩＥによる異方性エツチング
により基板表面及び溝底面の５ｉＪａ膜を除去して、溝
の内側側面と外側側面のＳｉ、Ｎ、膜を残す。次に、溝
内部を覆って基板全面にレジストを塗布し９通常のりソ
ゲラフイエ程を用いて溝２２の内側側面のみに５ｔ３Ｎ
ａ膜２４を残すようにバターニングする。First, Si3 was applied to the entire surface of the substrate, covering the inside of the groove (side and bottom surfaces).
A N4 film is grown in a vapor phase, and the 5iJa film on the substrate surface and the groove bottom is removed by anisotropic etching using RIE, leaving the Si, N, and N films on the inner and outer sides of the groove. Next, apply resist to the entire surface of the substrate, covering the inside of the groove, and apply 5t3N to only the inner side surface of the groove 22 using a normal glue soger coating.
Buttering is performed so that the a film 24 remains.
第２図（４）において、 Ｓｌ、Ｎａ膜膜種４耐酸化マ
スクにして１分離絶縁膜としてウェット酸化による厚さ
４０００〜５０００人のＳｉｎｇ膜３を形成する。この
際。In FIG. 2(4), a Sing film 3 having a thickness of 4,000 to 5,000 wafers is formed by wet oxidation as an isolation insulating film using an oxidation-resistant mask of 4 types of Sl and Na films. On this occasion.
５ｉＯ１膜３はコレクタ領域上にも戒長される。The 5iO1 film 3 is also formed on the collector region.
次いで、 Ｓｉ３Ｎ、膜２４及びパッドＳｉ０ｇ膜２３
を除去する。Next, Si3N film 24 and pad Si0g film 23
remove.
第２図（５）において、厚さ７０００〜１２０００人の
ｎ゛型ポリＳｔ層を基板全面に戒長し、エッチバックし
て溝内にｎ＋型のポリＳｔからなるコレクタ引出領域４
を形成する。ここで、ポリＳｔのドープは成長後に行っ
てもよい。In FIG. 2 (5), an n-type polySt layer with a thickness of 7,000 to 12,000 layers is deposited over the entire surface of the substrate, etched back, and a collector lead-out region 4 made of n+-type polySt is formed in the groove.
form. Here, doping with polySt may be performed after growth.
次に、コレクタ引出領域４の表面に熱酸化５ｉＯｚ膜２
５を形威し、その後熱処理により、コレクタ引出領域４
からコレクタ領域２に不純物を拡散させる。その結果、
コレクタ領域２の界面より内側はｎ゛型になりコンタク
ト抵抗を下げる役目をすることになる。Next, a thermally oxidized 5iOz film 2 is applied to the surface of the collector lead-out region 4.
5 and then heat-treated to form the collector draw-out area 4.
Then, impurities are diffused into the collector region 2. the result,
The area inside the interface of the collector region 2 becomes n-type and serves to lower the contact resistance.
次に、厚さ４０００〜５０００人（７） ＣＶ Ｄ −
Ｓ ｉ Ｏｚ膜２６を基板全面に成長する。Next, thickness 4000-5000 people (7) CV D −
A SiOz film 26 is grown over the entire surface of the substrate.
第２図（６）において、コレクタ領域２上のＳｉｎ、膜
２６及び３を開口してｐ型の不純物を導入してベース領
域６を形成する。In FIG. 2(6), the base region 6 is formed by opening the Sin films 26 and 3 on the collector region 2 and introducing p-type impurities.
次に、開口内に順次ｐ゛型のポリＳｉからなるベース電
極Ｂ、被覆絶縁膜２６１層間絶縁膜としてのＳｉＯ□膜
７を形成する。Next, a base electrode B made of p-type poly-Si, a covering insulating film 261, and a SiO□ film 7 as an interlayer insulating film are sequentially formed in the opening.
この工程の詳細は９例えば、 ＳｉＯ□膜２６及び３の
開口を覆って基板全面にベース電極Ｂ形成用のｐ゛型の
ポリＳｔ層を戒長し、これをバターニングしてベース電
極Ｂを形威し、被覆絶縁膜２６を基板全面に成長する。For details of this process, see 9. For example, a p-type polySt layer for forming the base electrode B is formed on the entire surface of the substrate, covering the openings of the SiO□ films 26 and 3, and this is patterned to form the base electrode B. As a result, a covering insulating film 26 is grown over the entire surface of the substrate.
エミッタ領域形成部の被覆絶縁膜２６とベース電極Ｂを
開口する。眉間絶縁膜として、開口内のベース電極Ｂの
表面に熱酸化ＳｉＯ２膜７を形成する。開口内にＳｉＯ
□膜７を介してｎ゛型のポリＳｉからなるエミッタ電極
を形成する。The coating insulating film 26 and the base electrode B in the emitter region forming portion are opened. A thermally oxidized SiO2 film 7 is formed on the surface of the base electrode B within the opening as an insulating film between the eyebrows. SiO inside the opening
□ An emitter electrode made of n-type poly-Si is formed via the film 7.
次に、工ごツタ電極Ｅから不純物を拡散させてｎ＋型の
工逅ツタ領域８を形成する。又、エミッタ領域８は電極
形成前にイオン注入により形成してもよい。Next, impurities are diffused from the ivy electrode E to form an n+ type ivy region 8. Further, the emitter region 8 may be formed by ion implantation before forming the electrode.
以上で、バイポーラトランジスタの要部が形成される。With the above steps, the main part of the bipolar transistor is formed.
実施例は集積回路のその他の素子形成工程と組み合わせ
て適用することができる。The embodiments can be applied in combination with other integrated circuit device formation processes.
以上説明したように本発明によれば、埋込領域を有しな
い新規の構造により、バイポーラトランジスタの動作速
度を向上させることができた。As described above, according to the present invention, the operating speed of a bipolar transistor can be improved by using a novel structure that does not have a buried region.
例えば、動作領域が同一寸法の場合について。For example, when the operating areas have the same dimensions.
埋込領域を持つ構造の従来例と埋込領域を持たない実施
例を比較すると次のようになる。A comparison between a conventional structure having a buried region and an embodiment without a buried region is as follows.
従来例 実施例
コレクタ抵抗（Ω）８４
コレクタ容量（ｐＦ／２００ ｕ ｍ ”） ０．１
５ ０．０５−スピード （ｐＳ）
１．２ ０．２Conventional example Example Collector resistance (Ω) 84 Collector capacitance (pF/200 um”) 0.1
5 0.05-Speed (pS)
1.2 0.2
第１図は本発明の一実施例を説明する一部断面を示す斜
視図。
第２図（１）〜（６）は実施例の製造工程を説明する断
面図。
第３図は従来例によるバイポーラトランジスタの断面図
である。
図において。
１はｐ−３ｔ基板。
ＩＣはチャネルカット領域。
２はコレクタ領域でｎ−Ｓｉ エビ層。
３は素子分離絶縁膜でＳｉ０ｇ膜。
４はコレクタ引出領域。
釧２ρｂ膜。
６はｐ型ベース領域。
７は眉間絶縁膜。
８はｎ型工逅ツタ領域。
Ｅはエミッタ電極、Ｂはベース電極。
Ｃはコレクタ電極
実拒４Ｐ１の一舟Ｆ＃面乏示す♀斗４足図第 １ 目
実羽１イクリのａＦｏｌ○色］
第２０（イの１）
実施例の断面積
冨２配偕／）２）FIG. 1 is a partially sectional perspective view illustrating an embodiment of the present invention. FIGS. 2(1) to 2(6) are cross-sectional views illustrating the manufacturing process of the embodiment. FIG. 3 is a sectional view of a conventional bipolar transistor. In fig. 1 is a p-3t substrate. IC is a channel cut area. 2 is the n-Si shrimp layer in the collector region. 3 is an element isolation insulating film, which is a Si0g film. 4 is the collector drawer area. Sen2ρb membrane. 6 is a p-type base region. 7 is the glabellar insulating membrane. 8 is the n-type industrial area. E is the emitter electrode, B is the base electrode. C is the collector electrode actual rejection 4P1 one ship F# surface deficiency ♀ 4-legged diagram 1st aFol○ color of 1 grain of grain] 20th (A-1) Example cross-sectional area depth 2 distribution/) 2)
Claims (1)
と素子分離絶縁膜（３）とコレクタ引出領域（４）とを
有し、 コレクタ領域は段差下の基板表面に接続する一導電型半
導体層からなり、内部にその表面より順次一導電型エミ
ッタ領域（８）、反対導電型ベース領域（６）が形成さ
れており、 素子分離絶縁膜はコレクタ領域の周縁に接して段差に沿
って基板表面に形成されており、 コレクタ引出領域はコレクタ領域の側面に接して段差下
の素子分離絶縁膜上に形成された一導電型半導体層から
なることを特徴とする半導体装置。[Claims] A collector region (2) on a substrate (1) having a step on its surface.
, an element isolation insulating film (3), and a collector lead-out region (4), the collector region is made of a semiconductor layer of one conductivity type connected to the surface of the substrate under the step, and an emitter region of one conductivity type is formed inside the layer sequentially from the surface. (8), a base region (6) of the opposite conductivity type is formed, an element isolation insulating film is formed on the substrate surface along the step in contact with the periphery of the collector region, and a collector lead-out region is formed on the side surface of the collector region. 1. A semiconductor device comprising a semiconductor layer of one conductivity type formed on an element isolation insulating film in contact with and under a step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21630189A JPH0380544A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21630189A JPH0380544A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0380544A true JPH0380544A (en) | 1991-04-05 |
Family
ID=16686383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21630189A Pending JPH0380544A (en) | 1989-08-23 | 1989-08-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0380544A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100809909B1 (en) * | 2007-03-07 | 2008-03-06 | 주식회사 케이디파워 | Apparatus of door |
-
1989
- 1989-08-23 JP JP21630189A patent/JPH0380544A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100809909B1 (en) * | 2007-03-07 | 2008-03-06 | 주식회사 케이디파워 | Apparatus of door |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5084402A (en) | Method of fabricating a semiconductor substrate, and semiconductor device, having thick oxide films and groove isolation | |
| US4794445A (en) | Semiconductor device | |
| JPS60117664A (en) | Bipolar semiconductor device | |
| JP2001284587A (en) | Semiconductor device and method of manufacturing the same | |
| JPH0380544A (en) | Semiconductor device | |
| JPH0252858B2 (en) | ||
| JP2538077B2 (en) | Method for manufacturing semiconductor device | |
| JPS5940571A (en) | Semiconductor device | |
| JPH11204541A (en) | Manufacture of combined substrate and semiconductor device | |
| JP2633411B2 (en) | Method for manufacturing semiconductor device | |
| JPH0128507B2 (en) | ||
| JPH02133929A (en) | Semiconductor device and its manufacture | |
| JPH0778833A (en) | Bipolar transistor and its manufacture | |
| JPS6158981B2 (en) | ||
| JPH0252859B2 (en) | ||
| JPS62183558A (en) | Manufacture of bipolar transistor | |
| JP2794571B2 (en) | Manufacturing method of bipolar transistor | |
| JP2604550B2 (en) | Semiconductor device | |
| JPS634664A (en) | Manufacture of semiconductor device | |
| JPH10150108A (en) | Semiconductor device and its manufacture | |
| JPH081927B2 (en) | Method for manufacturing substrate structure of semiconductor device | |
| JPH02246223A (en) | Manufacture of semiconductor device | |
| JPH04352478A (en) | Variable capacity diode | |
| JPH03109738A (en) | Manufacture of semiconductor device | |
| JPH03159167A (en) | Manufacture of semiconductor integrated circuit |