JPH02133929A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH02133929A JPH02133929A JP28907088A JP28907088A JPH02133929A JP H02133929 A JPH02133929 A JP H02133929A JP 28907088 A JP28907088 A JP 28907088A JP 28907088 A JP28907088 A JP 28907088A JP H02133929 A JPH02133929 A JP H02133929A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- field insulating
- film
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000012535 impurity Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000002265 prevention Effects 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 12
- 239000013078 crystal Substances 0.000 abstract description 10
- 230000003064 anti-oxidating effect Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000012528 membrane Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
ＬＯＣＯ３法による絶縁膜からなる素子間分離領域の形
成方法に関し、
フィールド絶縁膜の側端部における欠陥によって生じる
ソース、ドレインの接合リークを抑制して素子特性を向
上させることを目的とし、構造は、一導電型シリコン基
板に設けたフィールド絶縁膜によって素子分離される構
造の半導体装置において、前記フィールド絶縁膜の側端
部に接する異種導電型不純物領域が該側端部において前
記フィールド絶縁膜に接して該フィールド絶縁膜の深さ
まで延在した構成にする。[Detailed Description of the Invention] [Summary] Regarding a method for forming an isolation region made of an insulating film using the LOCO3 method, the device characteristics can be improved by suppressing source/drain junction leakage caused by defects at the side edges of a field insulating film. In a semiconductor device having a structure in which elements are isolated by a field insulating film provided on a silicon substrate of one conductivity type, an impurity region of a different conductivity type in contact with a side edge of the field insulating film is The side end portion is in contact with the field insulating film and extends to the depth of the field insulating film.
製造方法は、一導電型シリコン基板に酸化シリコン膜を
介して酸化防止膜のパターンを形成し、該酸化防止膜を
マスクとして前記酸化シリコン膜を透過させて異種導電
型不純物イオンを注入する工程と、次いで、酸化防止膜
をマスクとして熱酸化してフィールド絶縁膜を生成し、
前記酸化防止膜およびフィールド絶縁膜を透過させて全
面に一導電型不純物イオンを注入し、次いで、熱処理し
て前記フィールド絶縁膜の側端部に異種導電型不純物領
域、フィールド絶縁膜の底面に一導電型不純物領域を形
成する工程とが含まれてなることを特徴とする。The manufacturing method includes forming an anti-oxidation film pattern on a silicon substrate of one conductivity type via a silicon oxide film, and implanting impurity ions of a different conductivity type through the silicon oxide film using the anti-oxidation film as a mask. Then, a field insulating film is generated by thermal oxidation using the anti-oxidation film as a mask,
Impurity ions of one conductivity type are implanted into the entire surface through the oxidation prevention film and the field insulating film, and then heat treatment is performed to form impurity regions of a different conductivity type at the side edges of the field insulating film and at the bottom of the field insulating film. The method is characterized in that it includes a step of forming a conductive type impurity region.
本発明は半導体装置の製造方法にかかり、特にＬＯＣＯ
３法による絶縁膜からなる素子量分＃領域の形成方法に
関する。The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming a # region of an element amount consisting of an insulating film using three methods.
従来よりＬＳＩなどの半導体装置における素子間分離（
アイソレーション； １ｓｏｌａｔｉｏｎ ）方法とし
てＬＯＣＯ３法と呼ばれる選択酸化法が重用されている
が、このＬＯＣＯ３法によるフィールド絶縁膜は素子間
分離を完全にして界面リークを防止するために、フィー
ルド絶縁膜に接する半導体基板面に高不純物濃度層から
なるチャネルカット層を設ける構造が採られている。Conventionally, isolation between elements in semiconductor devices such as LSI (
A selective oxidation method called the LOCO3 method is widely used as an isolation (1solation) method.The field insulating film using the LOCO3 method is designed to completely isolate devices and prevent interfacial leakage between semiconductors in contact with the field insulating film. A structure is adopted in which a channel cut layer made of a high impurity concentration layer is provided on the substrate surface.
第３図（、；）、 （ｂ）は従来のＭＯ３型半導体装置
の断面図で、同図（ａ）は−殻構造のＭＯ３型半導体装
置。3(a) and 3(b) are cross-sectional views of a conventional MO3 type semiconductor device, and FIG. 3(a) is an MO3 type semiconductor device with a -shell structure.
同図（ｂｌはＬ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅ
ｄ Ｄｒａｉｎ ）構造のＭＯ３型半導体装置であって
、後者のＬＤＤ構造は公知のようにショートチャネル効
果を抑制するために考案された構造である。図中の記号
１はｐ型シリコン基板、２は酸化シリコン（ＳｉＯｚ）
膜からなるフィールド絶縁膜、３はｐ＋型チャネルカッ
ト層、４はゲート絶縁膜、５はゲート電極。The same figure (bl is L D D (Lightly Dope
d Drain ) structure, and the latter LDD structure is a structure devised to suppress the short channel effect as is well known. Symbol 1 in the figure is a p-type silicon substrate, 2 is silicon oxide (SiOz)
3 is a p+ type channel cut layer, 4 is a gate insulating film, and 5 is a gate electrode.
６はｎ型のソース領域どドレイン領域、７はＬＤＤｉ造
に特有のｎ−型のソース領域、ドレイン領域である。Reference numeral 6 indicates an n-type source region and drain region, and 7 indicates an n-type source region and drain region specific to the LDDi structure.
第４図（ａｌ〜ｆｆ）は−殻構造のＭＯ３型半導体装置
の従来の形成方法の工程順断面図を示しており、その概
要を説明すると、
第４図（ａｌ参照；まず、ｐ型シリコン基板１上に薄い
ＳｉＯ□膜１１全１１化して生成し、その上に化学気相
成長（ＣＶＤ）法によツ７ Ｓ ｉ ：ｌ Ｎ ＜膜１
２を被着する。FIG. 4 (al to ff) shows a step-by-step cross-sectional view of a conventional method for forming an MO3 type semiconductor device with a -shell structure, and the outline thereof is as follows. A thin SiO□ film 11 is formed on the substrate 1, and a thin SiO□ film 11 is formed on the substrate 1 by chemical vapor deposition (CVD).
2.
第４図（ｂｌ参照；次いで、上面にレジスト膜パターン
１３を選択的に形成し、それをマスクにしてＳｉ３Ｎ４
膜１２をエツチングして素子形成領域上のみに５ｉ３Ｎ
ａ膜１２を残存させる。FIG. 4 (see BL; next, a resist film pattern 13 is selectively formed on the upper surface, and using it as a mask, Si3N4
The film 12 is etched to form 5i3N only on the element forming area.
The a film 12 is left.
第４図（Ｃ１参照；次いで、５ｉ３Ｎａ膜１２およびレ
ジスト膜パターン１３のマスク部分を除いた５ｉｏｚｌ
ｌｉ１１の露出面にＳｉＯ□膜１１全１１させて硼素（
Ｂ”）をイオン注入する。FIG. 4 (see C1; next, the 5i3Na film 12 and the masked portion of the resist film pattern 13 are removed.
Boron (
B'') is ion-implanted.
第４図ｆｄｌ参照；次いで、レジスト膜パターン１３を
除去した後、１０００℃以上の高温度で熱酸化してＳｉ
Ｏ□膜からなるフィールド絶縁膜２を生成し、且つ、ｐ
゛型チャネルカット層３を活性化して画定する。See FIG. 4 fdl; Next, after removing the resist film pattern 13, thermal oxidation is performed at a high temperature of 1000° C. or higher to form a Si
A field insulating film 2 made of O□ film is produced, and p
A type channel cut layer 3 is activated and defined.
第４図ｔｅｌ参照；次いで、素子形成領域を被覆してい
るＳｉｎｇ膜１１およびＳｉ、 Ｎ、膜１２を除去し、
新たなＳｉｎ、膜を生成して、その上にＣＶＤ法によっ
て多結晶シリコン膜を被着し、これをレジスト膜パター
ン１４を用いてパターンニングして５ｉＯｚ膜からなる
ゲート絶縁膜４と多結晶シリコン膜からなるゲート電極
５を形成する。Refer to FIG. 4 (tel); Next, the Sing film 11 and the Si, N, film 12 covering the element formation region are removed.
A new Sin film is generated, a polycrystalline silicon film is deposited on it by the CVD method, and this is patterned using a resist film pattern 14 to form a gate insulating film 4 made of a 5iOz film and polycrystalline silicon. A gate electrode 5 made of a film is formed.
第４図（ｆｌ参照；次いで、ｎ型のソース領域、ドレイ
ン領域６を形成するために、砒素（Ａｓ” ）をイオン
注入する。4 (see fl; see FIG. 4; next, arsenic (As'') is ion-implanted to form n-type source and drain regions 6.
しかる後、熱処理してｎ型ソース領域、ｎ型ドレイン領
域６を画定して第３図（ａ）のように完成させる。Thereafter, heat treatment is performed to define an n-type source region and an n-type drain region 6 to complete the structure as shown in FIG. 3(a).
なお、第３図（ｂｌに示すＬＤＤ構造のＭＯ３型半導体
装置は工程途中（第４図ｔｅｌと第４図ｉｆ）の間）に
ｎ−型のソース領域、ドレイン領域７の形成工程とサイ
ドウオールとなる絶縁膜をゲート電極４の周囲に形成す
る工程が追加されるが、他は上記の形成方法と同様であ
る。Note that the MO3 type semiconductor device with the LDD structure shown in FIG. 3 (bl) has an n-type source region and drain region 7 formed during the process (between FIG. 4 tel and FIG. 4 if) and a side wall. A step of forming an insulating film around the gate electrode 4 is added, but the other steps are the same as the above-described forming method.
ところが、従前はソース領域、ドレイン領域がフィール
ド絶縁膜の深さに近い厚みにまで形成していたために余
り問題にはならなかったが、最近、微細化されてソース
領域、ドレイン領域の厚みが浅くなり、しかも、それに
比例してフィールド絶縁膜の厚さは余り浅くならないた
めに、フィールド絶縁膜の側端部においてフィールド絶
縁膜とソース領域、ドレイン領域との深さが大きく相違
して、半導体装置の動作時にソース、ドレイン領域周囲
に発生する空乏層がフィールド絶縁膜の側端に生じてい
る結晶欠陥部の中に形成され、その結果、ソース、ドレ
インの接合リークが発生して特性劣化をきたすことが問
題になってきた。However, in the past, this did not pose much of a problem because the source and drain regions were formed to a thickness close to the depth of the field insulating film, but recently, with miniaturization, the thickness of the source and drain regions has become shallower. Moreover, since the thickness of the field insulating film does not become very shallow in proportion to this, the depths of the field insulating film and the source and drain regions are greatly different at the side edges of the field insulating film, causing a semiconductor device During operation, a depletion layer that occurs around the source and drain regions is formed in the crystal defects that occur at the side edges of the field insulating film, resulting in junction leakage between the source and drain, resulting in characteristic deterioration. This has become a problem.
このようなフィールド絶縁膜の側端部における結晶欠陥
（第３図にＸ印で示す）はシリコンを熱酸化してＳｉＯ
□膜を生成した際、Ｓｉｎ、膜の膨張によってシリコン
に歪みを与えて発生するもので、これを回避することは
困難である。Such crystal defects at the side edges of the field insulating film (indicated by
□When a film is formed, the expansion of the film causes strain on the silicon, and it is difficult to avoid this.
本発明はこのような問題点を解消させ、フィールド絶縁
膜の側端部における欠陥によって生じるソース、ドレイ
ンの接合リークを抑制して素子特性を向上させることを
目的とした半導体装置の構造と製造方法を提案するもの
である。The present invention solves these problems and provides a structure and manufacturing method for a semiconductor device, which aims to improve device characteristics by suppressing source/drain junction leakage caused by defects at the side edges of a field insulating film. This is what we propose.
その課題は、第１図の実施例図に示すように、一導電型
シリコン基板１上に設けたフィールド絶縁膜２の側端部
に接する異種導電型不純物領域１０が該側端部において
前記フィールド絶縁膜に接して該フィールド絶縁膜の深
さまで延在している構造を有する半導体装置によって解
決される。The problem is that, as shown in the embodiment diagram of FIG. The problem is solved by a semiconductor device having a structure in contact with an insulating film and extending to the depth of the field insulating film.
その製造方法は、第２図に示すように、−ｉ電型シリコ
ン基板１上にＳｉＯ□膜１１を介してＳｉ、 Ｎ４膜な
どの酸化防止膜１２をパターンニングし、該酸化防止膜
をマスクとして５ｉＯｚ膜を透過させて異種導電型不純
物イオンを注入する工程と、次いで、前記酸化防止膜を
マスクとして熱酸化してフィールド絶縁膜２を生成する
工程と、次いで、前記酸化防止膜およびフィールド絶縁
膜を透過させて全面に一導電型不純物イオンを注入し、
熱処理して前記フィールド絶縁膜の側端部に異種導電型
不純物領域１０．フィールド絶縁膜の底面に一導電型不
純物領域３を同時に形成する工程とが含まれることを特
徴としている。As shown in FIG. 2, the manufacturing method involves patterning an oxidation prevention film 12 such as a Si or N4 film on a -i type silicon substrate 1 through a SiO□ film 11, and masking the oxidation prevention film. a step of implanting impurity ions of a different conductivity type through a 5iOz film, a step of thermally oxidizing the field insulating film 2 using the anti-oxidation film as a mask, and then a step of implanting impurity ions of a different conductivity type through the 5iOz film; Impurity ions of one conductivity type are implanted into the entire surface through the membrane,
A heat treatment is performed to form impurity regions 10 of different conductivity type on the side edges of the field insulating film. It is characterized in that it includes a step of simultaneously forming an impurity region 3 of one conductivity type on the bottom surface of the field insulating film.
即ち、本発明はフィールド絶縁膜を生成する前に、フィ
ールド絶縁膜側端に接する異種導電型（基板とは異種導
電型のこと）不純物領域を形成するための不純物をイオ
ン注入し、次いで、フィールド絶縁膜を生成した後に、
フィールド絶縁膜および酸化防止膜を透過させて全面に
チャネルカット層となるための不純物イオンを注入し、
熱処理してフィールド絶縁膜の側端部に異種導電型不純
物領域、フィールド絶縁膜の底面にチャネルカット層を
同時に形成する。かくして、フィールド絶縁膜側端に接
する異種導電型不純物領域がフィールド絶縁膜の深さま
で延在している構造に構成にする。That is, in the present invention, before forming a field insulating film, impurity ions are implanted to form an impurity region of a different conductivity type (different conductivity type than the substrate) in contact with the side edge of the field insulating film. After generating the insulating film,
Impurity ions are implanted to form a channel cut layer on the entire surface by penetrating the field insulating film and anti-oxidation film.
Heat treatment is performed to simultaneously form impurity regions of different conductivity types on the side edges of the field insulating film and a channel cut layer on the bottom surface of the field insulating film. In this way, a structure is created in which the impurity region of different conductivity type in contact with the side edge of the field insulating film extends to the depth of the field insulating film.
そうすれば、接合リークを生じる結晶欠陥部分は異種導
電型不純物領域に含まれ、空乏層には結晶欠陥がなくな
り、そのため、接合リークがなくなって素子特性が向上
する。By doing so, the crystal defect portion that causes junction leakage is included in the different conductivity type impurity region, and the depletion layer is free of crystal defects, thereby eliminating junction leakage and improving device characteristics.
以下、図面を参照して実施例によって詳細に説明する。 Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図（ａ）、 （ｂｌは本発明にかかるＭＯ３型半導
体装置の断面図で、同図（ａ）は−殻構造のＭＯ３型半
導体装置、同図（ｂｌはＬＤＤ構造のＭＯ３型半導体装
置であり、図中の記号は第３図と同一部位に同一記号が
付けであるが、その他の１０がフィールド絶縁膜の側端
部に設けたｎ型のソース領域とドレイン領域である。こ
のようなｎ型ソース領域、ドレイン領域１０が結晶欠陥
部分を包含して、空乏層に結晶欠陥をなくし、その結果
、接合リークがなくなって素子特性が改善される。FIGS. 1(a) and (bl are cross-sectional views of an MO3 type semiconductor device according to the present invention; FIG. 1(a) is a cross-sectional view of an MO3 type semiconductor device with a -shell structure; The symbols in the figure are the same parts as in Figure 3, and the other 10 are the n-type source and drain regions provided at the side edges of the field insulating film. The n-type source and drain regions 10 include crystal defect portions to eliminate crystal defects in the depletion layer, and as a result, junction leakage is eliminated and device characteristics are improved.
次に、第２図（ａｌ〜（ｇｌは本発明にかかる形成方法
の工程順断面図で、順を追って説明する。Next, FIGS. 2A to 2G are cross-sectional views showing the steps of the forming method according to the present invention, which will be explained step by step.
第２図（ａ）参照：従来法と同様に、ｐ型シリコン基板
１上に薄いＳｉｎ、膜１１を熱酸化して生成し、その上
にＣＶＤ法によって５ｉ３Ｎａ膜１２（酸化防止膜）を
被着する。Refer to FIG. 2(a): Similar to the conventional method, a thin Sin film 11 is formed on a p-type silicon substrate 1 by thermal oxidation, and a 5i3Na film 12 (antioxidation film) is coated thereon by the CVD method. wear it.
第２図（ｂｌ参照：更に従来と同しく、レジスト膜パタ
ーン１３を形成し、それをマスクにしてＳｉ、 Ｎ４膜
１２をエツチング除去して素子形成領域のみにＳｉ３Ｎ
、膜１２を残存させる。FIG. 2 (see BL: Further, as in the conventional method, a resist film pattern 13 is formed, and using this as a mask, the Si and N4 films 12 are etched away, and Si3N is etched only in the element formation region.
, leaving the membrane 12 remaining.
第２図（Ｃ）参照；次いで、５ｉｚＮ４膜１２およびレ
ジスト膜パターン１３のマスク部分を除いたＳｉＯ□膜
１１膜上１面にＳ ｉ Ｏｚ膜１１を透過させて砒素（
＾Ｓ゛）をイオン注入する。イオン注入条件は加速電圧
６０ＫｅＶ、ドーズ量５ ×１０１１〜５ Ｘ １０Ｉ
ｚ／ ｃｎｌ程度とする。Refer to FIG. 2(C); Next, arsenic (
＾S゛) is ion-implanted. The ion implantation conditions were an acceleration voltage of 60 KeV and a dose of 5 × 1011 to 5 × 10I.
It should be about z/cnl.
第２図（ｄｌ参照：次いで、レジスト膜パターン１３を
除去した後、１０００℃以上の高温度で熱酸化してＳｉ
Ｏ２膜からなるフィールド絶縁膜２（膜厚５０００人）
を生成する。その時、フィールド絶縁膜２の底部を含む
周囲部分に砒素イオン注入によるｎ型領域１０（フィー
ルド絶縁膜の側端部のｎ型ソース領域、ドレイン領域に
なる）が活性化され画定される。FIG. 2 (see dl: Next, after removing the resist film pattern 13, Si is thermally oxidized at a high temperature of 1000°C or more.
Field insulating film 2 made of O2 film (thickness: 5000)
generate. At this time, n-type regions 10 (which will become n-type source and drain regions at the side edges of the field insulating film) are activated and defined by arsenic ion implantation in the peripheral portion including the bottom of the field insulating film 2.
第２図（ｅｌ参照：次いでフィールド絶縁膜２とＳｉ３
Ｎ、膜１２． Ｓｉ ０２膜１１とを透過させて全面に
硼素（Ｂ＋）をシリコン基板１の深くまでイオン注入す
る。この時、硼素はシリコン基板内部に深く注入されて
、素子形成領域にも注入される。この時のイオン注入条
件は加速電圧１５０〜２００ＫｅＶ、 ドーズ量２
ＸＩＯ”／ ｃｒｌ程度にする。FIG. 2 (see el: Next, field insulating film 2 and Si3
N, membrane 12. Boron (B+) is ion-implanted to the entire surface of the silicon substrate 1 by penetrating the Si 0 2 film 11 to the depth of the silicon substrate 1 . At this time, boron is implanted deeply into the silicon substrate and also into the element formation region. The ion implantation conditions at this time were an acceleration voltage of 150 to 200 KeV, and a dose of 2.
XIO”/crl.
第２図（ｆ）参照；次いで、素子形成領域を被覆してい
るＳｉＯ□膜１１膜上１Ｓｉ３Ｎ、膜１２を除去し、新
たなＳｉｎ、膜を生成し、その上にＣＶＤ法によって多
結晶シリコン膜を被着し、これをレジスト膜パターン１
４を用いてパターンニングして５ｉｎ２膜からなるゲー
ト絶縁膜４と多結晶シリコン膜からなるゲート電漸５
（幅５０００〜６０００人）を形成する。Refer to FIG. 2(f); Next, the 1Si3N film 12 on the SiO□ film 11 covering the element formation region is removed, a new Sin film is formed, and polycrystalline silicon is deposited on it by CVD. Deposit a film and apply this as resist film pattern 1
A gate insulating film 4 made of a 5in2 film and a gate electric potential 5 made of a polycrystalline silicon film are patterned using
(width 5,000 to 6,000 people).
第４図（ｇｌ参照；次いで、ｎ型のソース領域、ドレイ
ン領域６を形成するために、砒素（Ａｓ” ）をイオン
注入する。FIG. 4 (see gl) Next, arsenic (As'') ions are implanted to form n-type source and drain regions 6.
しかる後、熱処理してｎ型ソース領域、ｎ型ドレイン領
域６ （深さ１０００〜２０００人）およびｐ゛型チャ
ネルカット層３を活性化して画定し、第１図（ａｌのよ
うに完成する。Thereafter, a heat treatment is performed to activate and define the n-type source region, the n-type drain region 6 (depth 1000 to 2000 mm), and the p'-type channel cut layer 3, and the device is completed as shown in FIG. 1 (al).
なお、第１図（ｂｌに示すＬＤＤ構造のＭＯ３型半導体
装置も上記の形成方法と同様にして形成される。Incidentally, an MO3 type semiconductor device having an LDD structure shown in FIG.
上記のような形成方法によれば、接合リークを生じるフ
ィールド絶縁膜２の側端部の結晶欠陥部分はｎ゛型ソー
ス領域、ドレイン領域１０に含まれるために、動作時に
発生する空乏層には結晶欠陥がなくなり、リーク特性が
改善されて、素子特性が向上する。According to the above-described formation method, since the crystal defect portion at the side edge of the field insulating film 2 that causes junction leakage is included in the n-type source region and drain region 10, the depletion layer generated during operation is Crystal defects are eliminated, leakage characteristics are improved, and device characteristics are improved.
なお、上記の実施例はＭＯ３型半導体装置で説明してい
るが、バイポーラ型など他の半導体装置にも適用できる
ことは当然である。Note that although the above embodiment has been described using an MO3 type semiconductor device, it is of course applicable to other semiconductor devices such as a bipolar type.
以上の説明から明らかなように、本発明によればリーク
電流が小さく素子特性の良い微細な半導体装置を実現す
ることができる。As is clear from the above description, according to the present invention, a fine semiconductor device with low leakage current and good device characteristics can be realized.
且つ、本発明によればチャネルカット層となる不純物が
シリコン基板全面の深くに注入されてシリコン基板が高
濃度になるためにα線のような放射線に強い構造の半導
体装置になる利点もある。In addition, according to the present invention, impurities forming a channel cut layer are implanted deep into the entire surface of the silicon substrate, resulting in a high concentration of the silicon substrate, which has the advantage of providing a semiconductor device with a structure that is resistant to radiation such as alpha rays.
第１図（ａ）、 （ｂ）は本発明にかかるＭＯ３型半導
体装置の断面図、
第２図（ａｌ〜（ａは本発明にかかる形成方法の工程順
断面図、
第３図は従来のＭＯ３型半導体装置の断面図、第４図ｆ
８）〜（ｆ）は従来の形成方法の工程順断面図である。
図において、
１はｐ型シリコン基板、
２はフィールド絶縁膜、
３はｐ＋型チャネルカット層、
４はゲート絶縁膜、
５はゲート電極、
６はｎ型のソース領域、ドレイン領域、７はｎ−型のソ
ース領域、ドレイン領域、１０はフィールド絶縁膜の側
端部のｎ型のソース領域、ドレイン領域、
１１はＳｉｎ、膜、
１２はＳｔ、 Ｎ４膜（酸化防止膜）、１３、１４はレ
ジスト膜パターン
を示している。
不発明１：ｔ）’ｔＰ３阿ａＳを十導確ス１褐鈴而図第
１図
、ｊ２ Ｓ＋３Ｎ４月粟1(a) and (b) are cross-sectional views of an MO3 type semiconductor device according to the present invention, FIG. Cross-sectional view of MO3 type semiconductor device, Figure 4f
8) to (f) are step-by-step sectional views of the conventional forming method. In the figure, 1 is a p-type silicon substrate, 2 is a field insulating film, 3 is a p+ type channel cut layer, 4 is a gate insulating film, 5 is a gate electrode, 6 is an n-type source region and drain region, and 7 is an n- 10 is an n-type source region and drain region at the side edge of the field insulating film, 11 is a Sin film, 12 is St, N4 film (antioxidation film), 13 and 14 are resists. The membrane pattern is shown. Non-invention 1: t)'t
Claims (2)
によつて素子分離される構造の半導体装置において、 前記フィールド絶縁膜の側端部に接する異種導電型不純
物領域が該側端部において前記フィールド絶縁膜に接し
て該フィールド絶縁膜の深さまで延在していることを特
徴とする半導体装置。(1) In a semiconductor device having a structure in which elements are isolated by a field insulating film provided on a silicon substrate of one conductivity type, an impurity region of a different conductivity type in contact with a side edge of the field insulating film is connected to the field at the side edge. A semiconductor device characterized in that the semiconductor device is in contact with an insulating film and extends to the depth of the field insulating film.
コン膜を生成し、該酸化シリコン膜上に酸化防止膜を形
成する工程と、 次いで、酸化防止膜をパターンニングし、該酸化防止膜
をマスクとして前記酸化シリコン膜を透過させて異種導
電型不純物イオンを注入する工程と、次いで、前記酸化
防止膜をマスクとして熱酸化してフィールド絶縁膜を生
成する工程と、 次いで、前記酸化防止膜およびフィールド絶縁膜を透過
させて全面に一導電型不純物イオンを注入する工程と、 次いで、熱処理して前記フィールド絶縁膜の側端部に異
種導電型不純物領域を形成し、同時にフィールド絶縁膜
の底面に一導電型不純物領域を形成する工程とが含まれ
てなることを特徴とする半導体装置の製造方法。(2) A step of oxidizing the surface of a silicon substrate of one conductivity type to generate a silicon oxide film, and forming an oxidation prevention film on the silicon oxide film, and then patterning the oxidation prevention film, and forming the oxidation prevention film on the silicon oxide film. implanting impurity ions of a different conductivity type through the silicon oxide film using as a mask, then thermally oxidizing the silicon oxide film as a mask to generate a field insulating film; and implanting impurity ions of one conductivity type into the entire surface through the field insulating film, and then performing heat treatment to form impurity regions of a different conductivity type at the side edges of the field insulating film, and at the same time implanting impurity ions of one conductivity type into the bottom surface of the field insulating film. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming an impurity region of one conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28907088A JPH02133929A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28907088A JPH02133929A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02133929A true JPH02133929A (en) | 1990-05-23 |
Family
ID=17738437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28907088A Pending JPH02133929A (en) | 1988-11-15 | 1988-11-15 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02133929A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152324A (en) * | 1991-11-26 | 1993-06-18 | Sharp Corp | Manufacture of semiconductor device |
| DE4325348A1 (en) * | 1992-08-03 | 1994-02-10 | Mitsubishi Electric Corp | Semiconductor device with p=n junction, e.g n=channel transistor - has impurity diffusion region between first impurity region and impurity concentration peak |
| US5529948A (en) * | 1994-07-18 | 1996-06-25 | United Microelectronics Corporation | LOCOS technology with reduced junction leakage |
| US5623154A (en) * | 1994-10-25 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having triple diffusion |
-
1988
- 1988-11-15 JP JP28907088A patent/JPH02133929A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152324A (en) * | 1991-11-26 | 1993-06-18 | Sharp Corp | Manufacture of semiconductor device |
| DE4325348A1 (en) * | 1992-08-03 | 1994-02-10 | Mitsubishi Electric Corp | Semiconductor device with p=n junction, e.g n=channel transistor - has impurity diffusion region between first impurity region and impurity concentration peak |
| US5440165A (en) * | 1992-08-03 | 1995-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with means for suppressing electric fields |
| US5635413A (en) * | 1992-08-03 | 1997-06-03 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing field effect transistor |
| US5529948A (en) * | 1994-07-18 | 1996-06-25 | United Microelectronics Corporation | LOCOS technology with reduced junction leakage |
| US5668393A (en) * | 1994-07-18 | 1997-09-16 | United Microelectronics Corporation | Locos technology with reduced junction leakage |
| US5623154A (en) * | 1994-10-25 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having triple diffusion |
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