JPH0364108A - Operational amplifier circuit - Google Patents
Operational amplifier circuitInfo
- Publication number
- JPH0364108A JPH0364108A JP1200608A JP20060889A JPH0364108A JP H0364108 A JPH0364108 A JP H0364108A JP 1200608 A JP1200608 A JP 1200608A JP 20060889 A JP20060889 A JP 20060889A JP H0364108 A JPH0364108 A JP H0364108A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- cascode
- output
- trs
- differential pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路に適した演算増幅回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an operational amplifier circuit suitable for integrated circuits.
一般に、演算増幅回路は、種々提案されているが、その
中で第２図に示す回路は、フォールデッド・カスコード
演算増幅回路として、知られている。この回路は、トラ
ンジスタＱ６〜Ｑ８の差動対と、トランジスタＱ、〜Ｑ
１５のカスコード段と、トランジスタＱ２３． Ｑ２４
の出力段で構成される。Generally, various operational amplifier circuits have been proposed, and among them, the circuit shown in FIG. 2 is known as a folded cascode operational amplifier circuit. This circuit consists of a differential pair of transistors Q6-Q8 and transistors Q, ~Q
15 cascode stages and transistors Q23. Q24
It consists of an output stage.
又電流源■１とトランジスタＱ、〜Ｑｓでバイアス回路
を構成している。この回路に於いては、入力電圧範囲が
広く、周波数特性が良好であることが知られている。Further, a bias circuit is constituted by the current source (1) and the transistors Q, -Qs. This circuit is known to have a wide input voltage range and good frequency characteristics.
上述した従来のフォールデッド・カスコード演算増幅回
路は、出力段がＡ級増幅回路であるため、負荷に対する
吸い込み電流（第２図の回路の極性の場合）の最大値は
、トランジスタＱＩＯのバイアス電流値である。従って
、演算増幅器の動作速度を高速とする為には、トランジ
スタＣ２３のバイアス電流値を大きく設定しておく必要
があり、これは必然的に消費電力の増加を招き、許容消
費電力が小さい時、動作速度が大きく制限されるという
欠点があった。In the conventional folded cascode operational amplifier circuit described above, the output stage is a class A amplifier circuit, so the maximum value of the sink current to the load (in the case of the polarity of the circuit in Figure 2) is equal to the bias current value of the transistor QIO. It is. Therefore, in order to increase the operating speed of the operational amplifier, it is necessary to set the bias current value of the transistor C23 to a large value, which inevitably leads to an increase in power consumption, and when the allowable power consumption is small, The drawback was that the operating speed was severely limited.
本発明の目的は、このような欠点を除き、高速動作と共
に、消費電力を少くした演算増幅器を提供することにあ
る。An object of the present invention is to eliminate such drawbacks and provide an operational amplifier that operates at high speed and consumes less power.
本発明の演算増幅回路の構成は、２つのトランジスタの
ゲートが各々第１．第２の入力端子にそれぞれ接続され
た第１の差動対と、この第１の差動対の第１と第２の各
ドレイン出力の各々が入力にそれぞれ接続されこの第１
の差動対と逆極性を有する第１．第２のカスコード回路
と、これら第１、第２のカスコード回路の入力に、ゲー
ト端子が接続された第１．第２のソース接地トランジス
タと、これら第１．第２のトランジスタのドレイン端子
が入力に接続され前記第１．第２の各カスコード回路と
逆極性の第３．第４のカスコード回路と、前記第１．第
２のカスコード回路の出力が。The configuration of the operational amplifier circuit of the present invention is such that the gates of two transistors are connected to the first . a first differential pair each connected to a second input terminal, and each of the first and second drain outputs of the first differential pair connected to an input terminal of the first differential pair;
The first differential pair has opposite polarity to the differential pair. a second cascode circuit, and a first cascode circuit whose gate terminal is connected to the inputs of the first and second cascode circuits. a second common source transistor; A drain terminal of the second transistor is connected to the input of the first transistor. A third cascode circuit of opposite polarity to each second cascode circuit. a fourth cascode circuit; and the first cascode circuit. The output of the second cascode circuit is.
入力された第１のシングルエンド変換回路と、前記第３
．第４のカスコード回路の出力がそれぞれ入力された第
２のシングルエンド変換回路と、前記第１．第２のシン
グルエンド変換回路の各々の出力が入力されその出力端
が出力端子に接続された第３のシングルエンド変換回路
とを有することを特徴とする。the input first single-ended conversion circuit;
．． a second single-ended conversion circuit to which the output of the fourth cascode circuit is respectively input; and a third single-ended conversion circuit to which each output of the second single-ended conversion circuit is input and whose output end is connected to the output terminal.
次に、本発明について図面を用いて詳細に説明する。 Next, the present invention will be explained in detail using the drawings.
第１図は本発明の第１の実施例を示す回路図である。こ
の回路は、トランジスタＱ６〜Ｑ、で差動対を構威し、
トランジスタＱ ＋ ｏ 、 Ｑ ｌ ４ 、 Ｑ １
ａ ｚ Ｑ ２１のゲート電位は固定バイアスされ、各
々カスコード回路を構成している。又、トランジスタＱ
、、、Ｑ、、とＱ １ｅ ｚ Ｑ ２０及び、Ｑ ２３
１ Ｑ ２４はシングルエンド変換回路であり、トラン
ジスタＣ２３１Ｃ２４のシングルエンド変換回路の出力
が、この演算増幅回路の出力端子３に導出されている。FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This circuit uses transistors Q6 to Q to form a differential pair,
Transistors Q + o, Q l 4, Q 1
The gate potential of azQ 21 is fixed biased, and each constitutes a cascode circuit. Also, transistor Q
, ,Q, , and Q 1e z Q 20 and ,Q 23
1Q24 is a single-end conversion circuit, and the output of the single-end conversion circuit of transistor C231C24 is led out to the output terminal 3 of this operational amplifier circuit.
この構成に於いて、入力端子１，２から入力信号が入力
された時の動作を考察する。差動対の差動出力は、２つ
の信号系路を持つが、１つはトランジスタＱ１゜とＱｌ
４のカスコード回路に入力され、その出力がトランジス
タＱ、、、Ｑ、、でシングル出力に変換され、トランジ
スタＣ２３のゲートを駆動する。他の１つの信号系路は
トランジスタＣ１２゜Ｑｌ、のソース接地トランジスタ
を介して、トランジスタＱｌｌｌ Ｃ２１のカスコード
回路に入力され、その出力がトランジスタＱ＋ｓ＋Ｑｚ
。でシングル出力に変換され、トランジスタＣ２４のゲ
ートを駆動する。従って、トランジスタＣ２３，Ｃ２４
は所謂プッシュプル動作を行うことになり、負荷に対し
て、正負両サイクルともに高速に動作することが出来る
。In this configuration, the operation when input signals are input from input terminals 1 and 2 will be considered. The differential output of the differential pair has two signal paths, one of which is connected to transistors Q1 and Ql.
The signal is input to the cascode circuit No. 4, and its output is converted into a single output by transistors Q, , , Q, , and drives the gate of transistor C23. The other signal path is input to the cascode circuit of transistor Qllll C21 via the common source transistor of transistor C12゜Ql, and its output is input to the cascode circuit of transistor Q+s+Qz.
. It is converted into a single output at , and drives the gate of transistor C24. Therefore, transistors C23 and C24
performs a so-called push-pull operation, and can operate at high speed in both positive and negative cycles with respect to the load.
以上説明したように本発明は、プッシュプル動作が得ら
れ、高速動作が達成出来ると共に、カスコード回路の多
段構成であるので、発振現象に対しても安定であるとい
う効果がある。As explained above, the present invention has the advantage of being able to achieve push-pull operation and high-speed operation, and also being stable against oscillation phenomena due to the multi-stage configuration of cascode circuits.
第１図は本発明の一実施例を示す回路図、第２図は従来
例の演算増幅回路を示す回路図である。
１．２・・・・・・入力端子、３・・・・・・出力端子
、４・・・・・・電源端子％ Ｑｌ〜Ｑ２４・・・・・
・ トランジスタ、Ｃ１・・・・・・容量、Ｉｌｌ Ｉ
２・・・・・・定電流源。FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional operational amplifier circuit. 1.2...Input terminal, 3...Output terminal, 4...Power supply terminal% Ql~Q24...
・Transistor, C1...Capacity, Ill I
2... Constant current source.
Claims (1)
子にそれぞれ接続された第１の差動対と、この第１の差
動対の第１と第２の各ドレイン出力の各々が入力にそれ
ぞれ接続されこの第１の差動対と逆極性を有する第１、
第２のカスコード回路と、これら第１、第２のカスコー
ド回路の入力に、ゲート端子が接続された第１、第２の
ソース接地トランジスタと、これら第１、第２のトラン
ジスタのドレイン端子が入力に接続され前記第１、第２
の各カスコード回路と逆極性の第３、第４のカスコード
回路と、前記第１、第２のカスコード回路の出力が入力
された第１のシングルエンド変換回路と、前記第３、第
４のカスコード回路の出力がそれぞれ入力された第２の
シングルエンド変換回路と、前記第１、第２のシングル
エンド変換回路の各々の出力が入力されその出力端が出
力端子に接続された第３のシングルエンド変換回路とを
有することを特徴とする演算増幅回路。A first differential pair in which the gates of two transistors are respectively connected to first and second input terminals, and each of the first and second drain outputs of this first differential pair is connected to an input terminal. a first differential pair connected to each other and having opposite polarity to the first differential pair;
A second cascode circuit, first and second common source transistors whose gate terminals are connected to the inputs of the first and second cascode circuits, and drain terminals of the first and second transistors that are inputted. connected to said first and second
a first single-ended conversion circuit into which the outputs of the first and second cascode circuits are input, and the third and fourth cascode circuits. a second single-ended conversion circuit into which the outputs of the circuits are inputted, and a third single-ended conversion circuit into which the outputs of the first and second single-ended conversion circuits are inputted and whose output ends are connected to the output terminals. An operational amplifier circuit comprising a conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200608A JPH0834391B2 (en) | 1989-08-01 | 1989-08-01 | Operational amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200608A JPH0834391B2 (en) | 1989-08-01 | 1989-08-01 | Operational amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0364108A true JPH0364108A (en) | 1991-03-19 |
| JPH0834391B2 JPH0834391B2 (en) | 1996-03-29 |
Family
ID=16427198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1200608A Expired - Lifetime JPH0834391B2 (en) | 1989-08-01 | 1989-08-01 | Operational amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834391B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998020610A1 (en) * | 1996-11-01 | 1998-05-14 | Burr-Brown Corporation | Low-impedance cmos output stage and method |
| WO2002021682A1 (en) * | 2000-09-08 | 2002-03-14 | Neo Tek Research Co., Ltd | High gain low power op amp for driving the flat panel display |
| US6570449B2 (en) * | 2000-10-13 | 2003-05-27 | Seiko Epson Corporation | Operation amplification circuit, constant voltage circuit and reference voltage circuit |
| US7222667B2 (en) | 2004-10-28 | 2007-05-29 | Honda Motor Co., Ltd. | Vehicular air-conditioning apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4713560B2 (en) * | 2007-10-29 | 2011-06-29 | 富士通セミコンダクター株式会社 | Differential amplifier circuit |
-
1989
- 1989-08-01 JP JP1200608A patent/JPH0834391B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998020610A1 (en) * | 1996-11-01 | 1998-05-14 | Burr-Brown Corporation | Low-impedance cmos output stage and method |
| US5856749A (en) * | 1996-11-01 | 1999-01-05 | Burr-Brown Corporation | Stable output bias current circuitry and method for low-impedance CMOS output stage |
| US6002276A (en) * | 1996-11-01 | 1999-12-14 | Burr-Brown Corporation | Stable output bias current circuitry and method for low-impedance CMOS output stage |
| WO2002021682A1 (en) * | 2000-09-08 | 2002-03-14 | Neo Tek Research Co., Ltd | High gain low power op amp for driving the flat panel display |
| US6570449B2 (en) * | 2000-10-13 | 2003-05-27 | Seiko Epson Corporation | Operation amplification circuit, constant voltage circuit and reference voltage circuit |
| US7222667B2 (en) | 2004-10-28 | 2007-05-29 | Honda Motor Co., Ltd. | Vehicular air-conditioning apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0834391B2 (en) | 1996-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000183671A (en) | Amplifier having dynamic compensation and method | |
| US5444363A (en) | Low noise apparatus for receiving an input current and producing an output current which mirrors the input current | |
| EP1980017A1 (en) | Amplifier circuit | |
| JPH0364108A (en) | Operational amplifier circuit | |
| US5994960A (en) | High speed switched op-amp for low supply voltage applications | |
| JPS63288512A (en) | Analog voltage comparator | |
| EP0403174A3 (en) | Differential amplifying circuit operable at high speed | |
| JPS6021605A (en) | Dmos high gain amplifier utilizing positive feedback | |
| US6496066B2 (en) | Fully differential operational amplifier of the folded cascode type | |
| JP2001111419A (en) | Charge pump circuit | |
| JPH03286606A (en) | Operational amplifier circuit | |
| JP2565195B2 (en) | Chopper type comparator | |
| US5337009A (en) | Error amplifier | |
| JPH07321563A (en) | Low distortion output stage | |
| JPH0355906A (en) | Operational amplifier circuit | |
| JP2765331B2 (en) | Level conversion circuit | |
| JP2570575B2 (en) | Flip-flop circuit | |
| CN116633342B (en) | Conversion circuit from CML (complementary metal oxide semiconductor) to CMOS (complementary metal oxide semiconductor) level with optimized duty ratio | |
| JPH03292007A (en) | Operational amplifier circuit | |
| JPH0787313B2 (en) | Operational amplifier circuit | |
| JP3282408B2 (en) | Operational amplifier | |
| JPH0574962B2 (en) | ||
| JPH05283950A (en) | Operational amplifier | |
| KR0157114B1 (en) | 2-phase continuation comparator | |
| JPH08307164A (en) | Operational amplifier circuit |