JPH0357235A - Designing method for semiconductor element - Google Patents

Designing method for semiconductor element

Info

Publication number
JPH0357235A
JPH0357235A JP1193022A JP19302289A JPH0357235A JP H0357235 A JPH0357235 A JP H0357235A JP 1193022 A JP1193022 A JP 1193022A JP 19302289 A JP19302289 A JP 19302289A JP H0357235 A JPH0357235 A JP H0357235A
Authority
JP
Japan
Prior art keywords
chip
positions
lead frame
electrode pads
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1193022A
Other languages
Japanese (ja)
Inventor
Nobuyuki Mori
森　伸之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1193022A priority Critical patent/JPH0357235A/en
Publication of JPH0357235A publication Critical patent/JPH0357235A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To easily mount a semiconductor element on different packages by a method wherein a figure data of a chip is input to a CAD apparatus, a wiring standard is compared and judged and common positions of pads to be connected on a lead frame and on the semiconductor element are designed. CONSTITUTION:An external-shape data of a semiconductor chip 3 is input to a CAD apparatus. The chip 3 is mounted on a mounting part of a lead frame; temporarily set imaginary electrode pad positions of a pad arrangement line 5 connected to the center of electrode pads of the chip 3 are connected to inner leads 1 corresponding to them. Then, temporarily wired lines are compared with a wiring standard regarding whether they are within a prescribed length or whether an inclination angle to a horizontal line of interconnections is within a prescribed value; it is judged whether they are within a prescribed value. A connectable range 4 which is set by the electrode pads to be connected to the individual leads 1 is decided. Then, positions of the electrode pads, i.e., pad coordinates 6, are set in positions to make the interconnections shortest in a position range common to the lead frame. Thereby, it is possible to obtain an element which can be mounted on different packages.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子設計法に関し、特に、半導体素子に
おける入出力端子である電極パッドの配置設計に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for designing a semiconductor device, and particularly to a layout design of electrode pads that are input/output terminals in a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の半導体素子設計法は、まず、ＣＡＤ（Ｃ
ｏｍｐｕｔｏｒ　　Ａｉｄｅｄ　　Ｄｅｓｉｇｎ）によ
り回路・論理設計を行ない、引き続き、ＣＡＤにより、
製造の際に使用するパターン設計である論理回路素子の
配置及び配線の引き回し等のレイアウト設計で行なわれ
ている。Conventionally, this type of semiconductor device design method first began with CAD (C
Perform circuit/logic design using computer aided design, and then continue with CAD.
This is done in the layout design of the arrangement of logic circuit elements and the routing of wiring, which is pattern design used during manufacturing.

また、半導体チップの入出力端子である電極パッドは、
前述の設計の際に、自動的に決められるので、半導体チ
ップを乗せるリードフレームに関しては、その半導体チ
ップの外形とか、電極パッドの数などから搭載できるよ
うにリードフレームが設計されていた。In addition, the electrode pads, which are the input and output terminals of semiconductor chips,
Since this is automatically determined during the above-mentioned design process, the lead frame on which the semiconductor chip is mounted is designed based on the external shape of the semiconductor chip, the number of electrode pads, etc.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、従来の半導体素子設計では、電極パッド
の位置座標は、あらかじめレイアウト設計で決定されて
いるので、半導体チップ毎にその半導体チップに合うリ
ードフレームを選定するか、あるいは設計していたため
、多大な設計工数を必要といていた欠点があった。特に
、近年、パッケージの多様化に伴ない、数種の相異なる
外形の半痺体装置の要求が急増しており、益々、数種の
リードフレームを設計しなければならないといった欠点
もあった． 本発明の目的は、かかる問題を解消する半導体素子設計
法を提供することである。However, in conventional semiconductor device design, the position coordinates of electrode pads are determined in advance in the layout design, so a lead frame that matches each semiconductor chip must be selected or designed, which requires a large amount of effort. The drawback was that it required a lot of design man-hours. In particular, in recent years, with the diversification of packages, the demand for hemiplegia devices with several different external shapes has rapidly increased, and this has led to the drawback that it is increasingly necessary to design several types of lead frames. An object of the present invention is to provide a semiconductor device design method that solves this problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体素子設計法は、少なくとも二つのリード
フレームの図形データと一つの半導体チップの図形デー
タをＣＡＤ装置に入力する工程と、それぞれの前記リー
ドフレームの結線すべき接続点を基点として前記半導体
チップの電極パッド配列ライン上に結線可能範囲をワイ
ヤリング基準により設定する工程と、この工程で得られ
たそれぞれの結線可能範囲より共通する結線可能範囲を
設定し、前記半導体チップ上の電極パッド位置を設計す
る工程とを含んで横或される。The semiconductor device design method of the present invention includes a step of inputting graphic data of at least two lead frames and graphic data of one semiconductor chip into a CAD device, and a step of inputting the graphic data of at least two lead frames and the graphic data of one semiconductor chip into a CAD device, and A process of setting a connectable range on the electrode pad array line of the chip using wiring standards, and setting a common connectable range from each connectable range obtained in this process, and determining the electrode pad position on the semiconductor chip. The process includes a designing process.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）及び（ｃ）は本発明の半導体素子
設計法の一実施例を説明するための半導体素子を示す平
面図、第２図は本発明の半導体素子設計法の一実施例を
説明するためのフローチャートである。ここで、この実
施例を理解し易いために、、第１図（ａ）及び（ｂ）に
示すように、二種類のリードフレームがあると仮定する
。1(a), (b), and (c) are plan views showing a semiconductor device for explaining one embodiment of the semiconductor device design method of the present invention, and FIG. 2 is a plan view showing a semiconductor device design method of the present invention. It is a flowchart for explaining one example. Here, in order to easily understand this embodiment, it is assumed that there are two types of lead frames, as shown in FIGS. 1(a) and 1(b).

この半導体素子設計法は、まず、第１図（ａ＞に示すリ
ードフレーム及び半導体チップ３の外形データ（ＸＹ座
標値）を、第２図に示すように、〔リードフレーム図形
データ入力〕及び〔半導体チップ図形データ入力〕で、
ＣＡＤ装置に入力する。次に、〔リードフレームと半導
体チップとを結線〕で、ＣＡＤ装置によりシミュレーシ
ョンを行ない、リードフレームの搭載部２に半導体チッ
プ３を搭載し、半導体チップ３の電極パッドの中心を結
ぶパッド配列ライン５の仮りに設定した架空電極パッド
位置とこれに対応するインナーリード１とを結線する。In this semiconductor element design method, first, the external shape data (XY coordinate values) of the lead frame and semiconductor chip 3 shown in FIG. Semiconductor chip figure data input]
Input into CAD device. Next, in [Connecting the lead frame and the semiconductor chip], a simulation is performed using a CAD device, and the semiconductor chip 3 is mounted on the mounting portion 2 of the lead frame, and the pad array line 5 connecting the centers of the electrode pads of the semiconductor chip 3 is The tentatively set aerial electrode pad position and the corresponding inner lead 1 are connected.

次に、〔ワイヤリング基準を満足するか〕で、仮りに配
線した線が、所定の長さ以内かあるいは配線の水平線に
対する傾き角度が所定値以内かといったワイヤリング基
準と比較し、その所定値内にあるか否かを判断する。も
し、ワイヤリング基準に適合していなければ、架空電極
パッドの位置をずらして再度結線する。このようにして
、〔電極パッドの位置範囲を設定〕で、各インナーリー
ド１と結線すべく電極パッドの設定する位置の範囲、す
なわち、結線可能範囲４が決められる。Next, in [Does the wiring standard meet?], compare the hypothetically wired wire with the wiring standard, such as whether the length is within a predetermined length or whether the inclination angle of the wiring with respect to the horizontal line is within a predetermined value. Determine whether it exists or not. If the wiring standards are not met, relocate the aerial electrode pads and reconnect. In this way, in [Setting the position range of electrode pads], the range of positions of the electrode pads to be connected to each inner lead 1, that is, the possible connection range 4 is determined.

一方、第１図（ｂ）に示すリードフレームも同様の工程
を経て、結線可能範囲４ａを求める。次に、〔（ａ）、
（ｂ）の電極パッドのそれぞれの位置範囲により電極パ
ッドの位置設定〕で、第１図（ｃ）に示すように、第ｌ
図（ａ）及び（ｂ）に示すリードフレームに共通した位
置範囲で最も配線の短くなる位置に電極パッドの位置、
すなわち、パッド座標６を設定する。On the other hand, the lead frame shown in FIG. 1(b) is also subjected to the same process to determine the connectable range 4a. Next, [(a),
(b), the positions of the electrode pads are set according to the respective position ranges of the electrode pads], as shown in FIG.
The electrode pad is located at the position where the wiring is the shortest in the common position range of the lead frames shown in Figures (a) and (b).
That is, pad coordinate 6 is set.

以上説明した実施例は二つの異なったリードフレームで
説明したが、異なったリードフレームが二つ以上あって
も同様にこの実施例の設計法を行なえば、違ったパッケ
ージに実装出来る半導体素子が得られるという利点があ
る。Although the embodiment described above has been explained using two different lead frames, if the design method of this embodiment is applied in the same way even if there are two or more different lead frames, a semiconductor element that can be mounted in different packages can be obtained. It has the advantage of being able to

第３図（ａ）及び（ｂ）は本発明の半導体素子設計法の
一実施例を利用して設計した場合を説明するための半導
体素子を示す平面図である。また、前述の場合と異なり
、例えば、第３図（ａ＞及び（ｂ）に示すように、半導
体チップ３上に、結線可能範囲４ｂ及び４ｃが設定され
る以外に、電極パッドが回路設計上で固定される固定バ
ッド７が存在する場合は、第２図に示す、サブルーチン
動作をバイパスして電極パッド位置設計することも出来
る。FIGS. 3(a) and 3(b) are plan views showing a semiconductor device designed using an embodiment of the semiconductor device design method of the present invention. Moreover, unlike the above case, for example, as shown in FIG. If there is a fixed pad 7 fixed in place, the electrode pad position can be designed by bypassing the subroutine operation shown in FIG.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＣＡＤ装置に半導体チッ
プの図形データ及び使用する二つ以上のリードフレーム
の図形データとを入力し、それぞれのリードフレームの
接続点を基点にして、ワイヤリング基準を比較判断し、
リードフレームと半導体素子上の接続すべき電極パッド
の共通位置を設計することによって、異なったリードフ
レームに搭載出来る半導体素子設計法が得られるという
効果がある。As explained above, the present invention inputs graphic data of a semiconductor chip and graphic data of two or more lead frames to be used into a CAD device, and compares wiring standards using the connection points of each lead frame as a base point. judge,
By designing the common position of the lead frame and the electrode pads to be connected on the semiconductor element, there is an effect that a semiconductor element design method that can be mounted on different lead frames can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａｍ　　（ｂ）及び（ｃ）は本発明の半導体素
子設計法の一実施例を説明するための半導体素子を示す
平面図、第２図は本発明の半導体素子設計法の一実施例
を説明するためのフローチャート、第３図（ａ）及び（
ｂ）は本発明の半導体素子設計法の一実施例を利用して
設計した場合を説明するための半導体素子を示す平面図
である．１・・・インナーリード、２・・・塔載部、３
・・・半導体チップ、４、４ａ、４ｂ、４Ｃ・・・結線
可能範囲、５・・・パッド配列ライン、６・・・パッド
座標、７・・・固定パッド。FIG. 1 (b) and (c) are plan views showing a semiconductor device for explaining one embodiment of the semiconductor device design method of the present invention, and FIG. 2 is an implementation of the semiconductor device design method of the present invention. Flowcharts for explaining examples, FIGS. 3(a) and (
b) is a plan view illustrating a semiconductor device designed using an embodiment of the semiconductor device design method of the present invention; 1... Inner lead, 2... Tower mounting part, 3
... Semiconductor chip, 4, 4a, 4b, 4C... Connection possible range, 5... Pad array line, 6... Pad coordinates, 7... Fixed pad.

Claims (1)

【特許請求の範囲】[Claims] 少なくとも二つのリードフレームの図形データと一つの
半導体チップの図形データをＣＡＤ装置に入力する工程
と、それぞれの前記リードフレームの結線すべき接続点
を基点として前記半導体チップの電極パッド配列ライン
上に結線可能範囲をワイヤリング基準により設定する工
程と、この工程で得られたそれぞれの結線可能範囲より
共通する結線可能範囲を設定し、前記半導体チップ上の
電極パッド位置を設計する工程とを含んでいることを特
徴とする半導体素子設計方法。A step of inputting graphic data of at least two lead frames and graphic data of one semiconductor chip into a CAD device, and connecting each of the lead frames on the electrode pad array line of the semiconductor chip using the connection point to be connected as a base point. The method includes a step of setting a possible range based on a wiring standard, and a step of setting a common connectable range from the respective connectable ranges obtained in this step and designing electrode pad positions on the semiconductor chip. A semiconductor device design method characterized by:
JP1193022A 1989-07-25 1989-07-25 Designing method for semiconductor element Pending JPH0357235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1193022A JPH0357235A (en) 1989-07-25 1989-07-25 Designing method for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1193022A JPH0357235A (en) 1989-07-25 1989-07-25 Designing method for semiconductor element

Publications (1)

Publication Number Publication Date
JPH0357235A true JPH0357235A (en) 1991-03-12

Family

ID=16300874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1193022A Pending JPH0357235A (en) 1989-07-25 1989-07-25 Designing method for semiconductor element

Country Status (1)

Country Link
JP (1) JPH0357235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784171A (en) * 1992-06-24 1998-07-21 Sony Corporation Printing method, printing device, printing head, container vessel for containing printing object and printing method for cassettes

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784171A (en) * 1992-06-24 1998-07-21 Sony Corporation Printing method, printing device, printing head, container vessel for containing printing object and printing method for cassettes
US5815282A (en) * 1992-06-24 1998-09-29 Sony Corporation Cassette having color-printed recessed and conveyed surfaces

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