JPH04129250A - Thin type hybrid integrated circuit substrate - Google Patents

Thin type hybrid integrated circuit substrate

Info

Publication number
JPH04129250A
JPH04129250A JP2250588A JP25058890A JPH04129250A JP H04129250 A JPH04129250 A JP H04129250A JP 2250588 A JP2250588 A JP 2250588A JP 25058890 A JP25058890 A JP 25058890A JP H04129250 A JPH04129250 A JP H04129250A
Authority
JP
Japan
Prior art keywords
ground
semiconductor
terminal
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2250588A
Other languages
Japanese (ja)
Inventor
Shigemi Nakamura
中村　茂美
Masaaki Ishido
石藤　正昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2250588A priority Critical patent/JPH04129250A/en
Publication of JPH04129250A publication Critical patent/JPH04129250A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a substrate, in which conductor patterns are arranged easily and which has general-purpose properties, by forming electrically insulated double loop-shaped conductor patterns surrounding a semiconductor IC chip mounting section and connecting a power terminal to one of the double loop- shaped conductor patterns and a ground terminal to the other. CONSTITUTION:When a power terminal 5 is used as a power supply and a ground terminal 6 as a ground in common and semiconductor IC chips 1 are designed as a leadless type thin-type hybrid integrated circuit device, all gold wires 2 are connected to either one of loop-shaped conductor patterns 4 formed around the semiconductor IC chips 1 respectively, and connected to the power terminal 5 and the ground terminal 6 by the bonding of the gold wires 2 in the vicinity of the power terminal 5 or the ground terminal 6 on the conductor patterns 4. Accordingly, even when the pads for the power supply or pads for the ground of the mounted semiconductor IC chips 1 are dispersed into approximately two or four respectively, the power supply and ground of the hybrid integrated circuit device can be set at the positions of specified power terminal 5 and ground terminal 6.

Description

【発明の詳細な説明】 〔産業上の利用分舒〕 本発明は薄型混成集積回路基板に関し、特にゲートアレ
ー等のパッド配置が可変である半導体ＩＣチップを搭載
するリードレスタイプの薄型混成集積回路基板に関する
。[Detailed Description of the Invention] [Industrial Application] The present invention relates to a thin hybrid integrated circuit board, and particularly to a leadless type thin hybrid integrated circuit mounted with a semiconductor IC chip having variable pad arrangement such as a gate array. Regarding the board.

〔従来の技術〕[Conventional technology]

従来、この種の薄型混成集積回路装置は、表面に搭載し
た少くとも１個の半導体ＩＣチップのパッドと薄型混成
集積回路基板（以下基板と記す）上の導体パターンとを
金線でボンディングする事により接続し、そこから基板
上の外部接続用パッドに引き出され、最後に、樹脂封止
されるという構造になっている。Conventionally, this type of thin hybrid integrated circuit device involves bonding the pads of at least one semiconductor IC chip mounted on the surface with a conductor pattern on a thin hybrid integrated circuit board (hereinafter referred to as "substrate") using gold wire. It has a structure in which it is connected to the external connection pad on the board, and finally it is sealed with resin.

この薄型混成集積回路装置を赤外線等のりフロ一方式か
レーザ一方式、あるいは、こて付は等によりセットのマ
ーデーボート上に半田付けにより接続して搭載している
。This thin hybrid integrated circuit device is mounted on the set's Marde boat by soldering using one type of adhesive such as infrared rays, one type of laser beam, or one type using a soldering iron.

この方法を用いると、従来の超小型モールドタイプのＩ
Ｃパッケージを用いるより３０〜５０％実装体積が低減
され、開発費及び製品単価も１／２以下で済む利点もあ
る。Using this method, the conventional ultra-small mold type I
It has the advantage that the mounting volume is reduced by 30 to 50% compared to using the C package, and the development cost and product unit price are reduced to less than half.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の基板を用いた混成集積回路装置では、基板上
の配線パターンが単純な形状に形成されているため、搭
載する半導体ＩＣチップのバッド配線の順番が、そのま
ま、基板の端子配置となっている。このため、ゲートア
レー等のように同一下地でパッド配置が可変な半導体Ｉ
Ｃチップを用いる場合は、半導体ＩＣチップの製品のコ
ード毎に全端子の配置が異なり、特に、電源端子とグラ
ンド端子が複数の全く異なる端子に設定される場合が多
くある。In this hybrid integrated circuit device using a conventional board, the wiring pattern on the board is formed in a simple shape, so the order of the pad wiring of the semiconductor IC chip to be mounted is the same as the terminal arrangement of the board. There is. For this reason, semiconductor ICs with variable pad placement on the same base, such as gate arrays, etc.
When using a C chip, the arrangement of all terminals differs depending on the code of the semiconductor IC chip product, and in particular, the power supply terminal and the ground terminal are often set to a plurality of completely different terminals.

このため、この薄型混成集積回路装置を搭載するメイン
ボード上の導体パターンの配線では、複数の電源端子あ
るいはグランド端子を接続するために、他の信号の導体
パターンの配置が極めて困難になるという問題点があっ
た。For this reason, when wiring conductor patterns on the main board on which this thin hybrid integrated circuit device is mounted, there is a problem in that it is extremely difficult to arrange conductor patterns for other signals in order to connect multiple power supply terminals or ground terminals. There was a point.

また、製品のＢＴスクリーニング用用具具検査治具も電
源端子あるいはグランド端子が異なるために半導体ＩＣ
チップのコード毎に用意する必要があるという問題点が
あった。In addition, the inspection jig for BT screening of products also has different power terminals or ground terminals, so
There was a problem in that it was necessary to prepare each code for each chip.

本発明の目的は、導体パターンの配置が容易で、汎用性
のある基板を提供することにある。An object of the present invention is to provide a versatile board on which conductor patterns can be easily arranged.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、少くとも１個の半導体ＩＣチップを搭載する
リードレスタイプの薄型混成集積回路基板において、前
記半導体ＩＣチップ搭載部を取囲む電気的に絶縁された
二重のループ状の導体パターンを設け、該二重のループ
状の導体パターンのうちの一方には電源端子を、他方に
はグランド端子を接続したことを特徴とする。The present invention provides a leadless type thin hybrid integrated circuit board on which at least one semiconductor IC chip is mounted, including an electrically insulated double loop conductor pattern surrounding the semiconductor IC chip mounting portion. A power terminal is connected to one of the double loop-shaped conductor patterns, and a ground terminal is connected to the other.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第１の実施例の基板に半導体ＩＣチッ
プを搭載した平面図である。FIG. 1 is a plan view of a semiconductor IC chip mounted on a substrate according to a first embodiment of the present invention.

第１の実施例は、第１図に示すように、電源端子５を電
源、グランド端子６をグランドとすることを共通とする
ことにしである。In the first embodiment, as shown in FIG. 1, the power terminal 5 is used as a power source, and the ground terminal 6 is used as a ground.

電源パッド及びグランドパッドが２個、４個あるゲート
アレーの半導体ＩＣチップ１をリードレスタイプの薄型
混成集積回路装置として設計する場合には、搭載する半
導体ＩＣチップ１の電源パッドあるいはグランドパッド
からの金線２は、それぞれ半導ＩＣＣチア１周囲に設置
したループ状導体パターン４のいずれか一方に全て接続
し、その導体パターン４上の電源端子５あるいはグラン
ド端子６の付近で金線２のボンディングにより電源端子
５とグランド端子６に接続する。When designing a gate array semiconductor IC chip 1 with two or four power supply pads and four ground pads as a leadless type thin hybrid integrated circuit device, the power supply pad or ground pad of the semiconductor IC chip 1 to be mounted is The gold wires 2 are all connected to either one of the loop-shaped conductor patterns 4 installed around the semiconductor ICC cheer 1, and the gold wires 2 are bonded near the power terminal 5 or ground terminal 6 on the conductor pattern 4. It is connected to the power supply terminal 5 and the ground terminal 6 by.

この結果、搭載半導体ＩＣチップ１の電源用パッドある
いはグランド用パッドが、それぞれ２個あるいは４個位
が分散してあっても、混成集積回路装置の電源およびグ
ランドは、所定の電源端子５及びグランド端子６の位置
に設定できる。このため、薄型混成集積回路装置を搭載
するメインボード上の配線パターン設計が大変容易にな
った。As a result, even if the power supply pads or ground pads of the mounted semiconductor IC chip 1 are dispersed, two or four each, the power supply and ground of the hybrid integrated circuit device are connected to the predetermined power supply terminal 5 and the ground. It can be set at the position of terminal 6. Therefore, it has become very easy to design the wiring pattern on the main board on which the thin hybrid integrated circuit device is mounted.

また、ＢＴスクリーニング用用具具電源・グランド以外
は全端子抵抗（２２にΩ）を通してプルアップした。こ
のために、本実施例の基板を用いて混成集積回路装置を
組立てた場合には、治具を共通に使用できる。In addition, all terminals except the power supply and ground of the BT screening tool were pulled up through resistance (22Ω). Therefore, when a hybrid integrated circuit device is assembled using the substrate of this embodiment, a jig can be used in common.

第２図は本発明の第２の実施例の基板に半導ＩＣチップ
を搭載した平面図である。FIG. 2 is a plan view of a semiconductor IC chip mounted on a substrate according to a second embodiment of the present invention.

第２の実施例は、第２図に示すように、第１の実施例と
は異なり、半導体ＩＣＣチア１周囲のループ状導体パタ
ーン４のそれぞれとあらかじめ決めである電源端子５あ
るいはグランド端子６との接続は、金線によるボンディ
ングでは無く、スルーホールを用いた第２層導体７で実
施するものである。As shown in FIG. 2, the second embodiment differs from the first embodiment in that each of the loop-shaped conductor patterns 4 around the semiconductor ICC cheer 1 is connected to a predetermined power supply terminal 5 or ground terminal 6. The connection is not made by gold wire bonding but by the second layer conductor 7 using through holes.

このようにすると、第１の実施例に比べて金線のボンデ
ィングの本数が少なくて済み、その分原価低減や信頼性
向上が期待できる。In this way, the number of gold wires required for bonding is smaller than in the first embodiment, and cost reduction and reliability improvement can be expected accordingly.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、搭載する半導体ＩＣチッ
プの周囲に、二重にループ状の導体パターンを設け、そ
れぞれの導体パターンをグランドと電源の共通パターン
として使用して薄型混成集積回路装置の任意の端子に引
き出す事により、パッドが全く一致していないゲートア
レー等の半導体ＩＣチップを搭載しても、薄型混成集積
回路装置の外形寸法及び電源・グランド端子を規格化す
る事ができ汎用性を持たせる効果がある。As explained above, the present invention provides a double loop-shaped conductor pattern around a semiconductor IC chip to be mounted, and uses each conductor pattern as a common pattern for ground and power to create a thin hybrid integrated circuit device. By pulling out to any terminal, it is possible to standardize the external dimensions and power/ground terminals of the thin hybrid integrated circuit device even if semiconductor IC chips such as gate arrays whose pads do not match at all are mounted, making it versatile. It has the effect of giving

これにより、マザーボード上の配線パターンの引き回し
が有利になるうえに、ＢＴスクリーニング治具や検査治
具に汎用性を持たせて、それぞれの薄型混成集積回路装
置の開発時の費用を大幅に削除する効果を有するもので
ある。This not only makes it easier to route the wiring patterns on the motherboard, but also makes BT screening jigs and inspection jigs more versatile, significantly reducing costs when developing each thin hybrid integrated circuit device. It is effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例の基板に半導体ＩＣチッ
プを搭載した平面図、第２図は本発明の第２の実施例の
基板に半導体ＩＣチップを搭載した平面図である。 １・・・半導体ＩＣチップ、２・・・金線、３・・・基
板、４・・・導体パターン、５・・・電源端子、６・・
・グランド端子、７・・・第２層導体、８・・・スルー
ホール。FIG. 1 is a plan view of a semiconductor IC chip mounted on a substrate according to a first embodiment of the present invention, and FIG. 2 is a plan view of a semiconductor IC chip mounted on a substrate according to a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor IC chip, 2... Gold wire, 3... Substrate, 4... Conductor pattern, 5... Power supply terminal, 6...
- Ground terminal, 7... Second layer conductor, 8... Through hole.

Claims (1)

【特許請求の範囲】[Claims] 少くとも１個の半導体ＩＣチップを搭載するリードレス
タイプの薄型混成集積回路基板において、前記半導体Ｉ
Ｃチップ搭載部を取囲む電気的に絶縁された二重のルー
プ状の導体パターンを設け、該二重のループ状の導体パ
ターンのうちの一方には電源端子を、他方にはグランド
端子を接続したことを特徴とする薄型混成集積回路基板
。In a leadless type thin hybrid integrated circuit board on which at least one semiconductor IC chip is mounted, the semiconductor I
An electrically insulated double loop conductor pattern is provided surrounding the C chip mounting area, and a power terminal is connected to one of the double loop conductor patterns, and a ground terminal is connected to the other. A thin hybrid integrated circuit board characterized by:
JP2250588A 1990-09-20 1990-09-20 Thin type hybrid integrated circuit substrate Pending JPH04129250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250588A JPH04129250A (en) 1990-09-20 1990-09-20 Thin type hybrid integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250588A JPH04129250A (en) 1990-09-20 1990-09-20 Thin type hybrid integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPH04129250A true JPH04129250A (en) 1992-04-30

Family

ID=17210124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250588A Pending JPH04129250A (en) 1990-09-20 1990-09-20 Thin type hybrid integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPH04129250A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04273153A (en) * 1991-02-27 1992-09-29 Nec Corp Semiconductor device
KR970053748A (en) * 1995-12-30 1997-07-31 황인길 Leadframe of Semiconductor Package
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US5801440A (en) * 1995-10-10 1998-09-01 Acc Microelectronics Corporation Chip package board having utility rings
US6034423A (en) * 1998-04-02 2000-03-07 National Semiconductor Corporation Lead frame design for increased chip pinout
US6734545B1 (en) 1995-11-29 2004-05-11 Hitachi, Ltd. BGA type semiconductor device and electronic equipment using the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04273153A (en) * 1991-02-27 1992-09-29 Nec Corp Semiconductor device
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US5801440A (en) * 1995-10-10 1998-09-01 Acc Microelectronics Corporation Chip package board having utility rings
US6734545B1 (en) 1995-11-29 2004-05-11 Hitachi, Ltd. BGA type semiconductor device and electronic equipment using the same
US7164194B2 (en) 1995-11-29 2007-01-16 Renesas Technology Corp. BGA type semiconductor device and electronic equipment using the same
US7291909B2 (en) 1995-11-29 2007-11-06 Renesas Technology Corp. BGA type semiconductor device and electronic equipment using the same
KR970053748A (en) * 1995-12-30 1997-07-31 황인길 Leadframe of Semiconductor Package
US6034423A (en) * 1998-04-02 2000-03-07 National Semiconductor Corporation Lead frame design for increased chip pinout

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