JPH0356134U - - Google Patents
Info
- Publication number
- JPH0356134U JPH0356134U JP1989116021U JP11602189U JPH0356134U JP H0356134 U JPH0356134 U JP H0356134U JP 1989116021 U JP1989116021 U JP 1989116021U JP 11602189 U JP11602189 U JP 11602189U JP H0356134 U JPH0356134 U JP H0356134U
- Authority
- JP
- Japan
- Prior art keywords
- bump
- opening
- electrode
- electrode pad
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の実施例を示すバンプ電極の断
面図、第２図は従来のバンプ電極の断面図、第３
図は本考案の使用例を示す図である。 １０……バンプ電極、１１……半導体基板、１
２……層間絶縁膜、１３……電極パツド、１４…
…絶縁保護膜、１５……Ａｌ層、１６……コンタ
クト金属膜、１７……バリア金属膜、１８……第
１のバンプ、１９……バンプ中間層、２０……第
２のバンプ。
面図、第２図は従来のバンプ電極の断面図、第３
図は本考案の使用例を示す図である。 １０……バンプ電極、１１……半導体基板、１
２……層間絶縁膜、１３……電極パツド、１４…
…絶縁保護膜、１５……Ａｌ層、１６……コンタ
クト金属膜、１７……バリア金属膜、１８……第
１のバンプ、１９……バンプ中間層、２０……第
２のバンプ。
Claims (1)
- 【実用新案登録請求の範囲】 半導体基板上に形成された電極パツドと、前記
半導体基板上に被着され、前記電極パツドの取り
だし用開孔部を有する絶縁保護膜と、前記開孔部
内に露出した前記電極パツド上に形成された金属
層と、前記金属層上に形成された外部接続用のバ
ンプとを、備えたバンプ電極において、 前記バンプは、 前記開孔部内に露出した前記金属層上に形成さ
れた第１のバンプと、 前記第１のバンプ上に被着されたバンプ中間層
と、 前記バンプ中間層上に形成されたリード接続用
の第２のバンプと、 を備え、前記バンプ中間層を前記第１および第２
のバンプより硬質な金属材料で形成したことを特
徴とするバンプ電極。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989116021U JPH0356134U (ja) | 1989-10-02 | 1989-10-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989116021U JPH0356134U (ja) | 1989-10-02 | 1989-10-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0356134U true JPH0356134U (ja) | 1991-05-30 |
Family
ID=31664328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989116021U Pending JPH0356134U (ja) | 1989-10-02 | 1989-10-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0356134U (ja) |
-
1989
- 1989-10-02 JP JP1989116021U patent/JPH0356134U/ja active Pending