JPH0353657B2 - - Google Patents
Info
- Publication number
- JPH0353657B2 JPH0353657B2 JP57000648A JP64882A JPH0353657B2 JP H0353657 B2 JPH0353657 B2 JP H0353657B2 JP 57000648 A JP57000648 A JP 57000648A JP 64882 A JP64882 A JP 64882A JP H0353657 B2 JPH0353657 B2 JP H0353657B2
- Authority
- JP
- Japan
- Prior art keywords
- cache
- memory
- data
- signal
- central processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 claims description 325
- 238000012545 processing Methods 0.000 claims description 43
- 230000002093 peripheral effect Effects 0.000 claims description 36
- 230000004044 response Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 2
- 230000000977 initiatory effect Effects 0.000 claims 2
- 230000004913 activation Effects 0.000 claims 1
- 238000013500 data storage Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 239000013256 coordination polymer Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 230000001343 mnemonic effect Effects 0.000 description 7
- 230000002401 inhibitory effect Effects 0.000 description 3
- 238000007726 management method Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 201000000760 cerebral cavernous malformation Diseases 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000032361 posttranscriptional gene silencing Effects 0.000 description 2
- 101710115643 Cathelicidin-1 Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013479 data entry Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000036316 preload Effects 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US22315481A | 1981-01-07 | 1981-01-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57169990A JPS57169990A (en) | 1982-10-19 |
JPH0353657B2 true JPH0353657B2 (fr) | 1991-08-15 |
Family
ID=22835271
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57000648A Granted JPS57169990A (en) | 1981-01-07 | 1982-01-07 | Processor for data |
Country Status (10)
Country | Link |
---|---|
JP (1) | JPS57169990A (fr) |
BE (1) | BE891723A (fr) |
CA (1) | CA1175581A (fr) |
CH (1) | CH656470A5 (fr) |
DE (1) | DE3200042A1 (fr) |
FR (1) | FR2497596B1 (fr) |
GB (1) | GB2090681B (fr) |
IT (1) | IT1154407B (fr) |
NL (1) | NL8200043A (fr) |
SE (1) | SE445270B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010095554A1 (fr) | 2009-02-20 | 2010-08-26 | 旭硝子株式会社 | Procédé de production d'électret, et élément de conversion du type à induction électrostatique |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS617967A (ja) * | 1984-06-15 | 1986-01-14 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | I/oコントロ−ラ |
AU5634086A (en) * | 1985-05-06 | 1986-11-13 | Wang Laboratories, Inc. | Information processing system with enhanced instruction execution and support control |
US4814981A (en) * | 1986-09-18 | 1989-03-21 | Digital Equipment Corporation | Cache invalidate protocol for digital data processing system |
DE3920883A1 (de) * | 1989-06-26 | 1991-01-03 | Siemens Ag | Verfahren und anordnung zur erhoehung der verarbeitungsgeschwindigkeit der zentraleinheit einer datenverarbeitungsanlage |
JPH03189845A (ja) * | 1989-12-13 | 1991-08-19 | Internatl Business Mach Corp <Ibm> | 階層メモリ・システムおよびキヤツシユ・メモリ・サブシステム |
JPH0756815A (ja) * | 1993-07-28 | 1995-03-03 | Internatl Business Mach Corp <Ibm> | キャッシュ動作方法及びキャッシュ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51148334A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | Buffer memory control method |
JPS5441291A (en) * | 1977-09-09 | 1979-04-02 | Sagami Chem Res Center | Cluster fixed substance, production thereof and catalyst |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3588829A (en) * | 1968-11-14 | 1971-06-28 | Ibm | Integrated memory system with block transfer to a buffer store |
US4169284A (en) * | 1978-03-07 | 1979-09-25 | International Business Machines Corporation | Cache control for concurrent access |
US4208716A (en) * | 1978-12-11 | 1980-06-17 | Honeywell Information Systems Inc. | Cache arrangement for performing simultaneous read/write operations |
GB2037039B (en) * | 1978-12-11 | 1983-08-17 | Honeywell Inf Systems | Cache memory system |
-
1981
- 1981-12-29 SE SE8107832A patent/SE445270B/sv not_active IP Right Cessation
-
1982
- 1982-01-04 DE DE19823200042 patent/DE3200042A1/de active Granted
- 1982-01-05 GB GB8200166A patent/GB2090681B/en not_active Expired
- 1982-01-06 IT IT67010/82A patent/IT1154407B/it active
- 1982-01-07 BE BE0/207010A patent/BE891723A/fr not_active IP Right Cessation
- 1982-01-07 NL NL8200043A patent/NL8200043A/nl unknown
- 1982-01-07 CA CA000393741A patent/CA1175581A/fr not_active Expired
- 1982-01-07 JP JP57000648A patent/JPS57169990A/ja active Granted
- 1982-01-07 CH CH78/82A patent/CH656470A5/de not_active IP Right Cessation
- 1982-01-07 FR FR828200156A patent/FR2497596B1/fr not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51148334A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | Buffer memory control method |
JPS5441291A (en) * | 1977-09-09 | 1979-04-02 | Sagami Chem Res Center | Cluster fixed substance, production thereof and catalyst |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010095554A1 (fr) | 2009-02-20 | 2010-08-26 | 旭硝子株式会社 | Procédé de production d'électret, et élément de conversion du type à induction électrostatique |
Also Published As
Publication number | Publication date |
---|---|
IT1154407B (it) | 1987-01-21 |
CA1175581A (fr) | 1984-10-02 |
GB2090681A (en) | 1982-07-14 |
SE8107832L (sv) | 1982-07-08 |
DE3200042C2 (fr) | 1991-03-07 |
BE891723A (fr) | 1982-04-30 |
FR2497596B1 (fr) | 1989-03-03 |
DE3200042A1 (de) | 1982-08-19 |
SE445270B (sv) | 1986-06-09 |
CH656470A5 (de) | 1986-06-30 |
NL8200043A (nl) | 1982-08-02 |
FR2497596A1 (fr) | 1982-07-09 |
IT8267010A0 (it) | 1982-01-06 |
JPS57169990A (en) | 1982-10-19 |
GB2090681B (en) | 1985-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4439829A (en) | Data processing machine with improved cache memory management | |
US4831520A (en) | Bus interface circuit for digital data processor | |
US5353415A (en) | Method and apparatus for concurrency of bus operations | |
US5787486A (en) | Bus protocol for locked cycle cache hit | |
JP3660679B2 (ja) | 高度パイプライン式バス・アーキテクチャ | |
US5463753A (en) | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller | |
KR100228940B1 (ko) | 메모리 일관성 유지 방법 | |
US4851991A (en) | Central processor unit for digital data processing system including write buffer management mechanism | |
CA1322058C (fr) | Systemes informatiques multiprocesseurs a memoire commune et a antememoires individuelles | |
US5774700A (en) | Method and apparatus for determining the timing of snoop windows in a pipelined bus | |
US4831581A (en) | Central processor unit for digital data processing system including cache management mechanism | |
US5659709A (en) | Write-back and snoop write-back buffer to prevent deadlock and to enhance performance in an in-order protocol multiprocessing bus | |
US5091845A (en) | System for controlling the storage of information in a cache memory | |
US5119484A (en) | Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction | |
US5226170A (en) | Interface between processor and special instruction processor in digital data processing system | |
USRE40921E1 (en) | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system | |
JPH0353657B2 (fr) | ||
US5276892A (en) | Destination control logic for arithmetic and logic unit for digital data processor | |
EP0302926B1 (fr) | Circuit de generation de signaux de commande pour unite arithmetique et logique pour un processeur numerique | |
JPH0816475A (ja) | マルチプロセッサシステム | |
AU617514B2 (en) | Multiple processor/cache memory system and data transaction control therefor | |
EP0418220B1 (fr) | Logique de commande de destination pour unite arithmetique et logique destinee a un processeur numerique de donnees | |
JPH058459B2 (fr) | ||
WO1988006763A1 (fr) | Unite centrale pour systeme informatique numerique incluant un circuit de traduction d'adresse virtuelle en adresse physique | |
JPH06324942A (ja) | 並列計算機システム |