GB2037039B - Cache memory system - Google Patents

Cache memory system

Info

Publication number
GB2037039B
GB2037039B GB7938170A GB7938170A GB2037039B GB 2037039 B GB2037039 B GB 2037039B GB 7938170 A GB7938170 A GB 7938170A GB 7938170 A GB7938170 A GB 7938170A GB 2037039 B GB2037039 B GB 2037039B
Authority
GB
United Kingdom
Prior art keywords
cache memory
memory system
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB7938170A
Other versions
GB2037039A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/968,312 external-priority patent/US4245304A/en
Priority claimed from US05/968,521 external-priority patent/US4208716A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2037039A publication Critical patent/GB2037039A/en
Application granted granted Critical
Publication of GB2037039B publication Critical patent/GB2037039B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
GB7938170A 1978-12-11 1979-11-05 Cache memory system Expired GB2037039B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/968,312 US4245304A (en) 1978-12-11 1978-12-11 Cache arrangement utilizing a split cycle mode of operation
US05/968,521 US4208716A (en) 1978-12-11 1978-12-11 Cache arrangement for performing simultaneous read/write operations

Publications (2)

Publication Number Publication Date
GB2037039A GB2037039A (en) 1980-07-02
GB2037039B true GB2037039B (en) 1983-08-17

Family

ID=27130509

Family Applications (2)

Application Number Title Priority Date Filing Date
GB7938170A Expired GB2037039B (en) 1978-12-11 1979-11-05 Cache memory system
GB08216967A Expired GB2114783B (en) 1978-12-11 1982-06-11 Cache arrangement utilizing a split cycle mode of operation

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB08216967A Expired GB2114783B (en) 1978-12-11 1982-06-11 Cache arrangement utilizing a split cycle mode of operation

Country Status (4)

Country Link
CA (1) CA1141040A (en)
DE (1) DE2949571A1 (en)
FR (1) FR2448189B1 (en)
GB (2) GB2037039B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2474201B1 (en) * 1980-01-22 1986-05-16 Bull Sa METHOD AND DEVICE FOR MANAGING CONFLICTS CAUSED BY MULTIPLE ACCESSES TO THE SAME CACH OF A DIGITAL INFORMATION PROCESSING SYSTEM COMPRISING AT LEAST TWO PROCESSES EACH HAVING A CACHE
SE445270B (en) * 1981-01-07 1986-06-09 Wang Laboratories COMPUTER WITH A POCKET MEMORY, WHICH WORKING CYCLE IS DIVIDED INTO TWO SUBCycles
DE3537115A1 (en) * 1985-10-18 1987-05-27 Standard Elektrik Lorenz Ag METHOD FOR OPERATING A DEVICE WITH TWO INDEPENDENT COMMAND INPUTS AND DEVICE WORKING ACCORDING TO THIS METHOD
JPH07122868B2 (en) * 1988-11-29 1995-12-25 日本電気株式会社 Information processing equipment
US5058116A (en) * 1989-09-19 1991-10-15 International Business Machines Corporation Pipelined error checking and correction for cache memories

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
FR129151A (en) * 1974-02-09
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4056845A (en) * 1975-04-25 1977-11-01 Data General Corporation Memory access technique
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4070706A (en) 1976-09-20 1978-01-24 Sperry Rand Corporation Parallel requestor priority determination and requestor address matching in a cache memory system

Also Published As

Publication number Publication date
DE2949571C2 (en) 1988-06-30
GB2037039A (en) 1980-07-02
GB2114783A (en) 1983-08-24
FR2448189A1 (en) 1980-08-29
CA1141040A (en) 1983-02-08
DE2949571A1 (en) 1980-06-19
FR2448189B1 (en) 1988-10-21
GB2114783B (en) 1984-01-11

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19931105