JPH0337730B2 - - Google Patents
Info
- Publication number
- JPH0337730B2 JPH0337730B2 JP56192293A JP19229381A JPH0337730B2 JP H0337730 B2 JPH0337730 B2 JP H0337730B2 JP 56192293 A JP56192293 A JP 56192293A JP 19229381 A JP19229381 A JP 19229381A JP H0337730 B2 JPH0337730 B2 JP H0337730B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- reactor
- chamber
- holder
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 62
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 21
- 230000007246 mechanism Effects 0.000 claims description 6
- 239000012808 vapor phase Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 description 51
- 239000007789 gas Substances 0.000 description 20
- 239000012535 impurity Substances 0.000 description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010891 electric arc Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- -1 silicon halide Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000001241 arc-discharge method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011437 continuous method Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005619 thermoelectricity Effects 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
本発明はグローまたはアーク放電を利用したプ
ラズマ気相法（PCVDと以下いう）により、安定
して再現性のよい半導体装置を多量に作製するた
めの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a manufacturing method for manufacturing semiconductor devices in large quantities with stability and good reproducibility by a plasma vapor phase method (hereinafter referred to as PCVD) using glow or arc discharge.
本発明はPCVD装置に対し、反応系に関しては
プラズマ気相法における反応性気体が導入される
反応筒内には電極その他のジグを設けず、被形成
面を有する基板とその基板ホルダ（例えば石英製
のボート）のみを導入し、反応性気体がラミナフ
ロー（層流）とせしめることにより被膜厚を均一
とし、さらに膜質もバツチ内、バツチ間でバラツ
キの少ない半導体膜を形成させるための製造方法
に関する。 The present invention provides a PCVD apparatus in which no electrodes or other jigs are provided in the reaction column into which reactive gases are introduced in the plasma vapor phase method, and a substrate having a surface to be formed and its substrate holder (for example, quartz) are provided. This invention relates to a manufacturing method for forming a semiconductor film with a uniform film thickness by introducing only a lamina flow of reactive gas, and with less variation in film quality within and between batches. .
一般にPCVD装置において、特に反応力の強い
珪素を主成分とする反応性気体であるシランまた
は珪素のハロゲン化物気体を用いる場合、反応筒
例えば石英ガラス管の内壁およびホルダに吸着し
た酸素（空気）および水分が珪化物気体と反応し
て、酸化珪素（低級酸化珪素）を作り、半導体と
しての導電性を悪くしていた。 Generally, in PCVD equipment, when using silane, which is a reactive gas mainly composed of silicon, which has particularly strong reactivity, or a silicon halide gas, oxygen (air) adsorbed on the inner wall and holder of a reaction tube, such as a quartz glass tube, and Moisture reacts with silicide gas to form silicon oxide (lower silicon oxide), which deteriorates the conductivity of semiconductors.
本発明はかかる酸素、水分の反応炉への導入を
防止するため、この反応筒に連絡して基板および
基板ホルダを保持または移動する機構を有する室
を設け、その生産性の向上および特性の再現性の
向上に務めた製造方法に関する。 In order to prevent such oxygen and moisture from being introduced into the reactor, the present invention provides a chamber that is connected to the reaction tube and has a mechanism for holding or moving the substrate and substrate holder, thereby improving productivity and reproducing the characteristics. Concerning a manufacturing method that improves performance.
さらに本発明はプラズマ放電電界が基板表面に
平行に（そつて）印加されるように電極を具備せ
しめ、活性の反応性生成物が被形成表面に垂直方
向に衝突して形成された半導体膜の特性を劣化さ
せてしまうことを防いでいることを他の目的とし
ている。この被形成面上へのスパツタ（損傷）の
防止は、例えば被形成面上にＰ型半導体層を設
け、その上面にＩ型（真性または実質的に真性）
の半導体層を作製しようとする時、Ｐ型を構成す
る不純物が1017〜1018cm-3の濃度にＩ層に混入し
てしまい、PI接合を劣化させてしまう。本発明
はかかる欠点を防ぐために示されたものである。 Furthermore, the present invention includes an electrode so that a plasma discharge electric field is applied parallel to the substrate surface, and the active reactive products collide perpendicularly to the surface of the substrate to form a semiconductor film. Another purpose is to prevent deterioration of characteristics. To prevent spatter (damage) on the surface to be formed, for example, a P-type semiconductor layer is provided on the surface to be formed, and an I-type (intrinsic or substantially intrinsic) semiconductor layer is formed on the upper surface.
When attempting to fabricate a semiconductor layer, impurities constituting the P type are mixed into the I layer at a concentration of 10 17 to 10 18 cm -3 , deteriorating the PI junction. The present invention has been proposed to prevent such drawbacks.
さらに本発明は前記した反応系よりなる第１の
反応系と、これに連結して第１の室を設け、この
第１の室に連結して第２の室を設け、さらにこの
第２の室に連結した第１の反応系と同様の第２の
反応系を設けた製造方法に関する。かかる製造方
法においては、まず第１の室にて真空引され、酸
素、水分が除去された雰囲気にて第１の反応炉に
基板およびホルダが移動機構により挿入され、こ
の反応炉にて一導電型例えばＰ型の導電型を有す
る半導体が形成された。さらにこの半導体が形成
された基板を再び第１の室に引出し、さらにこれ
に連結した第２の室へ同様に酸素、水分の全くな
い真空中にて移動される。さらにこの第２の室よ
り第２の反応炉に基板およびホルダーに導入さ
せ、第１の室とは異なる導電型または異なる添加
物またはその異なる濃度（不純物または添加物）
にて第２の半導体層を第１の半導体層上に形成さ
せることができる。 Furthermore, the present invention provides a first reaction system consisting of the reaction system described above, a first chamber connected to this, a second chamber connected to this first chamber, and further a second chamber connected to this first chamber. The present invention relates to a manufacturing method in which a second reaction system similar to the first reaction system is connected to a chamber. In this manufacturing method, first, a first chamber is evacuated and the substrate and holder are inserted into a first reactor by a moving mechanism in an atmosphere in which oxygen and moisture are removed, and one conductive conductor is inserted in this reactor. A semiconductor having a conductivity type, for example P type, was formed. Further, the substrate on which the semiconductor has been formed is taken out again to the first chamber, and further transferred to a second chamber connected thereto in a vacuum completely free of oxygen and moisture. Furthermore, the substrate and the holder are introduced into a second reactor from this second chamber, and a conductivity type different from that in the first chamber or a different additive or a different concentration thereof (impurity or additive) is introduced into the second reactor.
A second semiconductor layer can be formed on the first semiconductor layer.
この際、第１の反応炉の内壁に付着した不純物
が全く第２の半導体層を形成させる際付着するこ
とがないため、きわめて精度高く、導電率導電性
またはEg（エネルギバンド巾）等を制御すること
ができるようになつた。 At this time, impurities attached to the inner wall of the first reactor do not attach at all when forming the second semiconductor layer, so conductivity or Eg (energy band width) etc. can be controlled with extremely high precision. Now I can do it.
さらに本発明はさらにこの独立した反応炉を三
系統設け、これらを共通した室すなわち第１第２
および第３の室で互いに連結した製造装置におい
て、特に第１の反応炉にてＰ型半導体層を、第２
の反応炉にてＩ型半導体層を、さらに第３の反応
炉にてＮ型半導体層を形成して、PIN型のダイオ
ード特に光電変換装置を作製せんとする時、特に
有効である。 Furthermore, the present invention further provides three systems of these independent reactors, and connects them to a common chamber, i.e., the first, second, and
In particular, in a manufacturing apparatus connected to each other in a third chamber, a P-type semiconductor layer is formed in a first reactor, and a second
This method is particularly effective when a PIN type diode, particularly a photoelectric conversion device, is to be manufactured by forming an I type semiconductor layer in a second reactor and further forming an N type semiconductor layer in a third reactor.
本発明は積層するその層の数により共通した室
を介して反応炉をその積層する膜の順序に従つて
設けることにより、その段数を２段または３段の
みではなく、４〜10段にすることができる。かく
してPIN、PINPIN、PINIPIN、NIPIN、
PINIP、……等の接合構造に作ることができる。
またこの半導体層の作製の際、価の元素例えば
珪素に炭素またはゲルマニユームを添加し、その
添加量を制御することにより、添加量に比例、対
応した光学的エネルギバンド巾（Eg）を有せし
めることができる。例えばPIN接合をEgp、Egi、
Egn（Egp＞EgiEgn）としたＷ−Ｎ−Ｗ（広い
Eg−せまいEg−広いEg）として設けることを可
能とした。またさらにこのPIN接合を２つ積層し
て設けたPINPIN構造において、Egp1、Egi1、
Egn1、Egp2、Egi2、Egn2（Egp1＞Egn1Egi1
Egp2Egi2Egn2として設け、Egp1（2.0〜
2.4eV）、Egn1（1.7〜2.1eV）をSixc1-o（０＜ｘ＜
１）、Egi1、Egp1・（1.6〜1.8eV）をSiにより、
Egi2、Egn2（1.0〜1.5eV）をSixGe1-o（０＜ｘ＜
ｌ）として設けることが可能である。かかるタン
デム構造とするには反応系を６系統設ければよ
い。 The present invention increases the number of stages from 4 to 10 instead of only 2 or 3 by providing the reactor in the order of the films to be stacked through a common chamber depending on the number of layers to be stacked. be able to. Thus PIN, PINPIN, PINIPIN, NIPIN,
It can be made into a bonded structure such as PINIP, etc.
In addition, when producing this semiconductor layer, by adding carbon or germanium to a valent element such as silicon and controlling the amount of addition, it is possible to have an optical energy band width (Eg) proportional to and corresponding to the amount of addition. Can be done. For example, PIN junction is Egp, Egi,
W-N-W (wide) with Egn (Egp>EgiEgn)
Eg - narrow Eg - wide Eg). Furthermore, in the PINPIN structure in which two PIN junctions are stacked, Egp 1 , Egi 1 ,
Egn 1 , Egp 2 , Egi 2 , Egn 2 (Egp 1 > Egn 1 Egi 1
Set up as Egp 2 Egi 2 Egn 2 , Egp 1 (2.0 ~
2.4eV), Egn 1 (1.7~2.1eV) with Sixc 1-o (0<x<
1), Egi 1 , Egp 1・(1.6~1.8eV) by Si,
Egi 2 , Egn 2 (1.0~1.5eV) with SixGe 1-o (0<x<
l). To obtain such a tandem structure, six reaction systems may be provided.
またNINまたはPIN接合としたMIS・FET、
バイポーラトランジスタにおいては反応系を２系
統とし、第１の反応室により基板上にＮまたはＰ
層を、第２の反応系により次のＩ層を、さらに第
１の反応系に基板ホルダをもどして第３番目のＮ
またはＰ層を作製する三層構造を２系統にて作る
ことが可能である。 Also, MIS/FET with NIN or PIN junction,
In bipolar transistors, there are two reaction systems, and the first reaction chamber supplies N or P on the substrate.
layer, the next I layer by the second reaction system, and the third N layer by returning the substrate holder to the first reaction system.
Alternatively, it is possible to create a three-layer structure in which the P layer is created using two systems.
これら本発明は、反応炉を互いに連結するので
はなく、それぞれ独立した反応系を共通する室に
連結せしめ、この室を介して基板上に独立した半
導体層を形成させることを目的としている。 The object of the present invention is not to connect reactors to each other, but to connect independent reaction systems to a common chamber, and form independent semiconductor layers on a substrate via this chamber.
従来のPCVD装置に関しては、上下に平行平板
状に容量結合の電極を設け、その一方の電極例え
ば下側のカソード電極上に基板を配置し、下方向
より加熱する方法が知られている。しかしこの方
法においては、反応炉は一室であるためＰ型、Ｉ
型およびＮ型半導体層とを積層せんとすると、そ
の一回目の製造の後のＮ型半導体層の不純物が２
回目の次の工程のＰ型半導体層中に混入してしま
い、再結合中心となつてダイオード特性を劣化さ
せ、さらにその特性が全くばらついてしまつた。
このため光電変換装置を作ろうとしても、その開
放電圧Voc0.2〜0.6Vしか得られず、短絡電流を
数ｍＡ／cm2しか流すことができなかつた。 Regarding conventional PCVD apparatuses, a method is known in which capacitively coupled electrodes are provided in parallel flat plates above and below, a substrate is placed on one of the electrodes, for example, a lower cathode electrode, and the substrate is heated from below. However, in this method, since the reactor is one chamber, P type, I
When a type semiconductor layer and an N type semiconductor layer are stacked, the impurities in the N type semiconductor layer after the first manufacturing are 2.
It got mixed into the P-type semiconductor layer in the next step and became a recombination center, deteriorating the diode characteristics and causing the characteristics to vary completely.
For this reason, even if an attempt was made to make a photoelectric conversion device, an open circuit voltage Voc of only 0.2 to 0.6 V could be obtained, and a short circuit current of only a few mA/cm 2 could be passed.
加えてこの平行平板型の装置においては、電界
は基板表面に垂直方向であるため、Ｐ型層の後Ｉ
層を作らんとしても、このＩ層中にＰ層の不純物
が混入しやすく、ダイオード特性が出ない場合が
しばしば見られた。 In addition, in this parallel plate type device, the electric field is perpendicular to the substrate surface, so the I
Even if a layer is made, impurities from the P layer tend to mix into the I layer, and diode characteristics are often not achieved.
さらにこの反応装置は特に予備室を有していな
いため、１回製造するごとに反応炉の内壁を大気
（空気）にふれさせるため、酸素、水分が吸着し、
その吸着酸化物が反応中バツクグラウンドレベル
に存在するため、、電気伝導度が暗伝導度も10-11
〜10-8（Ωcm）-1、AM1での光伝導度も10-6〜10-4
（Ωcm）-1でしかなかつた。しかしこの吸着物が全
く存在しない装置を使つた本発明においては、暗
伝導度10-6〜10-4、AM1での光伝導度は、１×
10-3〜９×10-2（Ωcm）-1と約100倍も高く、半導
体的性質を有せしめることができた。本発明はか
くの如く従来多数用いられている平行平板型の一
室反応炉のPCVD装置のあらゆる欠点を除去せん
としたものである。 Furthermore, since this reactor does not have a preliminary chamber, the inner wall of the reactor is exposed to the atmosphere (air) every time it is manufactured, so oxygen and moisture are adsorbed.
Because the adsorbed oxide exists at the background level during the reaction, the electrical conductivity is 10 -11
~10 -8 (Ωcm) -1 , and the photoconductivity at AM1 is also 10 -6 ~10 -4
(Ωcm) It was only -1 . However, in the present invention, which uses an apparatus in which no adsorbed substances exist, the dark conductivity is 10 -6 to 10 -4 and the photoconductivity at AM1 is 1×
10 -3 to 9×10 -2 (Ωcm) -1 , which is approximately 100 times higher, allowing it to have semiconductor properties. The present invention is intended to eliminate all the drawbacks of the PCVD apparatus of the parallel plate type one-chamber reactor which has been used in large numbers in the past.
さらにこの従来の方式をさらに改良したもの
に、本発明人の出願になる独立分離型の反応装置
が知られている。この装置は、半導体装置作製方
法 昭和53年12月10日（53−152887）およびその
分割出願 半導体装置作製方法（56−055608）に
詳しく述べられている。さらに、被膜作製方法
昭和54年８月16日（54−104452）にもその詳細が
述べられている。 Furthermore, as a further improvement on this conventional system, an independent separation type reaction apparatus is known, which is filed by the present inventor. This device is described in detail in Method for Manufacturing a Semiconductor Device, December 10, 1972 (53-152887) and its divisional application Method for Manufacturing a Semiconductor Device (56-055608). Furthermore, the film preparation method
Details are also given on August 16, 1974 (54-104452).
これらの発明は、例えばPIN接合を有するダイ
オードを作製せんとする場合、Ｐ型半導体層用の
第１の反応系、Ｉ型半導体用の第２の反応系、さ
らにＮ型半導体層用の第３の反応系をそれぞれの
反応炉（ベルジヤー）をゲイトバルブにて連結し
たものである。かくすることによりＰ層の不純物
がＩ層に混入することがなく、またＮ層の不純物
がＩ層、Ｐ層に混入することがない。いわゆる各
半導体層での不純物制御を完全に精度よく行なう
ことができるという特徴を有する。さらにこのＰ
層用の反応炉の前またはＮ層用反応炉のあとに連
結して予備室を設け、いわゆる外部よりの酸素、
水蒸気の混入を防止しようとしたものである。 For example, when trying to fabricate a diode having a PIN junction, these inventions require a first reaction system for a P-type semiconductor layer, a second reaction system for an I-type semiconductor layer, and a third reaction system for an N-type semiconductor layer. This reaction system is constructed by connecting each reactor (Bergear) with a gate valve. This prevents impurities from the P layer from mixing into the I layer, and impurities from the N layer from mixing into the I and P layers. It has the characteristic that it is possible to control impurities in each semiconductor layer with complete precision. Furthermore, this P
A preliminary chamber is provided in front of the reactor for the layer or after the reactor for the N layer, and oxygen from the outside is supplied.
This was an attempt to prevent water vapor from entering.
しかしかかる本発明人の発明になるたて型のベ
ルジヤー式またはその変形の反応炉を互いに連結
した方式においては、基板の温度制御が十分に行
えない。すなわち300±20℃程度を有してしまつ
ていた。このため形成される被膜のバラツキが大
きく、好ましくなかつた。加えてひとつの反応炉
に充填できる基板の数量が例えば10cm□
で１〜10
まいであつた。このため生産性がきわめて低く、
いわゆる低価格、多量生産とはいえなかつた。 However, in the system invented by the present inventors in which reactors of the vertical Belgear type or a variation thereof are connected to each other, the temperature of the substrate cannot be sufficiently controlled. In other words, the temperature was approximately 300±20°C. For this reason, the formed coating had large variations, which was not preferable. In addition, the number of substrates that can be filled in one reactor is, for example, 1 to 10 at 10 cm□.
It was hot. As a result, productivity is extremely low.
It was not so-called low-priced, mass-produced products.
本発明はかかる本発明人の独立分離型の半導体
装置製造装置をさらに改良し、温度精度も300±
１℃以下におさえ、加えて１回のローデイング数
量を50〜500まいにすることを可能とした低価格、
高品質の半導体装置を多量に製造せんとするもの
である。 The present invention further improves the independent separation type semiconductor device manufacturing apparatus of the present inventor, and has a temperature accuracy of 300±.
Low price that can be kept below 1℃, and in addition, the number of loads per load can be reduced to 50 to 500.
The purpose is to manufacture high-quality semiconductor devices in large quantities.
以下に図面に従つてその実施例を示す。 Examples are shown below according to the drawings.
第１図は本発明の横型、独立分離式のプラズマ
CVD装置すなわち半導体装置製造装置の概要を
示す。 Figure 1 shows the horizontal, independent separation type plasma of the present invention.
An overview of a CVD device, that is, a semiconductor device manufacturing device is shown.
図面において第１の反応系１は円筒状の反応管
５例えば透明石英（アルミナその他のセラミツク
でもよい）であり、その直径は100〜300mmとし
た。さらにこの反応炉５の外側に一対のプラズマ
放電を行なわしめる電極２，２′を配置した。こ
の電極は例えばステンレス網よりなり、この電極
をおおつて抵抗加熱ヒータ３を設け、指示温度50
〜350℃例えば300℃に対し±１℃の精度にて制御
される。基板および基板ホルダは４で略記してお
り、反応性気体は６よりホモシナイザ２６をへて
供給される。一対の電極は供給用電源１３により
高周波（10KHz〜100MHz代表的には13.56MHzが
５〜200Wの強さにて供給される。反応後の不要
の生成物およびヘリユーム、水素等のキヤリアガ
スは、排気口１３より反応管内の圧力調整用バル
ブ１４をへてロータリーポンプ１５にて排出され
る。 In the drawing, the first reaction system 1 is a cylindrical reaction tube 5 made of, for example, transparent quartz (alumina or other ceramic may be used), and its diameter is 100 to 300 mm. Furthermore, a pair of electrodes 2 and 2' for generating plasma discharge were arranged outside the reactor 5. This electrode is made of, for example, a stainless steel mesh, and a resistance heater 3 is provided covering this electrode, and the indicated temperature is 50.
~350°C, for example 300°C, is controlled with an accuracy of ±1°C. The substrate and substrate holder are abbreviated as 4, and the reactive gas is supplied from 6 through a homogenizer 26. A pair of electrodes is supplied with a high frequency (10 KHz to 100 MHz, typically 13.56 MHz, at an intensity of 5 to 200 W) by a supply power source 13. Unnecessary products after the reaction and carrier gas such as helium and hydrogen are removed from the exhaust gas. It is discharged from the port 13 through the pressure regulating valve 14 in the reaction tube and by the rotary pump 15.
反応筒５は反応中は反応圧力は0.05〜0.6torr代
表的には0.3torrに保持され、反応性気体の実効
流速を数十ｍ／秒にまではやめた。 During the reaction, the reaction pressure in the reaction column 5 was maintained at 0.05 to 0.6 torr, typically 0.3 torr, and the effective flow rate of the reactive gas was kept to several tens of m/sec.
この第１の反応炉に加えてこの一方、図面では
入口側に基板およびホルダ４を反応炉内に挿入ま
たは内より炉外へ引出す移動機構１２を有する第
１の室７が設けられている。この室は大気圧にす
る場合は１４より高純度空気が供給され、通気は
バルブ３９をへてロータリーポンプ３７にて
0.001〜0.01torrに真空引がされている。 In addition to this first reactor, on the other hand, in the drawing, a first chamber 7 is provided on the inlet side having a moving mechanism 12 for inserting the substrate and holder 4 into the reactor or pulling them out from the reactor. When this chamber is set to atmospheric pressure, high-purity air is supplied from 14, and ventilation is performed by a rotary pump 37 via a valve 39.
It is evacuated to 0.001 to 0.01 torr.
またこの基板およびホルダ１１は予備室８より
移動され、この第１の予備室８は１３より空気が
導入され大気圧となり、真空引がバルブ４０，ポ
ンプ３８によりなされ、室１７と概略等圧の十分
低真空となつた。そして基板およびホルダ１０が
１１に移される。さらにこの１１は第１の反応炉
４に移され、所定の半導体膜を基板上に形成させ
た。 The substrate and holder 11 are also moved from the preliminary chamber 8, and air is introduced into the first preliminary chamber 8 from 13 to bring it to atmospheric pressure. Vacuuming is performed by the valve 40 and pump 38, and the pressure is approximately equal to that of the chamber 17. The vacuum was sufficiently low. The substrate and holder 10 are then transferred to 11. Further, this 11 was transferred to the first reactor 4, and a predetermined semiconductor film was formed on the substrate.
さらにこの被膜を形成させた後、基板およびホ
ルダ４は電極１１に到り、外部にとり出すものは
予備室８より外部にとり出すことができる。 Further, after this film is formed, the substrate and holder 4 reach the electrode 11, and those to be taken out can be taken out from the preliminary chamber 8.
またさらにこの上に半導体層を作ろうとする場
合、１１にシヤツタ３２を開け、第２の室３０に
移動させる。この３２および次段のシヤツタ３３
は必ずしも必要ではなく、その場合は共通の室を
反応炉に連続して複数ケ設けることになる。 Furthermore, if a semiconductor layer is to be formed on top of this, the shutter 32 is opened at 11 and the material is moved to the second chamber 30. This 32 and the next stage shutter 33
is not necessarily necessary, and in that case, a plurality of common chambers will be provided in series in the reactor.
またさらに基板およびホルダは第２の反応系４
２に移され、第２の半導体層（例えばＩ層）を第
１の半導体層（例えばＰ層）を形成する履歴に無
関係に独立して作ることができた。 Furthermore, the substrate and the holder are in the second reaction system 4.
2, the second semiconductor layer (for example, I layer) could be made independently, regardless of the history of forming the first semiconductor layer (for example, P layer).
この第２の反応炉も反応性気体の導入口24より
反応性気体が入り、キヤリアガス、不純物は排気
口、バルブ１４真空引ポンプ２０をへて外部に放
出される。 Reactive gas enters this second reactor through the reactive gas inlet 24, and the carrier gas and impurities are discharged to the outside through the exhaust port, valve 14, and vacuum pump 20.
さらにこの第２の半導体膜が形成された後、第
２の予備室３５をへて外部にとり出されてもよい
が、この図面ではさらに今一度の第３の反応系４
３をへて第３の半導体層例えばＮ層半導体層を形
成し、さらにこの三層が形成された基板およびホ
ルダ３４は真空引をされた第２の予備室３５をへ
て１３より空気の導入によつて大気圧にさせた
後、ゲートバルブ３６をあけて外部にとり出され
る。 Furthermore, after this second semiconductor film is formed, it may be taken out to the outside through the second preliminary chamber 35, but in this drawing, it is further removed from the third reaction system 4.
3, a third semiconductor layer, for example, an N-layer semiconductor layer, is formed, and the substrate and holder 34 on which these three layers have been formed pass through a second preliminary chamber 35 that is evacuated, and air is introduced from 13. After bringing the pressure to atmospheric pressure, the gate valve 36 is opened and the gas is taken out to the outside.
以上の概要より明らかな如く、本発明は第１の
反応系には第１の室があり、この室に設けられた
移動機構１２により基板およびホルダ４は反応炉
１と第１の室７との間を往複する。さらに同様に
第２、第３の反応炉、基板およびホルダの保持お
よび移動機構２９，４１を有している。この第
１、第２、第３の室は共通させて設けており、こ
の共通の室の前後の入口側および出口側に第１、
第２の予備室を空気中の酸素、水分が反応系に混
入しといように設けてある。この製造装置におい
ては、各反応ごとに反応炉より一度真空引された
室７に引出されるため、各反応系の反応性気体が
全くそれぞれの反応炉に混入されることがない。
特に各反応炉と室との間のしきりバルブ５２，５
３，５４を出入れの際開閉し基板およびホルダ１
１が１１′，１１″と移動の際は、このしきりバル
ブが完全に閉の状態であるため、従来の説明にて
本発明人により示された各反応系が互いに１つの
ゲイトバルブで連結されている場合に比べてさら
に不純物のオートドーピングが少なくなつた。 As is clear from the above outline, the present invention has a first chamber in the first reaction system, and a moving mechanism 12 provided in this chamber moves the substrate and holder 4 between the reactor 1 and the first chamber 7. It goes back and forth between. Furthermore, it similarly has second and third reactors, substrate and holder holding and moving mechanisms 29 and 41. These first, second, and third chambers are provided in common, and the first, second, and third chambers are provided on the inlet and outlet sides of the common chamber.
A second preliminary chamber is provided to prevent oxygen and moisture in the air from entering the reaction system. In this manufacturing apparatus, since each reaction is drawn out from the reactor to the chamber 7 which has been evacuated once, the reactive gases of each reaction system are never mixed into the respective reactors.
In particular, the gate valves 52, 5 between each reactor and the chamber
3, 54 to open and close the board and holder 1 when putting it in and taking it out.
When 1 moves to 11' and 11'', this gate valve is completely closed, so each reaction system shown by the inventor in the conventional explanation is connected to each other by one gate valve. The autodoping of impurities was further reduced compared to the case where the
加えてさらに以上の説明においては、基板のホ
ルダは各反応室を基板と共に移動させた。しかし
この移動は基板のみとし、ホルダは第１の反応炉
用のホルダ１１、第２の反応炉用ホルダ１１′第
３の反応炉用ホルダ１１′をそれぞれ専用に配置
せしめることが本発明の製造装置においては可能
である。かくすることにより、各反応室間の不純
物の混入特にホルダ表面を付着しているPN型ま
たはEg可変用不純物、添加物の混入を完全に除
去することができ、多量生産用として全く画期的
なものである。 Additionally, in the above description, the substrate holder was moved through each reaction chamber with the substrate. However, in the production of the present invention, only the substrate is moved, and the holders are arranged exclusively for the first reactor holder 11, the second reactor holder 11', and the third reactor holder 11'. This is possible with the device. By doing this, it is possible to completely remove impurities between each reaction chamber, especially the contamination of PN type or Eg variable impurities and additives that adhere to the holder surface, which is completely revolutionary for mass production. It is something.
第２図は第１図の製造装置を補かんするもので
ある。すなわち第１、第２、第３の反応炉に対し
て供給される反応性気体は６，２７，２８よりそ
れぞれ供給される。その反応性気体は第２図Ａ，
ＢおよびＣに対して示されている。 FIG. 2 supplements the manufacturing apparatus shown in FIG. 1. That is, the reactive gases supplied to the first, second, and third reactors are supplied from 6, 27, and 28, respectively. The reactive gas is shown in Figure 2A,
Shown for B and C.
第２図Ａにおいては水素で希釈したジポラン４
３，シラン４４反応炉内壁のエツチング用ガス例
えばCF4（O2＝０〜５％）またはNF3、炭化物の
添加物である珪素と炭素とが化合した反応性気体
例えばTMS（テトラメチルシランSi（CH3）4）４
６およびキヤリアガスである水素またはヘリユー
ム４７が配置されている。 In Figure 2A, Diporan 4 diluted with hydrogen
3. Silane 44 A gas for etching the inner wall of the reactor, such as CF 4 (O 2 = 0 to 5%) or NF 3 , a reactive gas in which silicon and carbon are combined as carbide additives, such as TMS (tetramethylsilane, Si (CH 3 ) 4 ) 4
6 and carrier gas hydrogen or helium 47 are arranged.
これらは流量計（マスフロメータ）５０電磁バ
ルブ５１をへて６より第１の反応炉に供給され
る。この場合はSixC1-o（0.2ｘ１）で作られ
導電型はＰ型としている。かくすることにより
1.7〜2.5eVのEgを有するＰ型のアモルフアスま
たはセミアモルフアス構造を含む非単結晶半導体
を基板上に100〜300Aの厚さに形成させた。 These are supplied to the first reactor from 6 through a flow meter (mass flow meter) 50 and an electromagnetic valve 51. In this case, it is made of SixC 1-o (0.2x1) and the conductivity type is P type. By doing so
A non-single crystal semiconductor containing a P-type amorphous or semi-amorphous structure having an Eg of 1.7 to 2.5 eV was formed on a substrate to a thickness of 100 to 300 A.
被膜の作製は本発明人の出願になる特許願（プ
ラズマ気相法S56.10.14 56−103627）に詳しく述
べられているが、例えば250〜330℃特に300℃
0.1〜0.3torrプラズマ発生用電流13.56MHz ５〜
100W被膜形成時間10秒〜10分とした。 The preparation of the film is described in detail in the patent application filed by the present inventor (Plasma Vapor Phase Method S56.10.14 56-103627).
0.1~0.3torr plasma generation current 13.56MHz 5~
The 100W film formation time was 10 seconds to 10 minutes.
反応炉内壁は５〜30回作製するとフレイク（薄
片）が発生するので、かかる場合には
CF4ZnyNF3によりプラズマエツチングして除去
すればよい。 If the inner wall of the reactor is fabricated 5 to 30 times, flakes will occur, so in such cases,
It can be removed by plasma etching with CF 4 ZnyNF 3 .
第２図ＢはＩ層のアモルフアスまたは５〜
100Aの大きさの微結晶性を含有するセミアモル
フアスまたはマイクロポリクリスタルよりなる非
単結晶半導体膜を作製する場合を示している。 Figure 2B shows the amorphous or 5-
A case is shown in which a non-single-crystal semiconductor film made of semi-amorphous or micro-polycrystal containing microcrystals with a size of 100 A is manufactured.
すなわちシラン４５CF4（O2＝０〜５％），キヤ
リアガスであるヘリユーム４９よりなり５〜20％
にヘリユームにて希釈されたシランにより光伝導
度１×10-3〜９×10-2（Ωcm）-1特に５〜20×10-3
（Ωcm）-3の値を有する珪素の非単結晶半導体を
0.4〜1μの厚さに作製した。 That is, it consists of silane 45CF 4 (O 2 = 0 to 5%) and carrier gas helium 49, 5 to 20%.
Silane diluted with helium increases the photoconductivity from 1×10 -3 to 9×10 -2 (Ωcm) -1, especially from 5 to 20×10 -3
A non-single crystal semiconductor of silicon with a value of (Ωcm) -3
It was manufactured to a thickness of 0.4 to 1μ.
また第２図ＣはＡとは逆にＮ型不純物であるフ
オスヒン４８，シラン４３，エツチング用ガス４
５TMS４６キヤリアガス４０を提供し100〜
500AのＮ型半導体層を作製した。 In addition, Fig. 2 C shows N-type impurity Phosphin 48, silane 43, and etching gas 4, contrary to A.
5 TMS 46 Carrier Gas 40 Provided 100~
A 500A N-type semiconductor layer was fabricated.
かくして第３図に示す如き基板上にPIN型のダ
イオードまたは光電変換装置を作り、その特性を
調べた。 Thus, a PIN type diode or photoelectric conversion device was fabricated on a substrate as shown in Figure 3, and its characteristics were investigated.
第３図Ａにおいてはステンレスの如き金属基板
またはカプトンの如きフレキシブルフイルム上に
ステンレス膜が形成された基板７０上にＰ型半導
体層７１Ｉ型半導体層７２Ｎ型半導体層７４より
なる半導体層７３を作製し、この上面にITOの如
き透光性透明導電膜を600〜800AP5＝10〜25Ω／
□を作製した。従来の一室式の平行平板型では
AM1（100ｍＷ／cm2）にて６〜7.5％／３mm□
しか
得られなかつたが、本発明人の出願になるたて型
の独立分離式においては、7.5〜9.5％／３mm□
が
得られた。しかし本発明では、ホルダを各反応炉
独立式にした場合、最高16％／３mm□
一般に12〜
15％の高い変換効率の太陽電池を作ることができ
た。またホルダを各反応炉共通にした場合、9.0
〜12.5％の高い効率であつた。 In FIG. 3A, a semiconductor layer 73 consisting of a P-type semiconductor layer 71, an I-type semiconductor layer 72, and an N-type semiconductor layer 74 is fabricated on a substrate 70 in which a stainless steel film is formed on a metal substrate such as stainless steel or a flexible film such as Kapton. , on this upper surface, a light-transmitting transparent conductive film such as ITO is applied 600~800AP 5 = 10~25Ω/
□ was made. In the conventional one-room parallel plate type
With AM1 (100mW/cm 2 ), only 6-7.5%/3mm□ could be obtained, but in the vertical independent separation type applied by the present inventor, 7.5-9.5%/3mm□ could be obtained. Ta. However, in the present invention, when the holder is made independent of each reactor, the maximum is 16%/3mm□ Generally 12~
We were able to create a solar cell with a high conversion efficiency of 15%. In addition, if the holder is shared by each reactor, 9.0
The efficiency was as high as ~12.5%.
これは酸素、水分等の酸化物気体の外部からの
混入防止、各半導体表面等への不純物混入を防止
したことにある。 This is because it prevents oxide gases such as oxygen and moisture from entering from the outside, and prevents impurities from entering the surfaces of each semiconductor.
さらに重要なことは、１回のバツチにおいて10
cm□
の基板を50〜500まいもローデイング可能で
あり、10cm□
１まいに対する設備消却費は従来の
50〜500円であつたものが、0.2〜２円と約1/100
に下げることが可能となつた点で光電変換装置の
流布のためきわめて重要であつた。 More importantly, in one batch, 10
It is possible to load 50 to 500 meters of substrates of cm□, and the equipment consumption cost for 1 meter of 10 cm□ is lower than that of conventional
Items that cost 50 to 500 yen now cost 0.2 to 2 yen, about 1/100
This was extremely important for the widespread use of photoelectric conversion devices, as it made it possible to lower the
第３図Ｂガラスの如き透光性基板７６上にITO
（500〜800A）７８および酸化スズまたは酸化ア
ンチモン７９（100〜300A）よりなる低シート抵
抗（P5＝５〜20Ω／□高耐熱性）の透明導電膜
７７上にＰ型半導体層71，Ｉ型層７２，Ｎ型層７
４およびアルミニユームまたはITOよりなる裏面
電極７５を設けたものである。かかる構造におい
ても変換効率10〜13％を得ることができた。 Figure 3B ITO on a transparent substrate 76 such as glass
A P-type semiconductor layer 71, I Type layer 72, N type layer 7
4 and a back electrode 75 made of aluminum or ITO. Even in this structure, a conversion efficiency of 10 to 13% could be obtained.
このためこの構造をガラス基板上に集積化しま
た同時にPIN型の逆流防止ダイオードを設けるこ
とにより民生用の太陽電池を従来と同一出力を得
る場合従来より1/2の面積でかつ価格は200〜250
円を20〜30円にまで下げ、10cm2の面積にて100〜
130円で作ることが可能になつた。 Therefore, by integrating this structure on a glass substrate and at the same time providing a PIN-type backflow prevention diode, a consumer solar cell with the same output as a conventional one would require 1/2 the area and cost 200 to 250 yen.
Lower the yen to 20 to 30 yen, and 100 to 100 in an area of 10 cm 2
It became possible to make it for 130 yen.
第４図は本発明のプラズマCVD法で特にグロ
ー放電法を用いる反応炉に配置される基板、電極
および基板のローテイングの関係を示す。 FIG. 4 shows the relationship among substrates, electrodes, and substrate rotations arranged in a reactor using the glow discharge method in the plasma CVD method of the present invention.
図面において第４図Ａは電極２，２′を水平方
向に平行に、また基板６１を裏面を互いに密接し
て表面は基板間を20〜40mmの間かくで設けた。ま
たその配置はやはり水平に設けたものである。 In FIG. 4A, the electrodes 2 and 2' are horizontally parallel to each other, and the substrates 61 are placed in close contact with each other on their back surfaces, with a distance of 20 to 40 mm between the substrates on the front surface. Also, the arrangement is horizontal.
反応炉１の反応筒５は直径100〜300mm〓代表的
には180mmを有し、その長さは200〜400〓cmを有す
るため、10cm□
の基板に図面の如き８まいではな
く各段20まいを10〜30列配置させることができ
た。このため１回の製造バツチで50〜600まいを
作ることができ、従来の平行平板式では全く考え
られない量の半導体装置を一度に作ることができ
た。 The reaction tube 5 of the reactor 1 has a diameter of 100 to 300 mm (typically 180 mm) and a length of 200 to 400 cm. I was able to arrange 10 to 30 rows of mai. As a result, 50 to 600 semiconductor devices can be manufactured in one production batch, making it possible to manufacture an amount of semiconductor devices at once that was completely unimaginable using the conventional parallel plate method.
第４図Ｂは電極２，２′を垂直方向に、また基
板６１の表面（被形成面）を垂直方向に裏面を互
いに密接させて設けたものである。その他はＡと
同様である。 In FIG. 4B, the electrodes 2 and 2' are vertically disposed, and the front surface (forming surface) of the substrate 61 is vertically disposed with the back surfaces of the substrate 61 in close contact with each other. Others are the same as A.
ホルダへの基板のローデイングはＡ，Ｂを互い
に交互に行なつてもよい。 Loading of substrates onto the holder may be performed by alternating steps A and B.
第４図Ｃはアーク放電法またはグロー放電法を
用いたプラズマCVD法である。 FIG. 4C shows a plasma CVD method using an arc discharge method or a glow discharge method.
図面では第１図Ａの１つの反応炉を示したもの
である。すなわち放電電極２，２′を反応筒方向
に有し、基板６１はホルダ６０にローデイングさ
れ、反応管５の外側には加熱用ヒータ３が設けら
れている。アーク放電とするには一方の電極より
熱電＋放出をさせた。反応性気体は６より導入さ
れ、不要の反応性成物およびキヤリアガスは６３
より外部に放出される。この不要の反応生成物は
低温になる領域で粉末状になるため、反応炉５の
中（内壁）にこれらが発生することを防ぐため、
ヒータ３は６５に示す如く反応管のすべてをおお
うようにした。 The drawing shows one reactor of FIG. 1A. That is, the discharge electrodes 2 and 2' are provided in the direction of the reaction tube, the substrate 61 is loaded in the holder 60, and the heater 3 is provided outside the reaction tube 5. To create an arc discharge, thermoelectricity was emitted from one electrode. Reactive gas is introduced at 6, and unnecessary reactive products and carrier gas are introduced at 63.
released to the outside. These unnecessary reaction products turn into powder in the low-temperature region, so to prevent them from forming inside the reactor 5 (inner wall),
The heater 3 was arranged to cover the entire reaction tube as shown at 65.
かくすることにより粉末状の反応生成物を反応
筒内に残留させることはなくなり、歩留の向上に
なつた。第１図また第４図Ａ，Ｂにおいても同様
にすると、さらに生産性の向上に役立つた。 By doing so, the powdered reaction product was no longer left in the reaction column, and the yield was improved. If the same procedure is applied to FIG. 1 and FIGS. 4A and 4B, the productivity will be further improved.
以上の説明より明らかな如く、本発明はプラズ
マ気相法に対し多量生産を可能にする横型反応方
式を採用し、さらにそれらに共通室を設け連続的
に製造する構造とすることによりバツチ方式と連
続方式とを結合させることが可能となつた。この
ためこの思想を基礎とし、２つの反応系、４〜８
の反応系等を作ることができ、初めてPCVD装置
で大量生産可能な方式を開発することができた。 As is clear from the above explanation, the present invention adopts a horizontal reaction method that enables mass production compared to the plasma vapor phase method, and furthermore, by providing a common chamber for both and creating a structure for continuous production, it is possible to use a batch method. It became possible to combine this with a continuous method. Therefore, based on this idea, two reaction systems, 4-8
We were able to create a reaction system, etc., and for the first time, we were able to develop a method that could be mass-produced using PCVD equipment.
さらにこの半導体製造装置において、単にPIN
の光電変換装置のみではなく、Ｎ（0.1〜1μ）−Ｉ
（0.2〜2μ）−Ｉ（0.5〜1μ）の伝導型のIGFFT（たて
チヤネル型の絶縁ゲイト型電界効果半導体装置）
を、またはそれを集積化した構造を作ることが可
能である。さらにこの反応炉に横方向に巾２〜20
cmの50〜100cmの長い半導体基板を配置し、その
上面全面にフオトセンサアレーその他の半導体装
置を作ることも可能である。以上本発明の半導体
製造方法の工学的効果はきわめて著しいものであ
ると信じる。 Furthermore, in this semiconductor manufacturing equipment, simply PIN
Not only photoelectric conversion devices, but also N(0.1~1μ)-I
(0.2~2μ)-I(0.5~1μ) conduction type IGFFT (vertical channel type insulated gate field effect semiconductor device)
It is possible to create a structure that integrates it. Furthermore, this reactor has a width of 2 to 20 mm in the horizontal direction.
It is also possible to arrange a long semiconductor substrate of 50 to 100 cm and make a photo sensor array or other semiconductor device on the entire top surface. We believe that the engineering effects of the semiconductor manufacturing method of the present invention are extremely significant.
第１図は本発明の半導体装置製造装置の実施例
を示す。第２図は第１図を補かんする反応性気体
のガス系の実施例を示す。第３図は本発明により
作られた光電変換装置のたて断面図を示す。第４
図は第１図の反応炉の部分を示す実施例である。
FIG. 1 shows an embodiment of the semiconductor device manufacturing apparatus of the present invention. FIG. 2 shows an embodiment of a reactive gas system that supplements FIG. 1. FIG. 3 shows a vertical sectional view of a photoelectric conversion device made according to the present invention. Fourth
The figure is an embodiment showing a portion of the reactor shown in FIG.
Claims (1)
基板ホルダーを保持するまたは移動する機構を有
する共通室とを有し、前記共通室に前記第１及び
第２の反応炉が連結されている装置を用いる方法
であつて、前記共通室から前記第１の反応炉へ基
板及び基板ホルダーを移動する工程と、該工程の
後前記第１の反応炉で基板上に第１の半導体を形
成させる工程と、該工程の後前記基板及び基板ホ
ルダーを前記共通室にもどす工程と、該工程の後
第２の反応炉に再び前記基板及び基板ホルダーを
移動させる工程と、該工程の後前記基板上の第１
の半導体上に第２の半導体を形成させる工程と、
該工程の後再び前記基板及び基板ホルダーを前記
共通室にもどす工程とを有することを特徴とする
半導体装置製造方法。 ２ 特許請求の範囲第１項において反応炉におけ
る基板は基板表面が反応性気体の流れに沿うよう
に配設されたことを特徴とする半導体装置製造方
法。 ３ 特許請求の範囲第１項において半導体層の形
成がプラズマ気相法によつておこなわれることを
特徴とする半導体装置製造方法。[Scope of Claims] 1. A common chamber having a first and second reactor and a mechanism for holding or moving a substrate and a substrate holder under reduced pressure; A method using an apparatus in which two reactors are connected, the method including the steps of moving a substrate and a substrate holder from the common chamber to the first reactor, and after the step, moving the substrate and the substrate holder in the first reactor. a step of forming a first semiconductor on the substrate; a step of returning the substrate and the substrate holder to the common chamber after the step; and a step of moving the substrate and the substrate holder to the second reactor again after the step. , after the step, the first
forming a second semiconductor on the semiconductor;
A method for manufacturing a semiconductor device, comprising the step of returning the substrate and substrate holder to the common room after the step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate in the reactor is arranged such that the surface of the substrate follows the flow of reactive gas. 3. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is formed by a plasma vapor phase method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192293A JPS5893322A (en) | 1981-11-30 | 1981-11-30 | Manufacturing apparatus for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192293A JPS5893322A (en) | 1981-11-30 | 1981-11-30 | Manufacturing apparatus for semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4103746A Division JPH0831420B2 (en) | 1992-03-30 | 1992-03-30 | Coating production equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893322A JPS5893322A (en) | 1983-06-03 |
| JPH0337730B2 true JPH0337730B2 (en) | 1991-06-06 |
Family
ID=16288860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56192293A Granted JPS5893322A (en) | 1981-11-30 | 1981-11-30 | Manufacturing apparatus for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893322A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010681A (en) * | 1983-06-30 | 1985-01-19 | Canon Inc | Device for manufacturing photoelectric converting member |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139378A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Integrated treatment apparatus for semiconductor wafers |
| JPS54153740A (en) * | 1978-05-25 | 1979-12-04 | Ulvac Corp | Continuous vacuum treatment apparatus |
| JPS5578524A (en) * | 1978-12-10 | 1980-06-13 | Shunpei Yamazaki | Manufacture of semiconductor device |
-
1981
- 1981-11-30 JP JP56192293A patent/JPS5893322A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52139378A (en) * | 1976-05-17 | 1977-11-21 | Hitachi Ltd | Integrated treatment apparatus for semiconductor wafers |
| JPS54153740A (en) * | 1978-05-25 | 1979-12-04 | Ulvac Corp | Continuous vacuum treatment apparatus |
| JPS5578524A (en) * | 1978-12-10 | 1980-06-13 | Shunpei Yamazaki | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5893322A (en) | 1983-06-03 |
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