JPS6132416A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6132416A JPS6132416A JP15253184A JP15253184A JPS6132416A JP S6132416 A JPS6132416 A JP S6132416A JP 15253184 A JP15253184 A JP 15253184A JP 15253184 A JP15253184 A JP 15253184A JP S6132416 A JPS6132416 A JP S6132416A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- temperature
- doped layer
- conductive film
- transparent conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
［従来の技術］
太陽電池などに用いられるａ−８ｉ：ｔｌ、 ａ−８＋
Ｃ：Ｈ。[Prior art] a-8i:tl, a-8+ used in solar cells, etc.
C:H.
ａ−Ｇｅ：Ｈｌａ−８ｉ： Ｆ：Ｈ、μｃ−３ｉ：Ｈな
どの非晶質シリコン膜を成膜する際に、通常容量結合方
ＲＦ平行平板ＣＶＤ装置が用いられている。 −−しか
し、この装置を用い、従来法のように２２０〜２５０℃
程度の温度で成膜すると、電子や半導体形成ガスから生
成されたラジカルが直接基板面に衝突するため、ＩＴＯ
、Ｉｎ２Ｏ５、Ｉ■０／５ｎ０２、Ｃｄｘ５ｎＯＹ（Ｘ
−０，５〜２、ｙ＝２〜４）、ｌｒ Ｏ（ｘ＝ ０．
３３〜０．５）など×１−ｘ
から形成された透−明導電膜が一部還元され、金属化す
る。この金属が堆積された第１不純物ド−プ層のみなら
ず真性層まで拡散して、一種のドーパントとして作用し
たり、真性層で発生した電子やホールを打消してしまう
再結合中心になったりするなど、半導体／透明導電膜間
の界面が著しく劣化する。また、前記金属化が生じると
、透明電極そのものの透明性や導電性も低下するため、
半導体装置の特性、とくに光電変換特性が大幅に低下す
る。When forming amorphous silicon films such as a-Ge:Hla-8i:F:H and μc-3i:H, a capacitively coupled RF parallel plate CVD apparatus is usually used. --However, using this equipment, the temperature
When a film is formed at a temperature of
, In2O5, I■0/5n02, Cdx5nOY(X
−0,5~2, y=2~4), lr O(x=0.
A transparent conductive film formed from x1-x such as 33-0.5) is partially reduced and metallized. This metal diffuses not only into the deposited first impurity doped layer but also into the intrinsic layer, acting as a kind of dopant or becoming a recombination center that cancels out electrons and holes generated in the intrinsic layer. The interface between the semiconductor/transparent conductive film is significantly deteriorated. In addition, when the metallization occurs, the transparency and conductivity of the transparent electrode itself decreases,
The characteristics of the semiconductor device, especially the photoelectric conversion characteristics, are significantly reduced.
［発明が解決しようとする問題点］
本発明は、前記のごとき酸化物透明導電膜上に非晶質半
導体を堆積する際におこる、酸化物透明導電膜の還元に
より生ずる問題を少なくしようとするものである。[Problems to be Solved by the Invention] The present invention attempts to reduce the problems caused by the reduction of the oxide transparent conductive film, which occurs when an amorphous semiconductor is deposited on the oxide transparent conductive film as described above. It is something.
［問題点を解決するための手段］
本発明は、酸化物透明導電膜上に第１不純物ドープ層（
以下、第１ドープ層という）、真性層、第２不純物ドー
プｍ＜以下、第２ドープ層という、第１ドープ層と反対
の導電タイプ）からなる非晶質半導体をこの順に堆積す
る際に、第１ドープ層の成膜温度を１０〜１８０℃、真
性層および第２不純物ドープ層の成膜温度を１６０〜３
５０℃にすることにより、前記問題を少なくしたもので
ある。[Means for solving the problems] The present invention provides a first impurity doped layer (
When depositing in this order an amorphous semiconductor consisting of a first doped layer (hereinafter referred to as a first doped layer), an intrinsic layer, and a second impurity doped m<hereinafter referred to as a second doped layer (conductivity type opposite to the first doped layer), The film forming temperature of the first doped layer is 10 to 180°C, and the film forming temperature of the intrinsic layer and the second impurity doped layer is 160 to 3°C.
By setting the temperature to 50°C, the above-mentioned problem is alleviated.
［実施例］
本発明に用いる酸化物透明導電膜とは一般に半導体装置
の製造に使用される、厚さ０．０１〜１０ＩＡ程度の酸
化物透明導電膜のことであり、このような酸化物透明導
電膜である限り、とくに限定はない。該導電膜の具体例
としては、ＩＴＯ１ＩＴＯ／ ５ｎＯｚ 、Ｉｎ２Ｏ５
，５ｎ０２． Ｃｄ ＳｎＯｖ（ｘ＝Ｏ１５〜２、Ｙ
＝２〜４）、Ｉｒ Ｏ（ｘ＝０．３３×１−ｘ
〜０．５）、ＣｄＯなどがあげられるが、これらに限定
されるものではない。[Example] The oxide transparent conductive film used in the present invention is an oxide transparent conductive film with a thickness of about 0.01 to 10 IA, which is generally used in the manufacture of semiconductor devices. There is no particular limitation as long as it is a conductive film. Specific examples of the conductive film include ITO1ITO/5nOz, In2O5
, 5n02. Cd SnOv (x=O15~2, Y
=2~4), IrO (x=0.33x1-x~0.5), CdO, etc., but are not limited to these.
これらの導電膜はいずれも、水素原子を含んだような還
元性のプラズマにより還元されやすく、とくに温度が高
くなると一般的な化学反応のばあいと同様、その還元が
顕著におこる。All of these conductive films are easily reduced by reducing plasma containing hydrogen atoms, and when the temperature is particularly high, the reduction occurs significantly as in a general chemical reaction.
本発明において酸化物透明導電膜上に堆積される第１ド
ープ層としては、たとえばａ−８ｉ：Ｈ。In the present invention, the first doped layer deposited on the oxide transparent conductive film is, for example, a-8i:H.
ａ−３ｉＣ：Ｈ、ａ−Ｇｅ：Ｈｌａ−８ｉ：Ｆ：Ｈ１μ
Ｃ−３ｉ：Ｈなどのｐ型のものが一般的に用いられるが
、このようなｐ型のドープ層に限定されるものではない
。a-3iC:H, a-Ge:Hla-8i:F:H1μ
Although a p-type layer such as C-3i:H is generally used, it is not limited to such a p-type doped layer.
第１ドープ層が堆積されたのちに一形成される真性層、
および第２ドープ層としては、通常用いられる真性層、
および第１ドープ層と反対の導電タイプである第２ドー
プ層であれば、とくに限定されるものではない。このよ
うな真性層の具体例としては、ａ−８ｉ：Ｈｌａ−８ｔ
：Ｆ、 ａ−３ｉ：Ｆ：Ｈｌａ−８ｉＧｅ：Ｈｌａ−８
ｉＳｎ：Ｈ，ａ−３ｉＮ：Ｈなど、第２ドープ層の具体
例としては、第１ドープ層がｐ型のばあいにはｎ型の１
ｔＣ−８ｉ：Ｉｆ 、 ａ−３ｉＣ：Ｈ、ａ−８ｉ：Ｈ
，ａ−８ｉＮ：Ｈなど、第１ドープ層がｎ型のばあいに
はｐ型のａ−８ｉ：Ｈ，μＣ−８ｉ：Ｈ、ａ−３ｉＣ：
Ｈなどがあげられる。an intrinsic layer formed after the first doped layer is deposited;
And as the second doped layer, a commonly used intrinsic layer,
The second doped layer is not particularly limited as long as it is a second doped layer having a conductivity type opposite to that of the first doped layer. A specific example of such an intrinsic layer is a-8i:Hla-8t
:F, a-3i:F:Hla-8iGe:Hla-8
Specific examples of the second doped layer, such as iSn:H and a-3iN:H, include n-type 1 when the first doped layer is p-type.
tC-8i:If, a-3iC:H, a-8i:H
, a-8iN:H, etc. When the first doped layer is n-type, p-type a-8i:H, μC-8i:H, a-3iC:
Examples include H.
本発明においては、第１ドープ層を成膜するばあい成膜
温度を１８０℃以下、好ましくは１５０℃以下、さらに
好ましくは１３０℃以下、ことにヒーターを用いない温
度（たとえば１０〜７０℃程度）、とくに好ましくは基
板を冷却した温度（たとえば１０〜４０℃程度）にする
のがよい。このように成膜温度を低くして成膜すること
により、酸化物透明導電膜が水素原芋を含んだ還元性の
プラズマと接触しても還元されにくくなり、したがって
生成する金属の凶も少なくなり、該金属による半導体層
の汚染から生ずる再結合中心の発生、ドーピング効率の
低下などの半導体特性の低下が著しく改善される。また
低い温度で成膜するので堆積される第１ドープ層に発生
する内部応力を少なくすることができるため、第１ドー
プＩＩ／酸化物透明導電膜の界面におけるストレスから
起因するダングリングボンドなどの欠陥を減少させるこ
とができる。さらに連続プロセス装置を用いてヒーター
を用いない温度で成膜するようなばあいには、ヒーター
の１つを節約することができ、装置コストの低減をはか
ることができる。In the present invention, when forming the first doped layer, the film forming temperature is 180°C or lower, preferably 150°C or lower, more preferably 130°C or lower, especially at a temperature not using a heater (for example, about 10 to 70°C). ), particularly preferably at a temperature at which the substrate is cooled (for example, about 10 to 40°C). By forming the film at a low film-forming temperature in this way, the oxide transparent conductive film is less likely to be reduced even if it comes into contact with reducing plasma containing hydrogen raw material, and therefore the metal produced is less likely to be harmful. Therefore, deterioration of semiconductor properties such as generation of recombination centers and deterioration of doping efficiency resulting from contamination of the semiconductor layer by the metal is significantly improved. In addition, since the film is formed at a low temperature, the internal stress generated in the deposited first doped layer can be reduced, so dangling bonds etc. caused by stress at the interface of the first doped II/oxide transparent conductive film can be reduced. Defects can be reduced. Furthermore, if a continuous process device is used to form a film at a temperature without using a heater, one of the heaters can be saved, and the cost of the device can be reduced.
前記第１ドープ層を成膜するばあいのプラズマ条件は成
膜温度が低いために注意を要し、通常圧力を０．２〜２
．５Ｔｏｒｒの範囲で、グロー放電を維持可能な最小ま
たはその近傍の圧力にし、シラン（またはシランとメタ
ンの混合ガス）に対するドーピングガスの流量比を０．
０５〜２，０％にし、ＲＦパワーはグロー放電を維持可
能な範囲（５〜２０１４／ｃｄ）で最小になるようにし
て、膜のドーピング特性、光学的禁止帯幅を最適化した
条件、たとえばｐ型半導体を製造するばあいには、導電
率の温度依存性から求まる活性化エネルギーΔＥが０．
６ｅＶ以下、光学的禁止帯幅ＥＯｐｔとの差がＥＯＤｔ
−ΔＥ≧Ｌ３ｅＶになるように最適化された条件である
。When forming the first doped layer, care must be taken regarding the plasma conditions because the film forming temperature is low, and the pressure is usually set at 0.2 to 2.
．． The pressure is at or near the minimum that can sustain glow discharge in the range of 5 Torr, and the flow rate ratio of doping gas to silane (or a mixture of silane and methane) is 0.
05 to 2,0%, and the RF power is minimized within the range that can maintain glow discharge (5 to 2014/cd), and the doping characteristics of the film and the optical band gap are optimized, for example. When manufacturing a p-type semiconductor, the activation energy ΔE determined from the temperature dependence of conductivity is 0.
6eV or less, the difference from the optical band gap EOpt is EODt
The conditions are optimized so that -ΔE≧L3eV.
なお本発明の方法を実施するための装置としては、通常
の容量結合型ＲＦ平行平板ＣｖＯ装置。The apparatus for carrying out the method of the present invention is a conventional capacitively coupled RF parallel plate CvO apparatus.
誘導結合型ＲＦ平行平板ＣｖＤ装置、ＤＣ０平行平板型
ＣｖＤ装置などがあげられるが、平行平板ＣＯｖ装置に
顕著な効果がみられる。Examples include an inductively coupled RF parallel plate CvD device, a DC0 parallel plate CvD device, and a remarkable effect is seen in the parallel plate COv device.
つぎに本発明の方法を実施例に基づき説明する。Next, the method of the present invention will be explained based on examples.
実施例１〜６および比較例１
ＲＦ容量結合型平行平板ＣｖＤ装置を用い、青板ガラス
板上にスパッタ法により厚さ７００＾になるようにＩＴ
Ｏを形成した。第１表に示す温度、ＣＶＤ圧力１．５Ｔ
ｏｒｒ、 ３ｉｔ１４／ ＣＨ４ｆ）流量が２／３、
ＳｉＨ４＋ＣＨ４の合計流量に対してＢｚ Ｈ６の流量
ηなるようにして、ＲＦパワー密度１ｏｏ１／ｃｄでρ
型ａ−８ｉＣ：Ｈ層をＩＴＯ面上に１００人堆積させた
のち、２２０℃、ＣＶＤ圧力ＩＴＯｒｒ ５ＳｉＨ４ガ
スを用いてＲＦパワー密度１５１１Ｍ／ ７でｉ型ａ−
３ｉ：８層を６０００ Ａ堆積させた。ついで２２０℃
、ＣＶ［１圧力２ Ｔｏｒｒ 、 ５ｉＨａに対しＰ
Ｈ３が１％、Ｈ２が３０倍になるように導入し、ＲＦパ
ワー密度５０〜７０＋ｎＷ／ＣＩｉでｎ型μｃ−８ｉ：
８層を３０ＯＡ堆積させ、電極としてＡ１を真空蒸着法
により１０００人堆積させて、１ｄの面積を有する太陽
電池を作製した。Examples 1 to 6 and Comparative Example 1 Using an RF capacitively coupled parallel plate CvD device, IT was deposited onto a blue plate glass plate by sputtering to a thickness of 700^.
O was formed. Temperature shown in Table 1, CVD pressure 1.5T
orr, 3it14/CH4f) flow rate is 2/3,
The flow rate of Bz H6 is set to η for the total flow rate of SiH4 + CH4, and ρ is set at an RF power density of 1oo1/cd.
Type a-8 iC: After 100 layers of H layer were deposited on the ITO surface, the i-type a-
3i:8 layers were deposited at 6000 A. Then 220℃
, CV [1 pressure 2 Torr, P for 5iHa
Introducing H3 to 1% and H2 to 30 times, n-type μc-8i at RF power density of 50 to 70+nW/CIi:
A solar cell having an area of 1 d was fabricated by depositing 8 layers at 30 OA and depositing 1000 A1 layers as electrodes by vacuum evaporation.
えられた太陽電池の特性をＡＭ−１，１００ｆｌｌＷ／
ｃａｔのソーラーシュレータ−を用いて測定した。それ
らの結果を第１表および第１図に示す。The characteristics of the solar cell obtained were AM-1,100flW/
It was measured using a Cat solar schulator. The results are shown in Table 1 and FIG.
酸化物透明電極／ｐ層／ｉ層の界面の様子をしらべるた
め、えられた太陽電池と同じＣＶＤ条件にてＥｌｌおよ
びｉｌをＩＴＯ上にそれぞれ１００＾、３００Ａの厚さ
に順次堆積させたのちＥＳＣＡ。In order to examine the state of the oxide transparent electrode/p layer/i layer interface, Ell and il were sequentially deposited on ITO to a thickness of 100 and 300 A, respectively, under the same CVD conditions as the solar cell. ESCA.
＾ｎｏｅｒ 、８１８８などの電子分光法により測定し
、０層およびｉ層に拡散したＩｎの量を分析した。The amount of In diffused into the 0 layer and the i layer was analyzed using electron spectroscopy such as Noer, 8188.
それらの結果を第１表に示す。The results are shown in Table 1.
［以下余白］
第１表の結果から、ｐ層の成膜温度を下げることにより
、太陽電池特性のうちの短絡電流（Ｊｓｃ）および曲線
因子（ＦＦ）に大幅な改善がみられ、結果的に光電変換
効率（η）の向上がはかられることがわかる。[Left below] From the results in Table 1, by lowering the p-layer deposition temperature, there was a significant improvement in the short circuit current (Jsc) and fill factor (FF) of the solar cell characteristics, and as a result, It can be seen that the photoelectric conversion efficiency (η) can be improved.
また第１表の結果から、ｐ層およびｉ層に拡散したＩｎ
の便が、成膜温度３０℃のものは１８０℃のものの１７
１０以下、２２５℃のものの１７２０以下であることが
わかる。Also, from the results in Table 1, it is clear that In diffused into the p-layer and i-layer
The stool of the film forming temperature of 30℃ is 17% higher than that of 180℃.
It can be seen that it is 10 or less, and 1720 or less at 225°C.
［発明の効果］
本発明の方法により半導体装置を製造すると低い湿麿で
第１ドープ層を成膜するため、酸化物透明導電膜が水素
原子を含んだような還元性のプラズマと接触しても還元
されにくくなり、したがって生成する金属の量も少なく
なり、該金属による再結合中心の増加、ドーピング特性
の低下などの半導体特性の低下が著しく改善される。ま
た低温度で成膜するために堆積される１ド一プ層に発生
する内部応力を少なくすることができるため、第１ドー
プ層／１ｍ化物透明導電膜の界面における応力により発
生するダングリングボンドなどの欠陥を減少させること
ができる。さらに連続プロセス装置を用いてヒーターを
使用しない温度で成膜するようなばあいには、ヒーター
の１つを節約する゛ことができ、装置コストの低減をは
かることができる。[Effects of the Invention] When a semiconductor device is manufactured by the method of the present invention, the first doped layer is formed at a low humidity, so that the oxide transparent conductive film comes into contact with reducing plasma containing hydrogen atoms. is also less likely to be reduced, and therefore the amount of metal produced is reduced, and deterioration of semiconductor properties such as increase in recombination centers and deterioration of doping properties due to the metal is significantly improved. In addition, because the film is formed at a low temperature, it is possible to reduce the internal stress that occurs in the 1-doped layer deposited, so dangling bonds that occur due to stress at the interface of the 1-doped layer/1 m compound transparent conductive film can be reduced. It is possible to reduce defects such as Furthermore, if a continuous process device is used to form a film at a temperature that does not use a heater, one heater can be saved, and the cost of the device can be reduced.
第１図は実施例１〜６でえられた太陽電池の特性を示し
たグラフである。FIG. 1 is a graph showing the characteristics of the solar cells obtained in Examples 1 to 6.
Claims (1)
、第２不純物ドープ層（第１不純物ドープ層と反対の導
電タイプ）からなる非晶質半導体をこの順に堆積する際
に、第１不純物ドープ層の成膜温度が１０〜１８０℃で
、真性層および第２不純物および第２不純物ドープ層の
成膜温度が１６０〜３５０℃であることを特徴とする半
導体装置の製造方法。 ２ 前記第１不純物ドープ層の成膜温度が１３０℃以下
である特許請求の範囲第１項記載の製造方法。 ３ 前記第１不純物ドープ層の成膜温度がヒーターを用
いない温度である特許請求の範囲第１項記載の製造方法
。 ４ 前記第１不純物ドープ層の成膜温度が基板を冷却し
た温度である特許請求の範囲第１項記載の製造方法。[Claims] 1. An amorphous semiconductor consisting of a first impurity doped layer, an intrinsic layer, and a second impurity doped layer (conductivity type opposite to the first impurity doped layer) is deposited in this order on an oxide transparent conductive film. A semiconductor device characterized in that the film formation temperature of the first impurity doped layer is 10 to 180°C, and the film formation temperature of the intrinsic layer, the second impurity, and the second impurity doped layer is 160 to 350°C. manufacturing method. 2. The manufacturing method according to claim 1, wherein the first impurity doped layer is formed at a temperature of 130° C. or lower. 3. The manufacturing method according to claim 1, wherein the first impurity-doped layer is formed at a temperature that does not use a heater. 4. The manufacturing method according to claim 1, wherein the first impurity-doped layer is formed at a temperature at which the substrate is cooled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152531A JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59152531A JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6132416A true JPS6132416A (en) | 1986-02-15 |
| JPH0719906B2 JPH0719906B2 (en) | 1995-03-06 |
Family
ID=15542473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59152531A Expired - Lifetime JPH0719906B2 (en) | 1984-07-23 | 1984-07-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719906B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149968A (en) * | 1987-12-07 | 1989-06-13 | Toshiba Corp | Manufacture of fiber sliding member |
| JPH0586544A (en) * | 1991-04-01 | 1993-04-06 | Toyota Autom Loom Works Ltd | Picking device of jet loom, reed for picking device and production of the reed |
| US5279334A (en) * | 1991-07-10 | 1994-01-18 | Tsudakoma Kogyo Kabushiki Kaisha | Reed maintenance device with warp sheet repositioner |
| JP2002246619A (en) * | 2001-02-13 | 2002-08-30 | Kanegafuchi Chem Ind Co Ltd | Method of manufacturing thin film photoelectric conversion device |
| US6461444B1 (en) | 1999-08-20 | 2002-10-08 | Kaneka Corporation | Method and apparatus for manufacturing semiconductor device |
| US10024065B2 (en) | 2009-03-27 | 2018-07-17 | Afi Licensing Llc | Floor panel and floating floor system incorporating the same |
-
1984
- 1984-07-23 JP JP59152531A patent/JPH0719906B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149968A (en) * | 1987-12-07 | 1989-06-13 | Toshiba Corp | Manufacture of fiber sliding member |
| JPH0586544A (en) * | 1991-04-01 | 1993-04-06 | Toyota Autom Loom Works Ltd | Picking device of jet loom, reed for picking device and production of the reed |
| US5279334A (en) * | 1991-07-10 | 1994-01-18 | Tsudakoma Kogyo Kabushiki Kaisha | Reed maintenance device with warp sheet repositioner |
| US6461444B1 (en) | 1999-08-20 | 2002-10-08 | Kaneka Corporation | Method and apparatus for manufacturing semiconductor device |
| JP2002246619A (en) * | 2001-02-13 | 2002-08-30 | Kanegafuchi Chem Ind Co Ltd | Method of manufacturing thin film photoelectric conversion device |
| US10024065B2 (en) | 2009-03-27 | 2018-07-17 | Afi Licensing Llc | Floor panel and floating floor system incorporating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719906B2 (en) | 1995-03-06 |
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