JPH0336791A - Multilayer circuit ceramic board - Google Patents
Multilayer circuit ceramic boardInfo
- Publication number
- JPH0336791A JPH0336791A JP17157289A JP17157289A JPH0336791A JP H0336791 A JPH0336791 A JP H0336791A JP 17157289 A JP17157289 A JP 17157289A JP 17157289 A JP17157289 A JP 17157289A JP H0336791 A JPH0336791 A JP H0336791A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- layer
- mesh
- layers
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 51
- 239000010410 layer Substances 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 37
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000011295 pitch Substances 0.000 description 24
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 239000011269 tar Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、メツシュ状電源層等を有する積層セラミック
基板上にさらに高密度な配線層を形成したセラミック多
層配線板に関し、特に積層セラミック基板内層のメツシ
ュ状電源層あるいは信号配線と上記配線層内の電源配線
あるいは信号配線との接続用パッドを積層セラミック基
板表面に高密度に有したセラミック多層配線板に関する
ものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a ceramic multilayer wiring board in which a higher density wiring layer is formed on a laminated ceramic substrate having a mesh-like power supply layer, etc. The present invention relates to a ceramic multilayer wiring board having, on the surface of the laminated ceramic substrate, pads for connection between a mesh-like power supply layer or signal wiring and the power supply wiring or signal wiring in the wiring layer at high density.
［従来の技術］
従来より、メツシュ状電源層等を有する積層セラミック
基板上に高密度配線の樹脂配線層を形成したセラミック
多層配線板が知られており、放熱性が良く高密度配線が
行える特長を生かし、チップ等の電子部品を実装する手
段として電子機器などの装置で広く利用されている。[Prior Art] Ceramic multilayer wiring boards have been known in the past, in which a resin wiring layer with high-density wiring is formed on a laminated ceramic substrate having a mesh-like power supply layer, etc., and has the advantage of good heat dissipation and high-density wiring. It is widely used in devices such as electronic equipment as a means of mounting electronic components such as chips.
第４図は従来構造のセラミック多層配線板の断面図を示
し、第５図は第４図中のＡＡ’ 平面図を示している。FIG. 4 shows a sectional view of a ceramic multilayer wiring board having a conventional structure, and FIG. 5 shows a plan view taken along line AA' in FIG.
図中、ｌは積層セラミック基板、Ｄ、Ｄ、、Ｄ、、Ｄ、
はメツシュ状電源層、Ｓは信号配線である。また、積層
セラミック基板ｌの周辺の３．４は、それぞれ入出力信
号端子および電源端子であり、ダイアホール２を経由し
て信号配線Ｓあるいはメツシュ状電源層ＤＩ−Ｄ４とに
接続される。５．６は、それぞれ信号配線パッド及び電
源配線パッドであり、ダイアホール２を経由して信号配
線Ｓあるいはメツシュ状電源層り、−Ｄ、に接続されて
いる。また７は積層セラミック基板１上に形成された樹
脂配線層であり、上記のパッド５．６を介して樹脂配線
層７内の電源配線あるいは高密度な信号配線が、積層セ
ラミック基板ｌのメツシュ状電源層Ｄ１〜Ｄ４あるいは
信号配線Ｓに接続されている（樹脂配線層７内の電源配
線あるいは信号配線は図示していない）。従来、第５図
に示すようなヴィアホール２間のピッチＰは、メツシュ
状電源層ＤＩｎ ＤＩ＋ Ｉ）、、 Ｉ）、のどの層に
おいても同一な構造となっていた。In the figure, l is a laminated ceramic substrate, D, D, , D, , D,
is a mesh-like power supply layer, and S is a signal wiring. Further, terminals 3.4 at the periphery of the multilayer ceramic substrate l are an input/output signal terminal and a power supply terminal, respectively, and are connected to the signal wiring S or the mesh-like power supply layer DI-D4 via the dia hole 2. Reference numerals 5 and 6 denote a signal wiring pad and a power supply wiring pad, respectively, which are connected to the signal wiring S or the mesh-like power supply layer -D via the dia hole 2. Further, 7 is a resin wiring layer formed on the laminated ceramic substrate 1, and the power wiring or high-density signal wiring in the resin wiring layer 7 is connected to the mesh-like shape of the laminated ceramic substrate l via the pads 5 and 6. It is connected to the power supply layers D1 to D4 or the signal wiring S (the power supply wiring or signal wiring in the resin wiring layer 7 is not shown). Conventionally, the pitch P between the via holes 2 as shown in FIG. 5 has been the same in all layers of the mesh-like power supply layers DIn DI+ I), , I).
［発明が解決しようとする課題］
しかしながら、上記従来の技術におけるセラミック多層
配線板では、実装するチップの高密度化などに伴い、近
年ますます樹脂配線層７の配線密度が高密度になり、そ
のため信号配線パッド５のピッチを狭くして人出力信号
端子数３の数を増大させる場合、あるいは電源配線パッ
ド６のピッチを狭くして電源配線パッド６を高密度化さ
せる場合、従来の構造のままでは、メツシュ状電源層の
メツシュ幅Ｗが狭くなり、メツシュ状電源層の電気抵抗
が増大する結果、給電層として使用出来ないことにもな
ってしまう問題点があった。特に大電流が必要な装置あ
るいはセラミック多層配線板のサイズが大きい場合では
、致命的な問題となる。[Problems to be Solved by the Invention] However, in the ceramic multilayer wiring board according to the above-mentioned conventional technology, the wiring density of the resin wiring layer 7 has become higher and higher in recent years due to the increase in the density of chips to be mounted. When increasing the number of human output signal terminals 3 by narrowing the pitch of the signal wiring pads 5, or when increasing the density of the power wiring pads 6 by narrowing the pitch of the power wiring pads 6, the conventional structure can be maintained. However, there is a problem in that the mesh width W of the mesh-like power supply layer becomes narrow, and the electrical resistance of the mesh-like power supply layer increases, resulting in the mesh-like power supply layer being unable to be used as a power supply layer. This becomes a fatal problem, especially in devices that require large currents or in cases where the size of the ceramic multilayer wiring board is large.
即ち、クリアランスをＣ，ヴィアホール径をＶとすると
、メツシュ幅ＷはＷ＝Ｐ−２ＸＣ−Ｖであり、積層セラ
ミック基板ｌでは製造性の観点から、ピッチＰの大きさ
に関係なくクリアランスＣをある程度大きくする必要が
あり、またダイアホール２の径Ｖも層間接続抵抗の観点
及び製造性の点から、通常０．１８ｍａ＋以上で設計さ
れる。このため、ピッチＰを狭くすると急激にメツシュ
幅Ｗが小さくなってしまう。ちなみに、Ｃは０．２４ｍ
ｍ程度必要であり、ピッチＰを積層セラミック基板ｌの
製造限界に近い０ 、８ ｔａｒｓとすると、Ｗは０．
１４＋ａｍと狭いものになってしまう。ここで、積層セ
ラミック基板ｌの導体材料は、タングステンやモリブデ
ン等であり、抵抗率が大きいため特に電気抵抗が大きく
なる。That is, if the clearance is C and the via hole diameter is V, then the mesh width W is W=P-2XC-V, and from the viewpoint of manufacturability, the clearance C is It is necessary to increase the diameter to some extent, and the diameter V of the dia hole 2 is usually designed to be 0.18 ma+ or more from the viewpoint of interlayer connection resistance and manufacturability. For this reason, when the pitch P is narrowed, the mesh width W suddenly becomes smaller. By the way, C is 0.24m
If the pitch P is set to 0.8 tars, which is close to the manufacturing limit of the laminated ceramic substrate l, then W is approximately 0.8 tars.
It will be narrow at 14+am. Here, the conductive material of the laminated ceramic substrate l is tungsten, molybdenum, or the like, and has a high resistivity, so the electrical resistance is particularly high.
本発明は、上記問題点を解決するために創案されたもの
で、ヴィアホールビッチを高密度にする一方で、給電層
の電気抵抗を低減するセラミック多層配線板を提供する
ことを目的とする。The present invention was devised to solve the above-mentioned problems, and an object of the present invention is to provide a ceramic multilayer wiring board that reduces the electrical resistance of the power supply layer while increasing the density of via hole bits.
［課題を解決するための手段］
上記の目的を達成するための本発明のセラミック多層配
線板の構成は、
積層セラミック基板上にさらに配線層を有するセラミッ
ク多層配線板において、
前記積層セラミック基板内層には少なくとも２層以上の
メツシュ状電源層及び層間接続用ヴィアホールを有し、
前記積層セラミック基板表面の周辺部には入出力信号端
子及び電源端子を有し、
前記積層セラミック基板表面の内側領域には前記積層セ
ラミック基板の上に形成される配線層の信号配線及び電
源配線との接続用パッドを有し、前記積層セラミック基
板のメツシュ状電源層の層配置に対応して前記層間接続
用ヴィアホールのピッチを変えその広いピッチの該メツ
シュ状電源層を大電流用とすることを特徴とする。[Means for Solving the Problems] The structure of the ceramic multilayer wiring board of the present invention for achieving the above object is as follows: In the ceramic multilayer wiring board further having a wiring layer on the laminated ceramic substrate, an inner layer of the laminated ceramic substrate is provided. has at least two or more layers of mesh-like power supply layers and via holes for interlayer connection, has input/output signal terminals and power supply terminals in the peripheral area of the surface of the multilayer ceramic substrate, and has an inner region of the surface of the multilayer ceramic substrate. has connection pads for signal wiring and power supply wiring of the wiring layer formed on the multilayer ceramic substrate, and the interlayer connection via hole corresponds to the layer arrangement of the mesh-like power supply layer of the multilayer ceramic substrate. The mesh-like power supply layer having a wide pitch is used for large current by changing the pitch of the mesh-like power supply layer.
［作用コ
本発明は、一般に、必要な電源電流が電源種別毎に異な
ることに着目し、大電流が必要なメツシュ状電源層と大
電流が必要でないメツシュ状電源層とを層分けし、大電
流が必要なメツシュ状電源層のヴィアホールピッチを大
電流が必要でないメツシュ状電源層のヴィアホールピッ
チより大きくすることにより、全体としてヴィアホール
ピッチを小さくして高密度にした場合、大電流が必要な
メツシュ状電源層については大きいメッシュ幅を確保し
、給電層としての電気抵抗を低減する。[Function] The present invention focuses on the fact that the required power supply current generally differs depending on the type of power supply, and divides the mesh-like power supply layer that requires a large current into the mesh-like power supply layer that does not require a large current, and By making the via hole pitch of a mesh-like power supply layer that requires a larger current than the via-hole pitch of a mesh-like power supply layer that does not require a large current, the overall via hole pitch can be made smaller and higher density can be achieved. For the mesh-like power supply layer, a large mesh width is ensured to reduce the electrical resistance as a power supply layer.
［実施例コ
以下、本発明の実施例を図面に基づいて詳細に説明する
。[Embodiments] Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第１図は本発明の一実施例の断面図を示し、第２図は第
１図中のＢＢ’平面図を示し、第３図は同じく第１図中
のＣＣ′平面図を示している。FIG. 1 shows a sectional view of an embodiment of the present invention, FIG. 2 shows a BB' plan view in FIG. 1, and FIG. 3 shows a CC' plan view in FIG. 1. .
第１図において、ｌは積層セラミック基板であり、その
積層セラミック基板ｌ内には複数層のメツシュ状電源層
Ｅ、Ｅ−，Ｅｓ、Ｄ４．Ｄｓを層分けして配置する。メ
ツシュ状電源層Ｅ、、Ｅｌ、Ｅｓは、積層セラミック基
板ｌの裏面側に配置し、大電流が必要な電源層として使
用する。一方、メッンユ状電源層Ｄ−、Ｄｓは、積層セ
ラミック基板ｌの表面側に配置し、大電流が必要でない
電源層として使用する。Ｓは積層セラミック基板ｌ内に
設けた信号配線である。３．４は、それぞれ積層セラミ
ック基板ｌの表面上の周辺に配置した人出力信号端子お
よび電源端子であり、ダイアホール２Ｓあるいは２Ｄ、
２Ｅを経由して信号配線Ｓあるいはメツシュ状電源層Ｅ
ｌ、Ｅｘ、Ｅｓ、Ｄ−、Ｄｓへ接続する。５は信号配線
パッド、６Ｄは小電流電源配線パッド、・６Ｅは大電流
電源配線パッドであり、それぞれヴィアホール２Ｓ、２
Ｄ、２Ｅを経由して信号配線Ｓあるいはメッンユ状電源
層Ｄ４Ｄ、あるいはメツシュ状電源層Ｅ 、Ｅ ｔ、
Ｅ ｓに接続する。７は積層セラミック基板ｌ上に形成
された樹脂配線層であり、上記の配線パッド５．６Ｄ。In FIG. 1, l is a laminated ceramic substrate, and the laminated ceramic substrate l includes a plurality of mesh-like power supply layers E, E-, Es, D4. Ds are arranged in layers. The mesh-like power supply layers E, , El, and Es are arranged on the back side of the multilayer ceramic substrate 1 and are used as power supply layers that require a large current. On the other hand, the menyu-shaped power supply layers D- and Ds are arranged on the front surface side of the multilayer ceramic substrate l, and are used as power supply layers that do not require a large current. S represents a signal wiring provided within the laminated ceramic substrate l. 3.4 are human output signal terminals and power supply terminals arranged around the surface of the multilayer ceramic substrate l, respectively, and are connected to the diaholes 2S or 2D,
Signal wiring S or mesh power supply layer E via 2E
Connect to l, Ex, Es, D-, Ds. 5 is a signal wiring pad, 6D is a small current power supply wiring pad, and 6E is a large current power supply wiring pad, which are connected to via holes 2S and 2, respectively.
D, 2E via signal wiring S or mesh-like power supply layer D4D, or mesh-like power supply layer E, Et,
Connect to Es. 7 is a resin wiring layer formed on the laminated ceramic substrate l, and is the wiring pad 5.6D described above.
６Ｅを介して、樹脂配線層７内の図示しない電源配線あ
るいは高密度な信号配線と、積層セラミック基板ｌの信
号線Ｓあるいはメツシュ状電源層Ｅ１＋ Ｅ２．Ｅ３．
Ｄ４．Ｄ５とを接続する。積層セラミック基板ｌの裏面
側に近い下層からのダイアホール２Ｄ、２Ｅ、２Ｓは、
その上層にメッンユ状電源層Ｅ、−Ｄ、がある場合には
その孔部を通って各端子３．４やパッド５．６Ｄ、６Ｅ
に達する。6E, the power supply wiring or high-density signal wiring (not shown) in the resin wiring layer 7 and the signal line S of the multilayer ceramic substrate l or the mesh-like power supply layer E1+E2. E3.
D4. Connect with D5. Dia holes 2D, 2E, and 2S from the lower layer near the back side of the multilayer ceramic substrate l are as follows:
If there is a menyu-shaped power supply layer E, -D on the upper layer, each terminal 3.4 and pad 5.6D, 6E are passed through the hole.
reach.
第２図では積層セラミック基板ｉ内の裏面側に近いメツ
シュ状電源層Ｅ、の平面が示され、第３図では積層セラ
ミック基板ｌ内の表面側に近いメツシュ状電源層り、が
示されている。これらの園側に示すように本実施例では
、メツシュ状電源層Ｅｌ、Ｅ２．Ｅ３のヴィアホールピ
ッチＰｇをメツシュ状電源層Ｄ ４． Ｄ ｓのヴィア
ホールピッチＰ。Fig. 2 shows the plane of the mesh-like power supply layer E near the back side in the multilayer ceramic substrate i, and Fig. 3 shows the mesh-like power supply layer near the front side in the multilayer ceramic substrate l. There is. As shown on the side of these figures, in this embodiment, mesh-like power supply layers El, E2 . The via hole pitch Pg of E3 is made into a mesh-like power supply layer D4. Via hole pitch P of D s.
の２倍とする。shall be twice that of
以上のように構成した実施例の作用を述べる。The operation of the embodiment configured as above will be described.
本実施例は、電源電流が電源種別によって異なる点に着
目し、大電流が必要な１Ｅ源層として、ヴィアホールピ
ッチＰＥを広く取り積層セラミック基板１の表面側であ
る下層に配置したメツシュ状電源層Ｅ、、 Ｅ、、Ｅ、
を用い、大電流が必要でない電源層として、ヴィアホー
ルピッチＰＤを狭く取り、積層セラミック基板Ｉ内の表
面側である上層に配置したメッンユ状電源層Ｄ４．Ｄｓ
を用いる。This embodiment focuses on the fact that the power supply current differs depending on the type of power supply, and as a 1E source layer that requires a large current, a mesh-like power supply with a wide via hole pitch PE is placed in the lower layer on the surface side of the multilayer ceramic substrate 1. Layer E,, E,, E,
As a power supply layer that does not require a large current, a menyu-shaped power supply layer D4. Ds
Use.
コレにより、メツシュ状電源層り、、Ｄ、は、そのヴィ
アホールビッチＰｆ、を狭くすることによる電気抵抗の
増加の影響が、小電流であることから少なくなり、ヴィ
アホールピッチの高密度化に対応することが可能になる
。この場合、第１図に示す信号配線Ｓを積層セラミック
基板ｌの表面側に配置すれば、ヴィアホールピッチ２Ｓ
のピッチを狭くし、高密度に信号配線パッド５及び入出
力信号端子３を設けることが可能である。一方、メツシ
ュ状電源層Ｅ ｌ＋ Ｅ ｔ、 Ｅ 、は、ヴィアホー
ルビッチＰｇがＰｏの２倍であることから、Ｐａを小さ
くしても、そのメツシュ幅Ｗ０が従来よりも十分広くな
り、その電気抵抗を大幅に低減することが可能になり、
大電流用の電源層として好適なものとなる。これを具体
例で示すと、クリアランスＣが０．２４ｍ＋、ヴィアホ
ール径Ｖが０ 、１８ ｍｍ＋、信号配線パッド５のピ
ッチすなわちメツシュ状電源層Ｄ ４． Ｄ ｓのヴィ
アホールピッチＰｏが０ 、８ ＋＋＋＋＋＋の場合、
上に述べた様に、メツシュ状電源層の配置を工夫して、
メツシュ状電源層Ｅ、、Ｅ、、Ｅ、のダイアホールビＰ
Ｅを２倍の１ 、６ ｍｍとするだけで、メッシュ状１
１＆源層Ｄ ４． Ｄ ｓのメツシュ幅ＷＤ（＝Ｐａ
２ＸＣＶ）に比較してメツシュ状電源層Ｅ、、Ｅ、、
Ｅ、のメツシュ幅Ｗ ｔ （＝ Ｐ Ｅ ２ Ｘ Ｃ
−Ｖ）を７倍も大きく出来、電気抵抗をｌ／７と大幅に
低減できる。As a result, the influence of the increase in electrical resistance due to narrowing the via hole bit Pf in the mesh-like power supply layer, D, is reduced because the current is small, and the via hole pitch can be increased in density. It becomes possible to respond. In this case, if the signal wiring S shown in FIG. 1 is placed on the surface side of the multilayer ceramic substrate l, the via hole pitch is 2
It is possible to narrow the pitch and provide the signal wiring pads 5 and the input/output signal terminals 3 with high density. On the other hand, in the mesh-like power supply layer E l+ E t, E , the via hole bit Pg is twice that of Po, so even if Pa is made smaller, the mesh width W0 becomes sufficiently wider than the conventional one, and its electrical It becomes possible to significantly reduce resistance,
This is suitable as a power supply layer for large currents. To give a concrete example, the clearance C is 0.24 m+, the via hole diameter V is 0.18 mm+, and the pitch of the signal wiring pads 5, that is, the mesh-like power supply layer D4. When the via hole pitch Po of D s is 0, 8 +++++++,
As mentioned above, by devising the arrangement of the mesh-like power supply layer,
Diahole via P of mesh-like power supply layers E, , E, , E
By simply doubling E to 1.6 mm, mesh 1
1 & source layer D 4. Mesh width WD of D s (=Pa
2XCV), the mesh-like power supply layer E, , E,
Mesh width W t (= P E 2 X C
-V) can be increased by 7 times, and the electrical resistance can be significantly reduced to 1/7.
なお、本実施例では、電源層のメツシュ形状を正方形と
しているが、円形等でも本発明の効果が損なわれること
が無いことは言うまでもない。また、電源層にはＧＮＤ
（グランド）層をも含むものである。さらに、積層セ
ラミック基板ｉ上に形成される配線層の例として、樹脂
配線層７をとりあげているが、セラミック配線層等の他
の配線層でもかまわない。このように、本発明はその主
旨に沿って種々に応用され、種々の実施態様を取り得る
ものである。In this embodiment, the mesh shape of the power supply layer is square, but it goes without saying that the effects of the present invention will not be impaired even if the mesh shape is circular. Also, GND is connected to the power layer.
(ground) layer. Further, although the resin wiring layer 7 is taken as an example of the wiring layer formed on the multilayer ceramic substrate i, other wiring layers such as a ceramic wiring layer may be used. As described above, the present invention can be applied in various ways and can take various embodiments in accordance with its gist.
［発明の効果］
以上の説明で明らかなように、本発明のセラミック多層
配線板によれば、メツシュ状電源層の層配置に対応して
層間接続用のヴィアホールピッチを変え、広いヴィアホ
ールピッチのメツシュ状電源層を大電流用とすることで
、大電流の電源層の電気抵抗を低減することができると
ともに、狭いヴィアホールピッチのメツシュ状電源層に
よりヴィアホールピッチの高密度化に対応することがで
きる。[Effects of the Invention] As is clear from the above description, according to the ceramic multilayer wiring board of the present invention, the via hole pitch for interlayer connection is changed in accordance with the layer arrangement of the mesh-like power supply layer, and a wide via hole pitch can be achieved. By using the mesh-like power supply layer for large currents, it is possible to reduce the electrical resistance of the high-current power supply layer, and the mesh-like power supply layer with a narrow via hole pitch allows for higher density via hole pitches. be able to.
第１図は本発明の一実施例を示す断面図、第２図は第１
図の実施例のＢＢ’平面図、第３図は第１図の実施例Ｃ
Ｃ′平面図、第４図は従来例の断面図、第５図は第４図
の従来例のＡＡ’ 平面図である。
ｌ・・・積層セラミック基板、２Ｅ、２Ｄ、２Ｓ・・・
ヴィアホール、３・・・入出力信号端子、４・・・電源
端子、５・・・信号配線パッド、６Ｄ、６Ｅ・・−・電
源配線パッド、７・・・樹脂配線層、Ｅ、、Ｅｔ、Ｅ、
・・・ヴィアホールピッヂの広いメツシュ状電源層、Ｄ
４Ｄ、・・・ヴィアホールピッチの狭いメツシュ状電源
層。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
BB' plan view of the embodiment shown in the figure, Figure 3 is the embodiment C of Figure 1.
4 is a sectional view of the conventional example, and FIG. 5 is an AA' plan view of the conventional example shown in FIG. 4. l...Laminated ceramic substrate, 2E, 2D, 2S...
Via hole, 3... Input/output signal terminal, 4... Power supply terminal, 5... Signal wiring pad, 6D, 6E... Power supply wiring pad, 7... Resin wiring layer, E,, Et , E.
・・・Wide mesh-like power layer of via hole pitch, D
4D...Mesh-like power layer with narrow via hole pitch.
Claims (1)
ラミック多層配線板において、 前記積層セラミック基板内層には少なくとも２層以上の
メッシュ状電源層及び層間接続用ヴィアホールを有し、 前記積層セラミック基板表面の周辺部には入出力信号端
子及び電源端子を有し、 前記積層セラミック基板表面の内側領域には前記積層セ
ラミック基板の上に形成される配線層の信号配線及び電
源配線との接続用パッドを有し、前記積層セラミック基
板のメッシュ状電源層の層配置に対応して前記層間接続
用ヴィアホールのピッチを変えその広いピッチの該メッ
シュ状電源層を大電流用とすることを特徴とするセラミ
ック多層配線板。(1) A ceramic multilayer wiring board having a wiring layer on a laminated ceramic substrate, wherein the inner layer of the laminated ceramic substrate has at least two or more layers of mesh power supply layers and via holes for interlayer connection, and the surface of the laminated ceramic substrate The periphery of the multilayer ceramic substrate has input/output signal terminals and power supply terminals, and the inner region of the surface of the multilayer ceramic substrate has pads for connection with signal wiring and power supply wiring of a wiring layer formed on the multilayer ceramic substrate. and the pitch of the via holes for interlayer connection is changed in accordance with the layer arrangement of the mesh-like power supply layer of the laminated ceramic substrate, and the mesh-like power supply layer with a wide pitch is used for large current use. Multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17157289A JP2664485B2 (en) | 1989-07-03 | 1989-07-03 | Ceramic multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17157289A JP2664485B2 (en) | 1989-07-03 | 1989-07-03 | Ceramic multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0336791A true JPH0336791A (en) | 1991-02-18 |
| JP2664485B2 JP2664485B2 (en) | 1997-10-15 |
Family
ID=15925636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17157289A Expired - Fee Related JP2664485B2 (en) | 1989-07-03 | 1989-07-03 | Ceramic multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2664485B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828773A (en) * | 1996-01-26 | 1998-10-27 | Harris Corporation | Fingerprint sensing method with finger position indication |
| US5862248A (en) * | 1996-01-26 | 1999-01-19 | Harris Corporation | Integrated circuit device having an opening exposing the integrated circuit die and related methods |
| US5963679A (en) * | 1996-01-26 | 1999-10-05 | Harris Corporation | Electric field fingerprint sensor apparatus and related methods |
| US6181807B1 (en) | 1996-01-23 | 2001-01-30 | Authentec, Inc. | Methods and related apparatus for fingerprint indexing and searching |
| EP1137333A4 (en) * | 1998-09-17 | 2004-03-24 | Ibiden Co Ltd | Multilayer build-up wiring board |
| JP2008305944A (en) * | 2007-06-07 | 2008-12-18 | Denso Corp | Ceramic laminating wiring substrate |
| US10212805B2 (en) | 2016-12-27 | 2019-02-19 | Fujitsu Limited | Printed circuit board and electric device |
-
1989
- 1989-07-03 JP JP17157289A patent/JP2664485B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6181807B1 (en) | 1996-01-23 | 2001-01-30 | Authentec, Inc. | Methods and related apparatus for fingerprint indexing and searching |
| US5828773A (en) * | 1996-01-26 | 1998-10-27 | Harris Corporation | Fingerprint sensing method with finger position indication |
| US5862248A (en) * | 1996-01-26 | 1999-01-19 | Harris Corporation | Integrated circuit device having an opening exposing the integrated circuit die and related methods |
| US5956415A (en) * | 1996-01-26 | 1999-09-21 | Harris Corporation | Enhanced security fingerprint sensor package and related methods |
| US5963679A (en) * | 1996-01-26 | 1999-10-05 | Harris Corporation | Electric field fingerprint sensor apparatus and related methods |
| EP1137333A4 (en) * | 1998-09-17 | 2004-03-24 | Ibiden Co Ltd | Multilayer build-up wiring board |
| EP1868423A1 (en) * | 1998-09-17 | 2007-12-19 | Ibiden Co., Ltd. | Multilayer build-up wiring board |
| JP2008305944A (en) * | 2007-06-07 | 2008-12-18 | Denso Corp | Ceramic laminating wiring substrate |
| US10212805B2 (en) | 2016-12-27 | 2019-02-19 | Fujitsu Limited | Printed circuit board and electric device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2664485B2 (en) | 1997-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0176245B1 (en) | Multilayer wiring substrate | |
| US6888240B2 (en) | High performance, low cost microelectronic circuit package with interposer | |
| JP2559954B2 (en) | Stepped multi-layer interconnection device | |
| US5841191A (en) | Ball grid array package employing raised metal contact rings | |
| US6492620B1 (en) | Equipotential fault tolerant integrated circuit heater | |
| JPH0336791A (en) | Multilayer circuit ceramic board | |
| US4538143A (en) | Light-emitting diode displayer | |
| SG72713A1 (en) | Multilayer printed-circuit board and method of fabricating the multilayer printed-circuit board | |
| JP2005166794A (en) | Component package, printed wiring board and electronic apparatus | |
| US6101098A (en) | Structure and method for mounting an electric part | |
| JPH03286590A (en) | Ceramic wiring board | |
| JPH11340609A (en) | Manufacture of printed wiring board and manufacture of unit wiring board | |
| JPH09246684A (en) | Bga mounting structure | |
| JP2629908B2 (en) | Power supply structure of multilayer wiring board | |
| JPH09312478A (en) | Multi-layer circuit board | |
| JPS60160641A (en) | Mounting of leadless package ic for board | |
| JPH11163489A (en) | Mounting structure of electronic component | |
| JP2828753B2 (en) | Hybrid integrated circuit device | |
| JP2646710B2 (en) | SOP type SMD double-sided printed board | |
| JP2010010413A (en) | Multilayer printed wiring board, and multilayer printed wiring board device | |
| JPS6369258A (en) | Multilayer interconnection substrate | |
| JPS582091A (en) | Printed circuit board | |
| JPS6225437A (en) | Multilayer interconnection substrate | |
| JP2804827B2 (en) | Substrate for mounting electronic components | |
| JP3510475B2 (en) | Conversion module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |