JPH03280582A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03280582A JPH03280582A JP8269090A JP8269090A JPH03280582A JP H03280582 A JPH03280582 A JP H03280582A JP 8269090 A JP8269090 A JP 8269090A JP 8269090 A JP8269090 A JP 8269090A JP H03280582 A JPH03280582 A JP H03280582A
- Authority
- JP
- Japan
- Prior art keywords
- type
- polysilicon
- oxide film
- substrate
- type impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 34
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 42
- 239000010410 layer Substances 0.000 abstract description 33
- 238000000034 method Methods 0.000 abstract description 7
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に内部電圧安定回路等に
用いるクランプ用ＰＮ接合ダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a PN junction diode for clamping used in an internal voltage stabilizing circuit or the like.
内部電圧安定回路等に用いる従来のクランプ用ＰＮ接合
ダイオードは、第３図に示す断面図のように、フィール
ド酸化膜２で分離されたＰ型Ｓｉ基板１の領域に、例え
ば、イオン注入でＮ型不純物を導入しアニールを行なう
ことにより形成したＮ型不純物領域６ａ、およびＰ型Ｓ
ｉ基板１により形成されるＰＮ接合を用いていた。また
、従来のクランプ用ＰＮ接合ダイオードの耐圧のコント
ロールは、フィールド酸化膜２下の濃度あるいはＮ型不
純物領域６ａの形成を高濃度の砒素および低濃度な燐の
２重イオン注入で行なう注入条件によって行なっていた
。A conventional clamping PN junction diode used in an internal voltage stabilizing circuit, etc., is constructed by injecting N into a region of a P-type Si substrate 1 separated by a field oxide film 2 by, for example, ion implantation, as shown in the cross-sectional view of FIG. An N-type impurity region 6a formed by introducing type impurities and performing annealing, and a P-type S
A PN junction formed by an i-substrate 1 was used. Furthermore, the breakdown voltage of the conventional clamping PN junction diode is controlled by the concentration under the field oxide film 2 or the implantation conditions in which the N-type impurity region 6a is formed by double ion implantation of high concentration arsenic and low concentration phosphorus. I was doing it.
上述した従来のＰＮ接合ダイオードは、構造が非常に簡
単である点は良かったが、一方で次のような欠点を有し
ていた。The above-mentioned conventional PN junction diode had the advantage of having a very simple structure, but had the following drawbacks.
第１に、クランプ電圧（ブレークダウン電圧）がフィー
ルド酸化Ｉｌ！２の膜厚のばらつきにより影響されてし
まうことである。Ｐ型Ｓｉ基板１の不純物であるボロン
原子が酸化されるにしたがって酸化膜中に取り込まれ、
Ｐ型Ｓｔ基板１中のボロン濃度が低下してしまう。その
ため、フィールド酸化膜２のように〜１．０μｍと厚い
場合、フィールド酸化膜２直下のＰ型Ｓｉ基板１表面の
濃度の低下も大きく、フィールド酸化膜２の膜厚のばら
つきが濃度のばらつきとなり、これがクランプ電圧のば
らつきになる。First, the clamp voltage (breakdown voltage) is the field oxidation Il! This problem is affected by variations in the film thickness of No. 2. As boron atoms, which are impurities in the P-type Si substrate 1, are oxidized, they are incorporated into the oxide film,
The boron concentration in the P-type St substrate 1 will decrease. Therefore, when the field oxide film 2 is as thick as ~1.0 μm, the concentration on the surface of the P-type Si substrate 1 directly under the field oxide film 2 decreases significantly, and variations in the film thickness of the field oxide film 2 lead to variations in concentration. , this results in variation in the clamp voltage.
第２に、ブレークダウンはＮ型不純物領域６ａとＰ型Ｓ
ｉ基板１との界面におけるＰ型Ｓｉ基板１表面近傍で起
るため、ブレークダウンにより発生した電子−正孔対が
酸化膜中に捕獲され、特に正孔の捕獲が顕著となること
により表面近傍における界面での空乏層を拡げることに
なり、クランプ電圧が時間とともに上昇してしまうこと
がある。ことにＮ型不純物領域６ａとＰ型Ｓｉ基板１と
の界面におけるＰ型Ｓｔ基板１表面近傍の表面の酸化膜
はフィールド酸化膜２から薄い酸化膜１１ａに変る領域
でもあり、捕獲順位も多くクランプ電圧の変動も大きい
ものとなる。Second, breakdown occurs between the N-type impurity region 6a and the P-type S
Since the breakdown occurs near the surface of the P-type Si substrate 1 at the interface with the i-substrate 1, the electron-hole pairs generated by the breakdown are captured in the oxide film. This may cause the depletion layer at the interface to expand, and the clamp voltage may increase over time. In particular, the surface oxide film near the surface of the P-type St substrate 1 at the interface between the N-type impurity region 6a and the P-type Si substrate 1 is also the region where the field oxide film 2 changes to the thin oxide film 11a, and has a large number of trapping orders. Voltage fluctuations will also be large.
本発明の半導体装置は、一導電型の半導体基板の所定領
域にエツチングにより形成された凹部と、凹部の側壁に
形成された絶縁膜と、凹部に埋込まれた逆導電型のポリ
シリコンと、逆導電型のポリシリコン下部の半導体基板
に逆導電型のポリシリコンからの熱拡散により形成され
た逆導電型の第１の拡散層と、逆導電型のポリシリコン
下部の前記半導体基板に形成された一導電型の第２の拡
散層とを有している。A semiconductor device of the present invention includes a recess formed by etching in a predetermined region of a semiconductor substrate of one conductivity type, an insulating film formed on the sidewall of the recess, and polysilicon of an opposite conductivity type buried in the recess. A first diffusion layer of an opposite conductivity type formed on the semiconductor substrate under the polysilicon of the opposite conductivity type by thermal diffusion from the polysilicon of the opposite conductivity type, and a first diffusion layer formed on the semiconductor substrate under the polysilicon of the opposite conductivity type. and a second diffusion layer of one conductivity type.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の第１の実施例の断面図である。Ｐ型
Ｓｉ基板１上に選択酸化により形成されたフィールド酸
化ＷＡ２と、選択的にＰ型Ｓｉ基板ｌをエツチングして
形成した第１の凹部の側壁に形成された側壁酸化膜４と
、第１の凹部に埋込まれたＮ型埋込みポリシリコン７と
、Ｎ型埋込みポリシリコン７を拡散源として形成された
Ｎ型不純物拡散層６と、Ｎ型埋込みポリシリコン７の形
成前にＮ型不純物拡散層６よりもさらに深い領域に形成
したＰ型不純物拡散層５と、薄い酸化膜１１と、層間絶
縁Ｍ３と、Ａ１配線８とから本実施例の半導体装置は精
成されている０本実施例においては、Ｐ型不純物拡散屑
５とＮ型不純物拡散層６とによりＰＮ接合ダイオードが
形成れている。FIG. 1 is a sectional view of a first embodiment of the invention. Field oxidation WA2 formed on the P-type Si substrate 1 by selective oxidation, sidewall oxide film 4 formed on the sidewall of the first recess formed by selectively etching the P-type Si substrate 1, and the first N-type buried polysilicon 7 buried in the concave portion, N-type impurity diffusion layer 6 formed using N-type buried polysilicon 7 as a diffusion source, and N-type impurity diffusion layer 6 formed using N-type buried polysilicon 7 as a diffusion source. The semiconductor device of this embodiment is refined from the P-type impurity diffusion layer 5 formed in a deeper region than the layer 6, the thin oxide film 11, the interlayer insulation M3, and the A1 wiring 8. , a PN junction diode is formed by the P-type impurity diffusion waste 5 and the N-type impurity diffusion layer 6.
クランプ電圧の耐圧コントロールは、Ｐ型不純物拡散層
５の不純物濃度を変更することにより行なわれる。この
とき、Ｐ型不純物拡散層５の不純物濃度としては、Ｐ型
Ｓｉ基板ｌの他の領域の不純物濃度より高く、従って、
クランプ電圧の耐圧コントロールはＰ型不純物拡散層５
とＮ型不純物拡散層６とのそれぞれの不純物濃度により
決定されることになる。別の方法として、Ｎ型不純物拡
散層６は上述のようにＮ型埋込みポリシリコン７が拡散
源であり、Ｎ型埋込みポリシリコン７中の不純物を砒素
もしくは砒素と燐の２種類にすることにより、あるいは
それぞれの濃度を変えることによって、ＰＮ接合タイオ
ードの耐圧をコントロールすることもできる。The breakdown voltage control of the clamp voltage is performed by changing the impurity concentration of the P-type impurity diffusion layer 5. At this time, the impurity concentration of the P-type impurity diffusion layer 5 is higher than the impurity concentration of other regions of the P-type Si substrate l, and therefore,
The breakdown voltage control of the clamp voltage is performed by the P-type impurity diffusion layer 5.
It is determined by the respective impurity concentrations of the N-type impurity diffusion layer 6 and the N-type impurity diffusion layer 6. Another method is to form the N-type impurity diffusion layer 6 by using the N-type buried polysilicon 7 as the diffusion source as described above, and by changing the impurity in the N-type buried polysilicon 7 to arsenic or two types of arsenic and phosphorus. Alternatively, the breakdown voltage of the PN junction diode can be controlled by changing the respective concentrations.
次に、本実施例の構造を製造する方法について説明する
。Next, a method for manufacturing the structure of this example will be explained.
まず、Ｐ型Ｓｉ基板１に選択酸化を行なってフィールド
酸化膜２を形成し、ダイオード形成領域上の薄い酸化膜
を除去した後、選択的にＰ型Ｓｉ基板１のエツチングを
行ない第１の凹部を形成する。First, selective oxidation is performed on the P-type Si substrate 1 to form a field oxide film 2, and after removing the thin oxide film on the diode formation region, the P-type Si substrate 1 is selectively etched to form the first recess. form.
次に、例えば熱酸化法により、表面全体に酸化膜を形成
する。この酸化膜は、側壁酸化膜となるため、ダイオー
ドの耐圧に充分耐る膜厚を要す。Next, an oxide film is formed over the entire surface by, for example, a thermal oxidation method. Since this oxide film becomes a sidewall oxide film, it needs to be thick enough to withstand the withstand voltage of the diode.
続いて、全体にＲＩＥ法によるエツチング（エッチバッ
ク）を行ない、側壁酸化膜４のみを残し、他の領域の酸
化膜を除去する。Subsequently, the entire structure is etched (etched back) using the RIE method, leaving only the sidewall oxide film 4 and removing the oxide film in other regions.
その後、フォトリングラフィ技術およびイオン注入技術
により、Ｐ型不純物拡散層５を形成する。Thereafter, a P-type impurity diffusion layer 5 is formed using photolithography technology and ion implantation technology.
次に、ＣＶＤ法によりポリシリコン膜の成長を行ない、
エッチバックを行なうことにより埋込み部分のポリシリ
コンのみを残し、他の部分のポリシリコンはエツチング
除去する。この後、選択的にＮ型不純物拡散層を形成す
るための不純物をポリシリコン中に導入してＮ型埋込み
ポリシリコン７を形成し、熱処理を行なうことで、Ｎ型
不純物拡散層６を形成する。Next, a polysilicon film is grown using the CVD method,
By performing etchback, only the polysilicon in the buried portion is left, and the polysilicon in other portions is etched away. After this, impurities for forming an N-type impurity diffusion layer are selectively introduced into the polysilicon to form an N-type buried polysilicon 7, and heat treatment is performed to form an N-type impurity diffusion layer 6. .
次に、フィールド酸化膜２で覆われていない部分に、熱
酸化により薄い酸化膜１１を形成する。Next, a thin oxide film 11 is formed by thermal oxidation on the portion not covered with the field oxide film 2.
最後に、眉間絶縁膜３．コンタクト開口、Ａｊ配線８等
を形成し、本実施例の半導体装置の構造を完成する。Finally, the glabellar insulating film 3. Contact openings, Aj wiring 8, etc. are formed to complete the structure of the semiconductor device of this example.
本実施例ではＰ型基板上のＮ型不純物拡散層でのＰＮ接
合について説明したが、Ｎ型基板上のＰ型不純物拡散層
でのＰＮ接合でも同等の効果が得られる。In this embodiment, a PN junction in an N-type impurity diffusion layer on a P-type substrate has been described, but the same effect can be obtained with a PN junction in a P-type impurity diffusion layer on an N-type substrate.
第２図は、本発明の第２の実施例の断面図である。Ｎ型
埋込みポリシリコン７、Ｐ型不純物拡散層５．Ｎ型不純
物拡散層６等の構造、形成方法は、第１の実施例と同じ
である。FIG. 2 is a cross-sectional view of a second embodiment of the invention. N-type buried polysilicon 7, P-type impurity diffusion layer 5. The structure and formation method of the N-type impurity diffusion layer 6 and the like are the same as in the first embodiment.
Ｐ型Ｓｉ基板１への電極を形成する場所は、シリーズ抵
抗が最小になるように、最もＰ型不純物拡散層５に近い
領域にすべきである。Ｎ型埋込みポリシリコン７の形成
方法と同様の方法により、Ｐ壁埋込みポリシリコン１０
を形成し、Ｎ型不純物拡散層６を形成する時の熱処理で
Ｐ型不純物拡散層９も同時に形成する。The location where the electrode is formed on the P-type Si substrate 1 should be the region closest to the P-type impurity diffusion layer 5 so that the series resistance is minimized. P-wall buried polysilicon 10 is formed by a method similar to that of N-type buried polysilicon 7.
, and a P-type impurity diffusion layer 9 is also formed at the same time by heat treatment when forming the N-type impurity diffusion layer 6.
これにより、Ｐ型Ｓｉ基板１側のシリーズ抵抗を最小に
することが可能となる。This makes it possible to minimize the series resistance on the P-type Si substrate 1 side.
以上説明したように本発明は、実施例に示した導電型の
場合において、Ｎ型埋込みポリシリコンを拡散源として
形成したＮ型不純物拡散層とあらこしぬ形成しておいた
第１の凹部下部のＰ型不純物拡散層とによりＰＮ接合を
形成しており、Ｎ型埋込みポリシリコンは第１の凹部の
側壁に形成された絶縁膜によりＰ型基板と絶縁されてい
るため、ＰＮ接合ダイオードのブレークダウンを起す箇
所はＰ型基板の内部となり、Ｐ型基板の表面濃度のばら
つきの影響を受けることはまったくないことになる。As explained above, in the case of the conductivity type shown in the embodiment, the present invention provides a first recess lower part formed in the same way as an N-type impurity diffusion layer formed using N-type buried polysilicon as a diffusion source. A PN junction is formed with the P-type impurity diffusion layer, and since the N-type buried polysilicon is insulated from the P-type substrate by the insulating film formed on the side wall of the first recess, the break of the PN junction diode The location where down occurs is inside the P-type substrate, and is not affected by variations in the surface concentration of the P-type substrate at all.
また、ＰＮ接合ダイオードのブレークダウンを起す箇所
の近傍には正孔を捕獲しやすい酸化膜はほとんどなく、
クランプ電圧の時間変動もほとんどないクランプ用ＰＮ
接合タイオードを実現できる。In addition, there is almost no oxide film that easily captures holes near the point where breakdown occurs in the PN junction diode.
PN for clamps with almost no time variation in clamp voltage
A junction diode can be realized.
これらの効果は、導電型を逆転しても同様に得られる。These effects can be similarly obtained even if the conductivity types are reversed.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は従来のＰＮ接合ダ
イオードの断面図である。
１・・・Ｐ型Ｓｉ基板、２・・・フィールド酸化膜、３
・・眉間絶縁膜、４・・・側壁酸化膜、５．９・・・Ｐ
型不純物拡散層、６・・・Ｎ型不純物拡散層、７・・・
Ｎ型埋込みポリシリコン、８・・・Ａ（配線、１０・・
・Ｐ壁埋込みポリシリコン、１１．ｌｌａ・・・薄い酸
化膜。FIG. 1 is a sectional view of a first embodiment of the invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIG. 3 is a sectional view of a conventional PN junction diode. 1... P-type Si substrate, 2... Field oxide film, 3
・・Glabella insulating film, 4... Sidewall oxide film, 5.9...P
type impurity diffusion layer, 6...N type impurity diffusion layer, 7...
N-type buried polysilicon, 8...A (wiring, 10...
・P-wall embedded polysilicon, 11. lla...thin oxide film.
Claims (1)
り形成された第１の凹部と、 前記第１の凹部の側壁に形成された絶縁膜と、前記第１
の凹部に埋込まれた逆導電型のポリシリコンと、 前記逆導電型のポリシリコン下部の前記半導体基板に、
前記逆導電型のポリシリコンからの熱拡散により形成さ
れた逆導電型の第１の拡散層と、前記逆導電型のポリシ
リコン下部の前記半導体基板に形成された一導電型の第
２の拡散層と、を有することを特徴とする半導体装置。 ２、前記半導体基板の所定領域にエッチングにより形成
された第２の凹部と、 前記第２の凹部の側壁に形成された絶縁膜と、前記第２
の凹部に埋込まれた一導電型のポリシリコンと、 前記一導電型のポリシリコン下部の前記半導体基板に、
前記一導電型のポリシリコンからの熱拡散により形成さ
れた逆導電型の第３の拡散層と、を有することを特徴と
する請求項１記載の半導体装置。[Claims] 1. A first recess formed by etching in a predetermined region of a semiconductor substrate of one conductivity type; an insulating film formed on a side wall of the first recess;
polysilicon of opposite conductivity type embedded in the recess of the semiconductor substrate below the polysilicon of opposite conductivity type,
a first diffusion layer of opposite conductivity type formed by thermal diffusion from the polysilicon of opposite conductivity type; and a second diffusion layer of one conductivity type formed in the semiconductor substrate below the polysilicon of opposite conductivity type. A semiconductor device characterized by having a layer. 2. a second recess formed by etching in a predetermined region of the semiconductor substrate; an insulating film formed on a sidewall of the second recess;
polysilicon of one conductivity type embedded in the recess of the semiconductor substrate below the polysilicon of one conductivity type,
2. The semiconductor device according to claim 1, further comprising a third diffusion layer of an opposite conductivity type formed by thermal diffusion from the polysilicon of the one conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8269090A JP2926854B2 (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8269090A JP2926854B2 (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03280582A true JPH03280582A (en) | 1991-12-11 |
| JP2926854B2 JP2926854B2 (en) | 1999-07-28 |
Family
ID=13781414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8269090A Expired - Lifetime JP2926854B2 (en) | 1990-03-29 | 1990-03-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2926854B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6740552B2 (en) | 1996-03-01 | 2004-05-25 | Micron Technology, Inc. | Method of making vertical diode structures |
| JP2009277756A (en) * | 2008-05-13 | 2009-11-26 | Denso Corp | Zener diode and method of manufacturing the same |
-
1990
- 1990-03-29 JP JP8269090A patent/JP2926854B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6740552B2 (en) | 1996-03-01 | 2004-05-25 | Micron Technology, Inc. | Method of making vertical diode structures |
| US6784046B2 (en) | 1996-03-01 | 2004-08-31 | Micron Techology, Inc. | Method of making vertical diode structures |
| US6787401B2 (en) | 1996-03-01 | 2004-09-07 | Micron Technology, Inc. | Method of making vertical diode structures |
| US7166875B2 (en) | 1996-03-01 | 2007-01-23 | Micron Technology, Inc. | Vertical diode structures |
| US7170103B2 (en) | 1996-03-01 | 2007-01-30 | Micron Technology, Inc. | Wafer with vertical diode structures |
| US7279725B2 (en) | 1996-03-01 | 2007-10-09 | Micron Technology, Inc. | Vertical diode structures |
| US7563666B2 (en) | 1996-03-01 | 2009-07-21 | Micron Technology, Inc. | Semiconductor structures including vertical diode structures and methods of making the same |
| US8034716B2 (en) | 1996-03-01 | 2011-10-11 | Micron Technology, Inc. | Semiconductor structures including vertical diode structures and methods for making the same |
| JP2009277756A (en) * | 2008-05-13 | 2009-11-26 | Denso Corp | Zener diode and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2926854B2 (en) | 1999-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1063731A (en) | Method for making transistor structures having impurity regions separated by a short lateral distance | |
| JP3307112B2 (en) | Method for manufacturing semiconductor device | |
| KR0128339B1 (en) | Bipolar transistor fabrication utilizing cmos techniques | |
| KR960019776A (en) | Semiconductor device and manufacturing method | |
| KR890011033A (en) | Manufacturing Method of Semiconductor Device | |
| JPH03280582A (en) | Semiconductor device | |
| JPH0555593A (en) | Manufacture of insulated-gate field-effect transistor | |
| JPS5947468B2 (en) | Bipolar transistor manufacturing method | |
| CN1020991C (en) | Isolation method of semiconductor device | |
| JPS63166271A (en) | Manufacture of mis semiconductor device | |
| JP2817247B2 (en) | Semiconductor device | |
| KR100385655B1 (en) | Bipolar Transistors and Manufacturing Method | |
| JPH036863A (en) | Semiconductor device | |
| JP2809662B2 (en) | Method for manufacturing double-diffused MOSFET device | |
| JP2859400B2 (en) | Manufacturing method of gate turn-off thyristor | |
| JP2890509B2 (en) | Method for manufacturing semiconductor device | |
| KR900017177A (en) | Semiconductor device and manufacturing method thereof | |
| US20040191995A1 (en) | Method of manufacturing a semiconductor device | |
| KR100193338B1 (en) | Separation structure of semiconductor device and manufacturing method thereof | |
| JP2006165370A (en) | Semiconductor device and its manufacturing method | |
| JPH01123474A (en) | Insulated gate type semiconductor device | |
| KR100274604B1 (en) | Method for fabricating semiconductor device | |
| KR0151122B1 (en) | A method for making a bipolar device | |
| JPH06326320A (en) | Semiconductor device and its manufacture | |
| JPH02180022A (en) | Manufacture of semiconductor device |