JPH03258021A - Phase synchronism oscillating method and its circuit - Google Patents
Phase synchronism oscillating method and its circuitInfo
- Publication number
- JPH03258021A JPH03258021A JP2057023A JP5702390A JPH03258021A JP H03258021 A JPH03258021 A JP H03258021A JP 2057023 A JP2057023 A JP 2057023A JP 5702390 A JP5702390 A JP 5702390A JP H03258021 A JPH03258021 A JP H03258021A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- oscillation
- circuit
- voltage
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 14
- 230000010355 oscillation Effects 0.000 claims abstract description 50
- 230000001360 synchronised effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は位相同期発振方法および回路、特に、データ転
送速度が変化する磁気ディスク等に用いられる位相同期
発振方法および回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronized oscillation method and circuit, and particularly to a phase synchronized oscillation method and circuit used for magnetic disks and the like in which data transfer speeds vary.
従来の位相同期発振方法および回路は、一つの電圧制御
発振回路で発振周波数を制御していた。In conventional phase-locked oscillation methods and circuits, the oscillation frequency was controlled by one voltage-controlled oscillation circuit.
上述した従来の位相同期発振方法および回路は、一つの
電圧制御発振回路で発振周波数を制御していたので、デ
ータ転送速度が大きく変化すると、電圧制御発振回路の
制御範囲を越えると、発振を制御できなくなり、また位
相引込み領域の長さが変化するため位相同期発振回路の
ループゲインが一定であると、規定時間内に位相引込み
できないという欠点があった。In the conventional phase-locked oscillation method and circuit described above, the oscillation frequency was controlled by a single voltage-controlled oscillation circuit, so if the data transfer rate changes significantly and exceeds the control range of the voltage-controlled oscillation circuit, the oscillation will be stopped. In addition, since the length of the phase locking region changes, if the loop gain of the phase synchronized oscillation circuit is constant, there is a drawback that phase locking cannot be performed within a specified time.
本発明の位相同期発振方法は、
（Ａ）二つの信号を位相を比較し、位相差に応じた位相
差信号を出力する位相比較手順、
（Ｂ）前記位相差信号中に含まれる高調波成分を除去し
、ローパスフィルタ信号を出力するローパスフィルタ手
順、
（Ｃ）前記ローパスフィルタ信号にもとづいて発振信号
が変化し、内部制御信号にもとづいて発振が停止する複
数の電圧制御発振回路を設ける手順、
（Ｄ）外部制御信号にもとづいて、前記複数の電圧制御
発振回路のいづれか１つを選択して動作させる前記内部
制御信号を、前記電圧制御発振回路に向けて送出する制
御手順、
とを含んで構成される。The phase synchronized oscillation method of the present invention includes: (A) a phase comparison procedure of comparing the phases of two signals and outputting a phase difference signal according to the phase difference; (B) harmonic components contained in the phase difference signal; (C) a step of providing a plurality of voltage-controlled oscillation circuits whose oscillation signals change based on the low-pass filter signal and whose oscillations stop based on an internal control signal; (D) a control procedure of transmitting the internal control signal to the voltage controlled oscillation circuit to select and operate one of the plurality of voltage controlled oscillation circuits based on an external control signal; configured.
次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図に示す位相同期発振回路は、
（Ａ）二つの信号を位相を比較し、位相差に応じた位相
差信号ｄを出力する位相比較回路１、（Ｂ）位相差信号
ｄ中に含まれる高調波成分を除去し、ローパスフィルタ
信号ｅを出力するローパスフィルタ回路２、
（Ｃ）ローパスフィルタ信号ｅにもとづいて発振信号が
変化し、内部制御信号ａ、ｂにもとづいて発振が停止す
る複数の電圧制御発振回路３，４（Ｄ）外部制御信号ｇ
にもとづいて、電圧制御発振回路３，４のいづれか１つ
を選択して動作させる内部制御信号ａ、ｂを、電圧制御
発振回路３．４に向けて送出する制御回路５、
とを含んで構成される。The phase synchronized oscillation circuit shown in Fig. 1 includes (A) a phase comparison circuit 1 that compares the phases of two signals and outputs a phase difference signal d according to the phase difference; (B) a phase difference signal included in the phase difference signal d; (C) A plurality of circuits in which the oscillation signal changes based on the low-pass filter signal e and the oscillation stops based on the internal control signals a and b. Voltage controlled oscillator circuit 3, 4 (D) external control signal g
a control circuit 5 that sends out internal control signals a and b to select and operate one of the voltage controlled oscillation circuits 3 and 4 based on the voltage controlled oscillation circuit 3.4. be done.
今、磁気ディスク装置のデータ転送速度が第１の速度で
あるとすると、発振器選択信号入力端子７がロウレベル
になり制御回路５は、内部制御信号ａをロウレベルにし
て電圧制御発振回路３を発振可能状態にし、内部制御信
号すをハイレベルにして電圧制御発振回路４を発振停止
状態にし、位相比較回路１には電圧制御発振回路３の発
振信号ｉが比較信号Ｃとして供給される。Now, assuming that the data transfer speed of the magnetic disk device is the first speed, the oscillator selection signal input terminal 7 becomes low level, and the control circuit 5 sets the internal control signal a to low level to enable the voltage controlled oscillation circuit 3 to oscillate. The voltage controlled oscillation circuit 4 is brought into a state where the oscillation is stopped by setting the internal control signal S to a high level, and the oscillation signal i of the voltage controlled oscillation circuit 3 is supplied to the phase comparison circuit 1 as the comparison signal C.
磁気ディスク装置のデータ転送速度が第２の速度である
とすると、発振器選択信号入力端子７がハイレベルにな
り制御回路５は、内部制御信号ａをハイレベルにして電
圧制御発振回路３を発振停止状態にし、内部制御信号す
をロウレベルにして電圧制御発振回路４を発振可能状態
にし、位相比較回路１には電圧制御発振回路４の発振信
号りが比較信号Ｃとして供給される。Assuming that the data transfer speed of the magnetic disk device is the second speed, the oscillator selection signal input terminal 7 becomes high level, and the control circuit 5 sets the internal control signal a to high level to stop the voltage controlled oscillation circuit 3 from oscillating. The voltage controlled oscillation circuit 4 is enabled to oscillate by setting the internal control signal S to a low level, and the oscillation signal of the voltage controlled oscillation circuit 4 is supplied to the phase comparison circuit 1 as a comparison signal C.
本発明の位相同期発振方法および回路は、データ転送速
度に従って電圧制御発振回路を切り替えることにより、
目的の周波数を発振するときの電圧制御発振回路の発振
周波数制御入力電圧を最適なポイントに設定することが
でき、また位相引込み領域の長さが変化しても位相同期
発振回路のループゲインを最適値にすることができるの
で、安定に位相引込みができるという効果がある。The phase synchronized oscillation method and circuit of the present invention switch the voltage controlled oscillation circuit according to the data transfer rate.
The oscillation frequency control input voltage of the voltage-controlled oscillator circuit when oscillating the target frequency can be set to the optimal point, and the loop gain of the phase-locked oscillator circuit can be optimized even if the length of the phase pull-in region changes. Since it can be set to a value, it has the effect of stably pulling in the phase.
第１図は本発明の一実施例を示すブロック図である。
１・・・・・・位相比較回路、２・・・・・ローパスフ
ィルタ、３，４・・・−・−重圧制御発振回路、５・・
・・・−制御回路。FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Phase comparator circuit, 2... Low pass filter, 3, 4...- Heavy pressure control oscillation circuit, 5...
...-control circuit.
Claims (3)
差信号を出力する位相比較手順、（Ｂ）前記位相差信号
中に含まれる高調波成分を除去し、ローパスフィルタ信
号を出力するローパスフィルタ手順、 （Ｃ）前記ローパスフィルタ信号にもとづいて発振信号
が変化し、内部制御信号にもとづいて発振が停止する複
数の電圧制御発振回路を設ける手順、 （Ｄ）外部制御信号にもとづいて、前記複数の電圧制御
発振回路のいづれか１つを選択して動作させる前記内部
制御信号を、前記電圧制御発振回路に向けて送出する制
御手順、 とを含むことを特徴とする位相同期発振方法。(1) (A) A phase comparison procedure that compares the phases of two signals and outputs a phase difference signal according to the phase difference; (B) removes harmonic components contained in the phase difference signal and filters it using a low-pass filter. a low-pass filter procedure for outputting a signal; (C) a procedure for providing a plurality of voltage-controlled oscillation circuits whose oscillation signal changes based on the low-pass filter signal and stops oscillation based on an internal control signal; (D) an external control signal A control procedure for transmitting the internal control signal to select and operate one of the plurality of voltage controlled oscillation circuits based on the voltage controlled oscillation circuit. Oscillation method.
差信号を出力する位相比較手段、（Ｂ）前記位相差信号
中に含まれる高調波成分を除去し、ローパスフィルタ信
号を出力するローパスフィルタ手段、 （Ｃ）前記ローパスフィルタ信号にもとづいて発振信号
が変化し、内部制御信号にもとづいて発振が停止する複
数の電圧制御発振回路を設ける手段、 とを含むことを特徴とする位相同期発振回路。(2) (A) Phase comparison means that compares the phases of two signals and outputs a phase difference signal according to the phase difference; (B) a low-pass filter that removes harmonic components contained in the phase difference signal; Low-pass filter means for outputting a signal; (C) means for providing a plurality of voltage-controlled oscillation circuits whose oscillation signal changes based on the low-pass filter signal and whose oscillation stops based on an internal control signal. A phase-locked oscillator circuit.
いづれか１つを選択して動作させる内部制御信号を、前
記電圧制御発振回路に向けて送出する制御手段を含む請
求項（２）記載の位相同期発振回路。(3) Claim (2) further comprising a control means for transmitting, to the voltage controlled oscillation circuit, an internal control signal for selecting and operating one of the plurality of voltage controlled oscillation circuits based on an external control signal. The phase-locked oscillator circuit described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057023A JPH03258021A (en) | 1990-03-07 | 1990-03-07 | Phase synchronism oscillating method and its circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2057023A JPH03258021A (en) | 1990-03-07 | 1990-03-07 | Phase synchronism oscillating method and its circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03258021A true JPH03258021A (en) | 1991-11-18 |
Family
ID=13043835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2057023A Pending JPH03258021A (en) | 1990-03-07 | 1990-03-07 | Phase synchronism oscillating method and its circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03258021A (en) |
-
1990
- 1990-03-07 JP JP2057023A patent/JPH03258021A/en active Pending
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