JPH0324946A - Preparation of copper clad laminated sheet - Google Patents

Preparation of copper clad laminated sheet

Info

Publication number
JPH0324946A
JPH0324946A JP15976289A JP15976289A JPH0324946A JP H0324946 A JPH0324946 A JP H0324946A JP 15976289 A JP15976289 A JP 15976289A JP 15976289 A JP15976289 A JP 15976289A JP H0324946 A JPH0324946 A JP H0324946A
Authority
JP
Japan
Prior art keywords
base material
copper
foil layer
conductive base
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15976289A
Other languages
Japanese (ja)
Inventor
Norio Kawachi
河内 範夫
Katsuro Aoshima
青島 克郎
Toshiro Miki
三木 利郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Electronics Co Ltd
Toagosei Co Ltd
Original Assignee
Meiko Electronics Co Ltd
Toagosei Co Ltd
Meiko Denshi Kogyo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Electronics Co Ltd, Toagosei Co Ltd, Meiko Denshi Kogyo Co Ltd filed Critical Meiko Electronics Co Ltd
Priority to JP15976289A priority Critical patent/JPH0324946A/en
Priority to US07/542,360 priority patent/US5096522A/en
Priority to DE69025500T priority patent/DE69025500T2/en
Priority to EP90111915A priority patent/EP0405369B1/en
Publication of JPH0324946A publication Critical patent/JPH0324946A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a copper clad laminated sheet equipped with a copper foil layer reduced in the number of pinholes and having isotropic mechanical characteristics by providing a process treating the surface of a conductive base material with a catalyst solution containing at least one noble metal selected from a group consisting of Pd, Pt, Ru, Rh, Au and Ag. CONSTITUTION:As a conductive base material, a belt or single plate composed of a material such as stainless steel, nickel or copper can be designated. A catalyst solution to be used contains at least one noble metal selected from a group consisting of Pd, Pt, Ru, Rh, Au and Ag as an essential component and there are three types of a colloid type, a solution type and a salt added type. Treatment such as degreasing or washing is applied to the surface of the conductive base material to bring the same to a clean state and the clean surface of the base material is treated with the catalyst solution. Next, the whole is washed with water and electrolytic copper plating treatment is applied thereto to form a copper foil layer with a predetermined thickness to the surface thereof and, after an insulating base material is superposed on the copper foil layer, the whole is bonded under heating and pressure to prepare an integrated laminate.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は銅張積層板の製造方法に関し、更に詳しくは、
ピンホールが少なく、しかも機械的特性が等方性である
銅箔層を備えた銅張積層板を転写法で製造する方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a copper-clad laminate, and more specifically,
The present invention relates to a method for producing a copper-clad laminate with a copper foil layer having few pinholes and isotropic mechanical properties by a transfer method.

(従来の技術) プリント配線板の素材である銅張積層板を製造する方法
の1つに転写法がある。
(Prior Art) One of the methods for manufacturing copper-clad laminates, which are materials for printed wiring boards, is a transfer method.

この転写l去で銅張積層板を製造する際には、まず、導
電性の金属ベルトや金属単板のような導電基材の表面に
、例えば、電解銅めっき処理を施して前記導電基材表面
に銅を電着することにより、所定厚みの銅箔層を形成す
る。ついで、この銅箔層の表面に、例えばプリプレグ薄
帯を熱圧着して、銅箔層とプリプレグ薄帯を一体に積層
する。その後、この一体積層体から前記した導電基材の
みを剥離して、プリプレグ薄帯側に銅箔層を残置せしめ
る。かくして、絶縁基材の表面には、銅箔層が転写され
た銅張積層板が得られる。
When manufacturing a copper-clad laminate using this transfer method, first, the surface of a conductive base material such as a conductive metal belt or a metal veneer is subjected to, for example, electrolytic copper plating treatment to coat the conductive base material. A copper foil layer of a predetermined thickness is formed by electrodepositing copper on the surface. Next, a prepreg ribbon, for example, is thermocompression bonded to the surface of this copper foil layer to integrally laminate the copper foil layer and the prepreg ribbon. Thereafter, only the conductive base material described above is peeled off from this single laminate, leaving the copper foil layer on the prepreg ribbon side. In this way, a copper-clad laminate with a copper foil layer transferred onto the surface of the insulating base material is obtained.

(発明が解決しようとする課題) ところで、最近は、プリント配線板の高機能化というこ
とから、各種素子の高密度実装が要求され、それに伴な
い微細な回路パターンを形成できる高密度プリント配線
板の研究が進められている。
(Problem to be Solved by the Invention) Recently, as printed wiring boards have become more sophisticated, there has been a demand for high-density mounting of various elements. Research is underway.

このような高密度プリント配線板を得るためには、その
厚みが極めて薄い銅箔層を備えた極薄銅張積層板を素材
とすることが有利である。
In order to obtain such a high-density printed wiring board, it is advantageous to use an ultra-thin copper-clad laminate having an extremely thin copper foil layer as a material.

一般に、ピンホールが存在していると、外観が悪く、商
品価値の低下を招く。したがって、極薄銅張積層板を転
写法で製造するに際して、ピンホールを発生させないた
めの努力が重ねられている。
Generally, the presence of pinholes gives a poor appearance and reduces commercial value. Therefore, when manufacturing ultra-thin copper-clad laminates by the transfer method, efforts are being made to prevent pinholes from occurring.

転写法におけるビンホールの発生原因は必ずしも解明さ
れているわけではないが、経験的には、用いる導電基材
の表面状態と、使用めっき浴を含めた電解めっき処理時
の条件に大きく規定されるということが知られている。
The cause of the occurrence of bottle holes in the transfer method is not necessarily clear, but experience has shown that it is largely determined by the surface condition of the conductive substrate used and the conditions during electrolytic plating, including the plating bath used. It is known.

例えば、転写法で用いる導電基材は、通常、ステンレス
スチール、ニッケル、銅のようナ材料のインゴットを板
状またはシート状に圧延加工して製造されているが、そ
の表面には、加工時のオイルピットのような気孔、溶製
時に生成する非金属介在物や金属間化合物等の組織欠陥
が不可避的に存在している。このような導電基材の表面
に銅箔層を形成した場合、銅の複製精度は0.05μm
程度であるため、前記した欠陥はそのまま形成された銅
箔層に複製されることになる。とくに、導電基材の表面
にアンダーカット状の気孔が存在している場合には、電
解銅めっき処理時に電着銅はこの気孔周辺部分に集中的
に堆積する。そして、形成された銅箔層に絶縁基材を積
層したのちこの絶縁基材を分離すると、前記アンダーカ
ット状気孔の一部に堆積している電着銅が引きちぎられ
て導電基材側に残留することになる。その結果、得られ
た銅張積層板の銅箔層には、アンダーカット状気孔の部
分に相当する個所がピンホールとして発現する。
For example, the conductive substrate used in the transfer method is usually manufactured by rolling an ingot of a material such as stainless steel, nickel, or copper into a plate or sheet. Microstructural defects such as pores such as oil pits, non-metallic inclusions and intermetallic compounds generated during melting are unavoidable. When a copper foil layer is formed on the surface of such a conductive base material, the copper replication accuracy is 0.05 μm.
Since the defects are of a certain extent, the defects described above will be directly replicated in the formed copper foil layer. In particular, when undercut-shaped pores are present on the surface of the conductive base material, electrodeposited copper is concentrated around the pores during electrolytic copper plating. Then, when an insulating base material is laminated on the formed copper foil layer and this insulating base material is separated, the electrodeposited copper deposited in a part of the undercut pores is torn off and remains on the conductive base material side. I will do it. As a result, pinholes appear in the copper foil layer of the resulting copper-clad laminate at locations corresponding to the undercut pores.

また、表面欠陥が表面に露出する非金属介在物や金属間
化合物である場合には、その導電性が基地金属と異なる
ため、導電基材の表面では、導電性の高低が生ずる。す
なわち、導電基材の表面において導電性のばらつきが生
ずる。そのため、電解銅めっき処理時には、導電基材の
表面における銅の電着状態が場所によって異なることと
なり、形成された銅箔層にはピンホールの発生が認めら
れるようになる。
Further, if the surface defect is a nonmetallic inclusion or an intermetallic compound exposed on the surface, the conductivity thereof is different from that of the base metal, so that the surface of the conductive base material has high and low conductivity. That is, variations in conductivity occur on the surface of the conductive base material. Therefore, during electrolytic copper plating, the state of copper electrodeposition on the surface of the conductive base material differs depending on the location, and pinholes are observed in the formed copper foil layer.

導電基材の表面における組織欠陥のうち、上記したよう
な物理的欠陥の場合には、導電基材の表面を研磨してそ
の欠陥を除去することも可能であるが、しかし、欠陥が
基材そのものに含まれている非金属介在物や金属間化合
物の場合には、表面研磨をしてもその欠陥を除去するこ
とができない。
Among the structural defects on the surface of the conductive base material, in the case of physical defects such as those described above, it is possible to remove the defect by polishing the surface of the conductive base material. In the case of non-metallic inclusions or intermetallic compounds contained therein, the defects cannot be removed even by surface polishing.

一方、電解銅めっき処理の条件からピンホール問題を考
えると、一般に、ビロリン酸銅や青化銅のめっき浴を用
いてかつ低電流密度で銅めっきを行なうと、これらの浴
に添加されるキレート剤の働きにより銅の電着がコント
ロールされて、形成された銅箔層へのピンホールの発生
は少なくなる傾向があることが知られている。
On the other hand, when considering the pinhole problem from the conditions of electrolytic copper plating, it is generally found that when copper plating is performed using copper birophosphate or copper cyanide plating baths at low current density, chelates added to these baths are It is known that the electrodeposition of copper is controlled by the action of the agent, and the occurrence of pinholes in the formed copper foil layer tends to be reduced.

しかしながら、この場合には、銅の電着速度は遅く、生
産性は高くないという問題がある。
However, in this case, there is a problem that the electrodeposition rate of copper is slow and the productivity is not high.

このように、従来の転写法においては、用いる導電基材
の表面に存在する組織欠陥のため、形成した銅箔層には
ピンホールが多数発生してしまう。
As described above, in the conventional transfer method, many pinholes are generated in the formed copper foil layer due to structural defects existing on the surface of the conductive base material used.

その結果、高密度プリント配線板の素材として有用な極
薄銅張積層板を転写法で製造する場合には、不可避的に
その生産性が低下してしまうし、また良品率も低下して
しまうという問題があった。
As a result, when manufacturing ultra-thin copper-clad laminates, which are useful as materials for high-density printed wiring boards, by the transfer method, productivity inevitably decreases, and the yield rate also decreases. There was a problem.

また、導電基材は、その製造に際し、圧延加工時におけ
る加工、および銅箔層形成前の前処理、例えば研磨工程
で、基材表面に異方性が発現する。
Further, when manufacturing the conductive base material, anisotropy is developed on the surface of the base material during rolling processing and pretreatment before forming the copper foil layer, such as a polishing step.

そのため、この基材表面に形成した銅箔層もその機械的
特性に異方性が生じて、例えば、銅箔層の縦横方向では
伸び率に差が生ずることがある。銅箔層にこのような異
方性が生ずると、銅張積層板からプリント回路板を形成
するときの加熱を伴なう工程を複数回経由する際に、回
路の信頼性に悪影響が及ぶという問題があった。
Therefore, the copper foil layer formed on the surface of this base material also has anisotropy in its mechanical properties, and for example, the elongation rate of the copper foil layer may differ in the longitudinal and lateral directions. If such anisotropy occurs in the copper foil layer, it will adversely affect the reliability of the circuit when it goes through multiple heating processes when forming printed circuit boards from copper-clad laminates. There was a problem.

本発明は上記した問題を解決し、電解銅めっき処理時の
条件とは無関係に、ピンホールが少なく、しかも機械的
特性が等方性である銅箔層を備えた銅張積層板の製造方
法の提供を目的とする。
The present invention solves the above problems and is a method for producing a copper-clad laminate having a copper foil layer with few pinholes and isotropic mechanical properties, regardless of the conditions during electrolytic copper plating. The purpose is to provide.

(課題を解決するための手段・作用) 上記した目的を達成するために、本発明においテハ、導
電基材の表面を、Pd,  PL Ru, Rh,A 
u + A gの群から選ばれる少なくとも1種の貴金
属を含有する触媒液で処理する工程(以下、第1工程と
いう);導電基材の前記処理表面に電解銅めっき処理を
施して銅箔層を形成する工程; (以下、第2工程とい
う)前記銅箔層に絶縁基材を熱圧着して積層体とする工
程(以下第3工程という);および、前記積層体から導
電基材のみを分離する工程(以下、第4工程という);
を備えていることを特徴とする銅張積層板の製造方法が
提供される。
(Means and effects for solving the problem) In order to achieve the above-mentioned object, in the present invention, the surface of the conductive base material is made of Pd, PL Ru, Rh, A.
A step of treating with a catalyst solution containing at least one noble metal selected from the group of u + A g (hereinafter referred to as the first step); electrolytic copper plating treatment is performed on the treated surface of the conductive base material to form a copper foil layer. (hereinafter referred to as the second step) a step of thermocompression bonding an insulating base material to the copper foil layer to form a laminate (hereinafter referred to as the third step); and a step of removing only the conductive base material from the laminate. Separating step (hereinafter referred to as the fourth step);
Provided is a method for manufacturing a copper-clad laminate, comprising:

本発明は、上記した第l工程に最大の特徴を有するもの
であり、以後の工程に関しては、従来からの転写法の場
合と基本的に変わることはない。
The present invention has the greatest feature in the first step described above, and the subsequent steps are basically the same as in the case of the conventional transfer method.

まず、第1工程は、導電基材の表面を後述する触媒液で
処理することにより、該導電基材の表面にPd,Pt,
Ru,Rh.Au.Agの微細な粒子を一様に吸着せし
める工程である。
First, in the first step, the surface of the conductive base material is treated with a catalyst liquid to be described later, so that the surface of the conductive base material is coated with Pd, Pt,
Ru, Rh. Au. This is a process in which fine particles of Ag are uniformly adsorbed.

用いる導電基材は格別限定されるものではなく、従来か
ら転写法で使用されている材料、形状のものであれば何
であってもよい。例えば、ステンレススチール、ニッケ
ル、銅などの材料のベルトや単板などをあげることがで
きる。
The conductive base material to be used is not particularly limited, and may be any material and shape that has been conventionally used in transfer methods. Examples include belts and veneers made of materials such as stainless steel, nickel, and copper.

用いる触媒液は、Pd,  Pt, Ru, Rh, 
Au,Agの群から選ばれる少なくともl種の貴金属を
必須成分として含有し、プラスチックスのような非導電
性材料の表面に無電解めっきを施すときに使用されるも
のである。この触媒液には、コロイド型,溶液型,塩添
加型の3つのタイプがある。
The catalyst liquid used is Pd, Pt, Ru, Rh,
It contains as an essential component at least one noble metal selected from the group of Au and Ag, and is used when performing electroless plating on the surface of non-conductive materials such as plastics. There are three types of this catalyst liquid: colloid type, solution type, and salt-added type.

本発明においては、これら3つのタイプのいずれをも使
用することができるが、とくにコロイド型のものが取扱
い易く好適である。また、触媒液に含有される貴金属と
しては、Pdが比較的安価で、かつ入手し易く好ましい
In the present invention, any of these three types can be used, but a colloid type is particularly suitable because it is easy to handle. Further, as the noble metal contained in the catalyst liquid, Pd is preferable because it is relatively inexpensive and easily available.

例えば、Pd−Sn系触媒液のコロイドタイプのものは
、PdCltとSnCj’zと多量のH(lとから成る
もので、Sn”+の還元力により生或する金属Pdがα
−Sn酸の保護コロイドとしてコロイド状に液内に分散
しているものである。
For example, a colloid type Pd-Sn catalyst liquid is composed of PdClt, SnCj'z, and a large amount of H(l), and the metal Pd produced by the reducing power of Sn''+ is
- It is dispersed in a liquid in a colloidal form as a protective colloid for Sn acid.

例えばコロイド型の触媒液で導電基材の表面を処理する
と、前記した貴金属のコロイド粒子が導電基材の表面に
均一に吸着される。その結果、導電基材の表面に露出さ
れていた非金属介在物や金属間化合物はこれらコロイド
粒子によって被覆される。そして、その後、貴金属を取
巻く保護コロイドを例えば塩酸洗浄、水洗などの処理に
より除去すれば、導電基材の全面は微細な貴金属粒子で
被覆された状態になる。その結果、導電基材の表面にお
いては、導電性のばらつきが解消されて、吸着する貴金
属微粒子の作用で均質な導電性が付与されることになる
For example, when the surface of a conductive substrate is treated with a colloidal catalyst liquid, the noble metal colloid particles described above are uniformly adsorbed on the surface of the conductive substrate. As a result, nonmetallic inclusions and intermetallic compounds exposed on the surface of the conductive base material are covered with these colloid particles. Then, if the protective colloid surrounding the noble metal is removed by, for example, hydrochloric acid washing or water washing, the entire surface of the conductive base material will be covered with fine noble metal particles. As a result, variations in conductivity are eliminated on the surface of the conductive base material, and homogeneous conductivity is imparted by the action of the adsorbed noble metal fine particles.

また、次段の電解銅めっき処理時においては、この吸着
している貴金属粒子が電着銅結晶の或長核として作用す
るが、この貴金属粒子は極めて微細であるため、電着銅
は大きな結晶として成長しずらくなる。すなわち、次段
の第2工程で形成される導電基材表面の銅箔層は、微細
結晶の集合体となるため、ピンホールの発生は有効に阻
止されるようになる。
In addition, during the next electrolytic copper plating process, these adsorbed noble metal particles act as long nuclei of electrodeposited copper crystals, but since these noble metal particles are extremely fine, the electrodeposited copper does not form large crystals. As a result, it becomes difficult to grow. That is, the copper foil layer formed on the surface of the conductive base material in the next second step becomes an aggregate of fine crystals, so that the generation of pinholes is effectively prevented.

用いる触媒液において、貴金属濃度は100〜150p
pmであることが好ましい。これらの濃度、とくに貴金
属の濃度が下限値より低い場合は、上記した効果が充分
に発揮されず、形成された銅箔層におけるピンホールの
発生数は多くなり、また発生ビンホールも大きくなるか
らである。濃度が上限値よりも高い場合は、その効果が
飽和に達して経済的に不利となるからである。
In the catalyst liquid used, the noble metal concentration is 100 to 150 p.
Preferably, it is pm. If the concentration of these, especially the concentration of precious metals, is lower than the lower limit, the above effects will not be fully exhibited, and the number of pinholes generated in the formed copper foil layer will increase, and the size of the generated bottleholes will increase. be. This is because if the concentration is higher than the upper limit, the effect reaches saturation and becomes economically disadvantageous.

この第1工程においては、まず、所定の導電基材の表面
に脱脂、水洗等の処理を施して、表面を清浄な状態にす
る。ついで、この表面を上記した触媒液で処理する。処
理方法としては、格別限定されないが、触媒液に導電基
材を浸漬する方法が好適である。この浸漬処理の場合、
浸漬時間は30〜60秒程度が好適である。浸漬特間が
短すぎる場合は、導電基材表面の改質は不充分で形成し
た銅箔層におけるビンホールの発生を抑制できず、また
長すぎる場合は効果が飽和に達して無意味であるからで
ある。
In this first step, first, the surface of a predetermined conductive base material is subjected to treatments such as degreasing and washing with water to make the surface clean. This surface is then treated with the above catalyst liquid. Although the treatment method is not particularly limited, a method of immersing the conductive base material in a catalyst liquid is suitable. In this immersion process,
The immersion time is preferably about 30 to 60 seconds. If the immersion period is too short, the surface modification of the conductive base material is insufficient and the formation of bottle holes in the formed copper foil layer cannot be suppressed, and if it is too long, the effect reaches saturation and is meaningless. It is.

触媒液による処理後は、全体を水洗したのち、次の第2
工程に移送する。
After the treatment with the catalyst liquid, the whole body is washed with water, and then the next second treatment is carried out.
Transfer to process.

なお、触媒液による処理に先立ち、導電基材の表面を研
磨しておくと、ピンホールの発生を一層有効に抑制する
ことができる。このことは、導電基材の表面粗度が大き
くなると、電解銅めっき処理時に水素過電圧が低下して
水素発生が激しくなり、その結果、形成された銅箔層に
ピンホールが発生し易くなるという現象が抑制されるた
めであると考えられる。また、研磨することにより、導
電基材表面の不規則な凹凸はなくなるとともに、新鮮な
表面状態になるので、そのことがピンホールの発生防止
に貢献するものとも考えられる。好ましい表面粗度は、
0、1−1 llm程度である。
Note that, if the surface of the conductive base material is polished prior to the treatment with the catalyst liquid, the generation of pinholes can be more effectively suppressed. This means that when the surface roughness of the conductive base material increases, the hydrogen overvoltage decreases during electrolytic copper plating and hydrogen generation becomes more intense, and as a result, pinholes are more likely to occur in the formed copper foil layer. This is thought to be because the phenomenon is suppressed. Further, by polishing, irregular irregularities on the surface of the conductive base material are eliminated and a fresh surface condition is obtained, which is considered to contribute to the prevention of pinholes. The preferred surface roughness is
It is about 0.1-1 llm.

第2工程は、第1工程を経て得られた導電基材に電解銅
めっき処理を施して、その表面に所定厚みの銅箔層を形
成する工程である。
The second step is a step of subjecting the conductive base material obtained through the first step to electrolytic copper plating to form a copper foil layer of a predetermined thickness on its surface.

このときの処理条件、例えば、めっき浴の組成,浴温度
,浴のpH,めっき時の電流密度,めっき時間などは格
別限定されるものではなく、目的とする銅箔層の関係で
、適宜好適な条件を設定すればよい。
The processing conditions at this time, such as the composition of the plating bath, the bath temperature, the pH of the bath, the current density during plating, and the plating time, are not particularly limited. All you have to do is set the conditions.

この場合、電着銅の堆積速度を15μm/min以上と
する高速めっき法や、比較的遅い堆積速度のめりきl去
のいずれを適用しても、形成される銅箔層におけるピン
ホールの発生は抑制される。それゆえ、この工程におい
て、高速めっき法を適用すれば、極めて高能率で銅箔層
を形成することができる。
In this case, regardless of whether a high-speed plating method in which the electrodeposited copper is deposited at a deposition rate of 15 μm/min or more or a plating method with a relatively slow deposition rate is applied, pinholes will not occur in the copper foil layer that is formed. suppressed. Therefore, in this process, if a high-speed plating method is applied, the copper foil layer can be formed with extremely high efficiency.

第3工程は、第2工程で形成された銅箔層に絶縁基材を
重ね合わせたのち、全体を熱圧着して一体の積層体を製
造する工程である。
The third step is a step of superimposing an insulating base material on the copper foil layer formed in the second step, and then thermocompression bonding the whole to produce an integrated laminate.

絶縁基材としては、従来から転写法で用いられているも
のであれば何であってもよく、格別限定されるものでは
ない。通常、ガラス繊維にエポキシ樹脂等を含浸せしめ
たのちそれを半硬化状態(Bステージ)にしたプリプレ
グが好適である。
The insulating base material is not particularly limited and may be any material that has been conventionally used in transfer methods. Usually, prepreg, which is made by impregnating glass fiber with epoxy resin or the like and then bringing it into a semi-cured state (B stage), is suitable.

また、熱圧着の条件もまた、格別限定されるものではな
く、従来の転写法の場合と同様であればよい。
Furthermore, the conditions for thermocompression bonding are not particularly limited either, as long as they are the same as in the case of conventional transfer methods.

なお、銅箔層の表面と絶縁基材との密着性を高めるため
に、前記した第2工程において、導電基材表面に形成さ
れた銅箔層の表面に、更に別のめっき条件で銅めっきを
施し、その表面を粗度が1〜5μm程度となるように粗
面化することが好ましい。
In addition, in order to improve the adhesion between the surface of the copper foil layer and the insulating base material, in the second step described above, the surface of the copper foil layer formed on the surface of the conductive base material is further copper plated under different plating conditions. It is preferable to roughen the surface to a roughness of about 1 to 5 μm.

第4工程は、第3工程で得られた積層体から導電基材の
みを分離する工程である。
The fourth step is a step of separating only the conductive base material from the laminate obtained in the third step.

この工程を経ることにより、絶縁基材側に銅箔層が転写
され、ここに目的とする銅張積層板が得られる。
By going through this process, the copper foil layer is transferred to the insulating base material side, and the intended copper-clad laminate is obtained here.

(発明の実施例) 実施例1〜4,比較例1.2 縦510mm,幅340mm,厚み1mm、表面粗度が
l〜2.0μmであり、ハードニング処理を施したステ
ンレススチール(SUS 3 0 4)板を6枚用意し
た。なお、このスチール板は、縦方向に圧延加工が施さ
れているものであった。
(Examples of the Invention) Examples 1 to 4, Comparative Example 1.2 Measures 510 mm in length, 340 mm in width, 1 mm in thickness, and has a surface roughness of 1 to 2.0 μm, and is made of hardened stainless steel (SUS 30 4) Six boards were prepared. Note that this steel plate had been rolled in the longitudinal direction.

このうちの4枚の片面につき、オシレーション付ロータ
リー研削装置を用いることにより、その表面の粗度を0
.5〜0.8μmにした。
By using a rotary grinding device with oscillation on one side of four of these sheets, the roughness of the surface was reduced to zero.
.. The thickness was set to 5 to 0.8 μm.

6枚の単板すべてに脱脂,酸洗,水洗処理を施してその
表面を清浄にしたのち、研削処理を施した単板4枚、研
削処理をしていない単板2枚については、第1表に示し
た時間、触媒液に浸漬した。
After degreasing, pickling, and water washing all six veneers to clean their surfaces, the four veneers that were ground and the two veneers that were not ground were cleaned in the first step. It was immersed in the catalyst solution for the time shown in the table.

このときの触媒液は、Pd−Sn系アクチベータ(コロ
イド型,Pd濃度130ppm)である。
The catalyst liquid at this time was a Pd-Sn activator (colloid type, Pd concentration 130 ppm).

これらの単板を触媒液から取り出し、充分に水洗した。These veneers were taken out from the catalyst solution and thoroughly washed with water.

ついで、6枚の単板全てに、下記条件で高速めっきを施
し厚み5μmの銅箔層を形成した。
Next, all six veneers were subjected to high-speed plating under the following conditions to form a copper foil layer with a thickness of 5 μm.

めっき浴: CLISO4” 5Hz0150g/jl
’,H2SO42oog/l, 浴  温:60゜C, 陽極:白金・鉛極,めっき浴の
単板表面における接岐スピード:7 m/sec, 電流密度:80A/drrl’,めっき時間=15秒。
Plating bath: CLISO4” 5Hz0150g/jl
', H2SO42oog/l, bath temperature: 60°C, anode: platinum/lead electrode, plating bath speed on the veneer surface: 7 m/sec, current density: 80 A/drrl', plating time = 15 seconds.

得られた各単板の銅箔層側の表面を、厚み50μmのガ
ラスーエポキシ樹脂プリプレグの片面に重ね合わせ、温
度170℃、圧力25kg/carで1時間熱圧着した
のち、30分かけて30℃にまで冷却し、単板を剥離し
た。
The surface of the copper foil layer side of each of the obtained veneers was superimposed on one side of a glass-epoxy resin prepreg with a thickness of 50 μm, and thermocompression bonded at a temperature of 170°C and a pressure of 25 kg/car for 1 hour. It was cooled to ℃ and the veneer was peeled off.

単板は円滑に剥離され、ここに極薄銅張積層板が得られ
た。
The veneer was peeled off smoothly, and an ultra-thin copper-clad laminate was obtained.

これらの極薄銅張積層板を暗室中のライトテーブルに置
き、銅箔層の表面を倍率100倍の実体顕微鏡で観察し
た。5 1 0mmX 3 4 0m+++の面積内に
存在するピンホールの個数、大きさを計測した。
These ultra-thin copper-clad laminates were placed on a light table in a dark room, and the surface of the copper foil layer was observed using a stereomicroscope with a magnification of 100 times. The number and size of pinholes existing within an area of 510 mm x 340 m++ were measured.

また、各銅箔層をそれぞれ絶縁基材から注意深く剥離し
て、それら銅箔層の縦方向,横方向における伸び率(%
)を測定し、その縦・横比を算出した。以上の結果を一
括して第1表に示した。
In addition, each copper foil layer was carefully peeled off from the insulating base material, and the elongation rate (%) of the copper foil layer in the vertical and horizontal directions was measured.
) was measured and its length/width ratio was calculated. The above results are collectively shown in Table 1.

(以下余白) 表の結果から明らかなように、表面粗度が同一であって
も、触媒液で処理した場合は、ピンホールの発生個数が
著しく減少する(実施例3と比較例l)。また、触媒液
処理を施す場合、表面粗度を小さくしたものは、明らか
にピンホールの大きさが小さくなる(実施例1と実施例
4)。
(The following is a blank space) As is clear from the results in the table, even if the surface roughness is the same, when treated with a catalyst liquid, the number of pinholes generated is significantly reduced (Example 3 and Comparative Example 1). Furthermore, when the catalyst liquid treatment is applied, the size of pinholes is clearly reduced when the surface roughness is reduced (Example 1 and Example 4).

また、本発明方広で形成される銅箔層はその機械的特性
が等方性を示す。
Further, the mechanical properties of the copper foil layer formed using the method of the present invention are isotropic.

これは、単板が縦方向に圧延加工されていることに基づ
く表面の異方性を、微細な貴金属粒子が吸着してめっき
発生核となることにより緻密な析出となり、結晶成長の
重要部分である初期析出機構に関し、物性の等方性に影
響を与えるためと考えられる。
This is due to the surface anisotropy caused by the longitudinal rolling of the veneer, which is caused by fine precious metal particles adsorbing and becoming plating generation nuclei, resulting in dense precipitation, which is an important part of crystal growth. This is thought to be due to a certain initial precipitation mechanism that affects isotropy of physical properties.

(発明の効果) 以上の説明で明らかなように、本発明方法によれば、導
電基材の表面欠陥が触媒液による処理によって生成した
貴金属粒子で均一に被覆されることになり、その結果、
導電基材の表面には均一な銅箔層の形戊が可能となって
、ビンホールの発生が抑止されることになる。
(Effects of the Invention) As is clear from the above explanation, according to the method of the present invention, the surface defects of the conductive base material are uniformly covered with the noble metal particles generated by the treatment with the catalyst liquid, and as a result,
It becomes possible to form a uniform copper foil layer on the surface of the conductive base material, thereby suppressing the occurrence of bottle holes.

それゆえ、本発明方法は、高密度プリント配線板の素材
として賞用されているが、しかしピンホール発生問題を
抱えている極薄銅張積層板の製造に適用して極めて有効
である。
Therefore, the method of the present invention is extremely effective when applied to the production of ultra-thin copper-clad laminates, which are prized as materials for high-density printed wiring boards, but suffer from the problem of pinhole formation.

Claims (2)

【特許請求の範囲】[Claims] (1)導電基材の表面を、Pd、Pt、Ru、Rh、A
u、Agの群から選ばれる少なくとも1種の貴金属を含
有する触媒液で処理する工程; 導電基材の前記処理表面に電解銅めっき処理を施して銅
箔層を形成する工程; 前記銅箔層に絶縁基材を熱圧着して積層体とする工程;
および、 前記積層体から導電基材のみを分離する工程;を備えて
いることを特徴とする銅張積層板の製造方法。
(1) The surface of the conductive base material is Pd, Pt, Ru, Rh, A
a step of treating with a catalyst solution containing at least one noble metal selected from the group of u, Ag; a step of performing electrolytic copper plating on the treated surface of the conductive base material to form a copper foil layer; A step of thermocompression bonding an insulating base material to form a laminate;
and a step of separating only the conductive base material from the laminate. A method for producing a copper-clad laminate, the method comprising:
(2)前記触媒液による処理に先立って、前記導電基材
の表面に研磨処理を施す請求項1記載の銅張積層板の製
造方法。
(2) The method for manufacturing a copper-clad laminate according to claim 1, wherein the surface of the conductive base material is subjected to a polishing treatment prior to the treatment with the catalyst liquid.
JP15976289A 1989-06-23 1989-06-23 Preparation of copper clad laminated sheet Pending JPH0324946A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP15976289A JPH0324946A (en) 1989-06-23 1989-06-23 Preparation of copper clad laminated sheet
US07/542,360 US5096522A (en) 1989-06-23 1990-06-22 Process for producing copper-clad laminate
DE69025500T DE69025500T2 (en) 1989-06-23 1990-06-22 Process for producing a copper-clad laminate
EP90111915A EP0405369B1 (en) 1989-06-23 1990-06-22 Process for producing copperclad laminate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15976289A JPH0324946A (en) 1989-06-23 1989-06-23 Preparation of copper clad laminated sheet

Publications (1)

Publication Number Publication Date
JPH0324946A true JPH0324946A (en) 1991-02-01

Family

ID=15700714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15976289A Pending JPH0324946A (en) 1989-06-23 1989-06-23 Preparation of copper clad laminated sheet

Country Status (1)

Country Link
JP (1) JPH0324946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007266316A (en) * 2006-03-28 2007-10-11 Matsushita Electric Works Ltd Stainless transfer base having plated circuit layer, circuit board, and component built-in module
US7641169B2 (en) 2003-05-29 2010-01-05 Sumitomo Metal Industries, Ltd. Substrate for a stamper

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7641169B2 (en) 2003-05-29 2010-01-05 Sumitomo Metal Industries, Ltd. Substrate for a stamper
JP2007266316A (en) * 2006-03-28 2007-10-11 Matsushita Electric Works Ltd Stainless transfer base having plated circuit layer, circuit board, and component built-in module
JP4508140B2 (en) * 2006-03-28 2010-07-21 パナソニック電工株式会社 Built-in module

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