JPH03228321A - Plasma cvd device - Google Patents
Plasma cvd deviceInfo
- Publication number
- JPH03228321A JPH03228321A JP2366190A JP2366190A JPH03228321A JP H03228321 A JPH03228321 A JP H03228321A JP 2366190 A JP2366190 A JP 2366190A JP 2366190 A JP2366190 A JP 2366190A JP H03228321 A JPH03228321 A JP H03228321A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- etching
- semiconductor substrate
- substrate
- holding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 36
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 18
- 238000007599 discharging Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は少くとも一対の対向する電極を具備し、電極の
一方に半導体基板を載せ、電極対間に高電圧を印加し、
放電を生じさせて半導体基板上７こ成膜を行なうプラズ
マＣＶＤ装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention comprises at least a pair of opposing electrodes, a semiconductor substrate is placed on one of the electrodes, a high voltage is applied between the pair of electrodes,
The present invention relates to a plasma CVD apparatus that forms a film on a semiconductor substrate by generating discharge.
従来のプラズマＣＶＤ装置は第３図に示す様）こ、真空
処理容器１内に保持電極２１と対向電極２０とを設け、
保持電極２１に半導体基板３を載せて保持し、この真空
処理容器１内に反応ガスをガス導入口４より導入しなが
ら放電用電源５により画電極２０．２１間に高電圧を印
加して放電を生じさせ、半導体基板３上に気相成長を行
なわせる構造となっていた。尚、保持電極２１はヒータ
ー６によって加熱され、排気ガスは排気ロアから排出さ
れる。A conventional plasma CVD apparatus (as shown in FIG. 3) is provided with a holding electrode 21 and a counter electrode 20 in a vacuum processing chamber 1.
The semiconductor substrate 3 is placed and held on the holding electrode 21, and a high voltage is applied between the picture electrodes 20 and 21 by the discharge power source 5 while introducing a reactive gas into the vacuum processing container 1 from the gas inlet 4 to discharge the substrate. The structure was such that vapor phase growth was performed on the semiconductor substrate 3. Note that the holding electrode 21 is heated by the heater 6, and the exhaust gas is discharged from the exhaust lower.
上述した従来のプラズマＣＶＤ装置は、保持電極２１に
半導体基板３を載置し、電極間に放電を斤なわせる構造
である為、プラズマＣＶＤ工程前り集積回路製造工程に
おいて、裏面に必然的に形成される自然酸化膜や、拡散
炉における熱酸化膜等の薄い絶縁膜により、半導体基板
３と保持電極２１との間にある接触抵抗を生じる。The conventional plasma CVD apparatus described above has a structure in which the semiconductor substrate 3 is placed on the holding electrode 21 and a discharge is generated between the electrodes. A contact resistance is generated between the semiconductor substrate 3 and the holding electrode 21 due to a thin insulating film such as a naturally oxidized film formed or a thermal oxidized film formed in a diffusion furnace.
二の接触抵抗は、半導体基板毎々の裏面状態により異な
る為に、放電中における半導体基板の電位に差異が生じ
、電位差による各半導体基板に集中するプラズマ密度の
違いから、成長膜の膜質が半導体基板毎に不均一になる
ため、半導体装置の歩留りを低下させるという欠点を生
じている６〔課題を解決するための手段〕
本発明のプラズマＣＶＤ装置は、半導体基板を保持する
円筒状の保持電極と、この保持電極に対向して設けられ
た対向電極と、前記保持電極の内側に設けられエツチン
グガスを９部させ放電により半導体基板の裏面をエツチ
ングするためのエツチング用電極と、前記エツチングさ
れた半導体基板の裏面と前記保持電極とを電気的に接続
する手段とを含んで構成される。The second contact resistance differs depending on the condition of the back surface of each semiconductor substrate, so there is a difference in the potential of the semiconductor substrate during discharge, and due to the difference in plasma density concentrated on each semiconductor substrate due to the potential difference, the quality of the grown film is different from that of the semiconductor substrate. 6 [Means for Solving the Problem] The plasma CVD apparatus of the present invention has a cylindrical holding electrode for holding a semiconductor substrate, and a cylindrical holding electrode for holding a semiconductor substrate. , a counter electrode provided to face the holding electrode, an etching electrode provided inside the holding electrode for etching the back surface of the semiconductor substrate by applying 9 parts of etching gas and discharging the etched semiconductor; The device includes means for electrically connecting the back surface of the substrate and the holding electrode.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の模式断面図である。FIG. 1 is a schematic sectional view of a first embodiment of the present invention.
第１図において、真空処理容器１内には半導体基板３を
保持する円筒状の保持電極２１Ａと対向電極２０とが設
けられており、そして特に保持電極２１Ａの内側には、
エツチングカスを噴出させるエツチング用電極８が設け
られている。そしてこのエツチング用を極８はモーター
等からなるエツチング用電極駆動部１１により上下動し
、半導体基板３の裏面に接触できるように構成されてい
る。In FIG. 1, a cylindrical holding electrode 21A for holding a semiconductor substrate 3 and a counter electrode 20 are provided in a vacuum processing container 1, and in particular, inside the holding electrode 21A,
An etching electrode 8 for spouting etching scum is provided. The etching electrode 8 is moved up and down by an etching electrode drive section 11 consisting of a motor or the like, so that it can come into contact with the back surface of the semiconductor substrate 3.
次に水弟１の実施例の動作について説明する。Next, the operation of the embodiment of Sui-Tei 1 will be explained.
エツチング用電極８が半導体基板３の裏面より離れ、か
つ、スイッチ１３が開いた状態で、例えばＣＦ４＋０２
等のエツチングガスをエツチングガス導入口９より導入
しなか、エツチング用電極８と、半導体基板３との間に
エツチング用電源１２により放電を生じさせることによ
り、半導体基板３の裏面に形成された薄い絶縁膜はエツ
チングされてなくなる。尚、エツチングガスはエツチン
グガス排気口１０より排気される。For example, when the etching electrode 8 is separated from the back surface of the semiconductor substrate 3 and the switch 13 is open,
A thin film formed on the back surface of the semiconductor substrate 3 is produced by causing an electric discharge between the etching electrode 8 and the semiconductor substrate 3 by the etching power supply 12 while introducing etching gas such as etching gas through the etching gas inlet 9. The insulating film is etched away. Incidentally, the etching gas is exhausted from the etching gas exhaust port 10.
次にエツチング用電極８をエツチング用電極駆動部１１
により移動させ、半導体基板３の裏面の絶縁膜かエツチ
ングされた部分に接触された俺に、スイッチ１３を閉じ
、成膜用ガス導入口４より成膜用ガスを導入しながら保
持電極２１Ａと対向ｔｉ２０との間に放電用電源５によ
り高電圧を印加して成膜を行なう。この時、半導体基板
３裏面の絶縁膜をエツチングにて取り去った部分に保持
電極２１Ａと電気的に接続されたエツチング用電極８を
接触させている為に、半導体基板３に集中するプラズマ
密度は、プラズマＣＶＤより前の工程でウェハー裏面に
形成された絶縁膜により影響されることなく、どんな半
導体基板においても一定となるため、膜厚及び膜質の均
一な膜を成長させることが出来る。尚第１図において６
は半導体基板加熱用のヒーター、７は成膜用ガス排気口
である。Next, the etching electrode 8 is moved to the etching electrode drive unit 11.
When the switch 13 is closed and the film-forming gas is introduced from the film-forming gas inlet 4, the electrode is faced to the holding electrode 21A. A high voltage is applied between the discharge power supply 5 and the discharge power source 5 to form a film. At this time, since the etching electrode 8 electrically connected to the holding electrode 21A is brought into contact with the part where the insulating film on the back surface of the semiconductor substrate 3 has been removed by etching, the plasma density concentrated on the semiconductor substrate 3 is as follows. It is not affected by the insulating film formed on the back surface of the wafer in a step before plasma CVD and is constant on any semiconductor substrate, so it is possible to grow a film with uniform thickness and quality. In addition, 6 in Figure 1
7 is a heater for heating the semiconductor substrate, and 7 is a gas exhaust port for film formation.
第２図は本発明の第２の実施例の模式断面図である。FIG. 2 is a schematic sectional view of a second embodiment of the invention.
本実施例では放電用電源５の出力にスイッチ１３と連動
する切り替えスイッチ１４を設けてこの切り替えスイッ
チ１４を半導体基板３の裏面工・・ｌチング時には端子
Ｅの方に、モして成膜時には端子りの方に切り替えるこ
とにより、半導体基板裏面のエツチング、及び成膜を１
つの放電用電源５により行なえる様にしたもので、その
他は第１の実施例と同様である。In this embodiment, a changeover switch 14 that is connected to the switch 13 is provided at the output of the discharge power source 5, and the changeover switch 14 is connected to the terminal E when processing the back side of the semiconductor substrate 3, and when forming a film. By switching to the terminal type, etching and film formation on the back side of the semiconductor substrate can be done in one step.
This embodiment can be performed using one discharge power source 5, and the rest is the same as the first embodiment.
尚、水弟２の実施例においても第１の実施例と同様の効
果を得ることが出来るが、水弟２の実施例は放電用の電
源を１台少くすることが出来るという利点を有している
。In addition, although the same effect as the first embodiment can be obtained in the embodiment of Suiden 2, the embodiment of Suiden 2 has the advantage that the number of power supplies for discharging can be reduced by one. ing.
以上説明した様に本発明は、半導体基板を保持する保持
電極を円筒状とし、その内部に半導体基板裏面との間に
エツチングガスを導入しながら、放電を生じさせ、半導
体基板裏面をドライエツチングするエツチング用電極と
、保持電極とエツチングされた半導体基板の裏面を電気
的に接続する手段を設けることにより、プラズマＣＶＤ
工程前の工程で半導体基板の裏面に絶縁膜が形成されて
も、その影響を受けることなく膜厚及び膜質の均一な膜
を成長することが出来るため、半導体装置の歩留りを向
上させる効果かある。As explained above, the present invention has a cylindrical holding electrode that holds a semiconductor substrate, and while introducing an etching gas into the inside of the holding electrode between it and the back surface of the semiconductor substrate, discharge is generated to dry-etch the back surface of the semiconductor substrate. By providing means for electrically connecting the etching electrode and the holding electrode to the back surface of the etched semiconductor substrate, plasma CVD
Even if an insulating film is formed on the back side of the semiconductor substrate in the process before the process, it is possible to grow a film with uniform thickness and quality without being affected by the insulating film, which has the effect of improving the yield of semiconductor devices. .
第１図は本発明の第１の実施例の模式断面図、第２図は
本発明の第２の実施例の模式断面図、第３（２１は従来
のプラズマＣＶＤ装置の模式断面図である。
１・・・真空処理容器、３・・・半導体基板、４・・・
成膜用ガス導入口、５・・・放電用電源、６・・・ヒー
ター７・・・成膜用ガス排気口、８・・・エツチング用
電極、９・・・エツチングガス導入口、１０・・・エツ
チングガス排気口、１１・・・エツチング用電極駆動部
、１２・・・エツチング用電源、１３・・・スイッチ、
１４・・・切替スイッチ、２０・・・対向電極、２１．
２１Ａ・・・保持電極。Fig. 1 is a schematic sectional view of the first embodiment of the present invention, Fig. 2 is a schematic sectional view of the second embodiment of the invention, and the third figure (21 is a schematic sectional view of a conventional plasma CVD apparatus). 1... Vacuum processing container, 3... Semiconductor substrate, 4...
Film forming gas inlet, 5... Discharge power supply, 6... Heater 7... Film forming gas exhaust port, 8... Etching electrode, 9... Etching gas inlet, 10. ... Etching gas exhaust port, 11... Etching electrode drive unit, 12... Etching power supply, 13... Switch,
14... Changeover switch, 20... Counter electrode, 21.
21A...Holding electrode.
Claims (1)
極に対向して設けられた対向電極と、前記保持電極の内
側に設けられエッチングガスを噴出させ放電により半導
体基板の裏面をエッチングするためのエッチング用電極
と、前記エッチングされた半導体基板の裏面と前記保持
電極とを電気的に接続する手段とを含むことを特徴とす
るプラズマＣＶＤ装置。A cylindrical holding electrode for holding a semiconductor substrate, a counter electrode provided opposite to the holding electrode, and a counter electrode provided inside the holding electrode for jetting etching gas and etching the back surface of the semiconductor substrate by discharge. A plasma CVD apparatus comprising an etching electrode and means for electrically connecting the etched back surface of the semiconductor substrate and the holding electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2366190A JPH03228321A (en) | 1990-02-02 | 1990-02-02 | Plasma cvd device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2366190A JPH03228321A (en) | 1990-02-02 | 1990-02-02 | Plasma cvd device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03228321A true JPH03228321A (en) | 1991-10-09 |
Family
ID=12116683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2366190A Pending JPH03228321A (en) | 1990-02-02 | 1990-02-02 | Plasma cvd device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03228321A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0668609A2 (en) * | 1994-02-22 | 1995-08-23 | Siemens Aktiengesellschaft | Process for plasma etching the backside of a semiconductor wafer, the front surface not being coated with a protective resin |
| DE19502777A1 (en) * | 1994-02-22 | 1995-08-24 | Siemens Ag | Method for plasma-assisted backside etching of a semiconductor wafer in the case of a lacquer-free front surface of a pane |
| WO2008108603A1 (en) * | 2007-03-08 | 2008-09-12 | Sosul Co., Ltd. | Apparatus for etching a substrate |
| WO2008114958A1 (en) * | 2007-03-16 | 2008-09-25 | Sosul Co., Ltd. | Apparatus for plasma processing and method for plasma processing |
| KR101333521B1 (en) * | 2007-04-13 | 2013-11-28 | (주)소슬 | Apparatus for plasma treatment |
-
1990
- 1990-02-02 JP JP2366190A patent/JPH03228321A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0668609A2 (en) * | 1994-02-22 | 1995-08-23 | Siemens Aktiengesellschaft | Process for plasma etching the backside of a semiconductor wafer, the front surface not being coated with a protective resin |
| DE19502777A1 (en) * | 1994-02-22 | 1995-08-24 | Siemens Ag | Method for plasma-assisted backside etching of a semiconductor wafer in the case of a lacquer-free front surface of a pane |
| EP0668609A3 (en) * | 1994-02-22 | 1997-04-23 | Siemens Ag | Process for plasma etching the backside of a semiconductor wafer, the front surface not being coated with a protective resin. |
| WO2008108603A1 (en) * | 2007-03-08 | 2008-09-12 | Sosul Co., Ltd. | Apparatus for etching a substrate |
| WO2008114958A1 (en) * | 2007-03-16 | 2008-09-25 | Sosul Co., Ltd. | Apparatus for plasma processing and method for plasma processing |
| US8888950B2 (en) | 2007-03-16 | 2014-11-18 | Charm Engineering Co., Ltd. | Apparatus for plasma processing and method for plasma processing |
| KR101333521B1 (en) * | 2007-04-13 | 2013-11-28 | (주)소슬 | Apparatus for plasma treatment |
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